From: "Lodes, Jim" <[email protected]>
The DDC scl high and low times were set to the minimum values
from the i2c specification, but the i2c specification takes into
account the rise time and fall time to calculate the frequency.
To pass HDMI certification DDC can not exceed 100kHz therefore in
a system where the rise times and fall times are negligible the high
and low times for scl need to be 10us.
Signed-off-by: Lodes, Jim <[email protected]>
Signed-off-by: J.D. Schroeder <[email protected]>
---
drivers/gpu/drm/omapdrm/dss/hdmi5_core.c | 4 ++--
drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c b/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
index 6a39752..d993f78 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
@@ -51,8 +51,8 @@ static void hdmi_core_ddc_init(struct hdmi_core_data *core)
{
void __iomem *base = core->base;
const unsigned long long iclk = 266000000; /* DSS L3 ICLK */
- const unsigned ss_scl_high = 4000; /* ns */
- const unsigned ss_scl_low = 4700; /* ns */
+ const unsigned ss_scl_high = 4600; /* ns */
+ const unsigned ss_scl_low = 5400; /* ns */
const unsigned fs_scl_high = 600; /* ns */
const unsigned fs_scl_low = 1300; /* ns */
const unsigned sda_hold = 1000; /* ns */
diff --git a/drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c b/drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c
index 8ea531d..f3e4b81 100644
--- a/drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c
+++ b/drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c
@@ -51,8 +51,8 @@ static void hdmi_core_ddc_init(struct hdmi_core_data *core)
{
void __iomem *base = core->base;
const unsigned long long iclk = 266000000; /* DSS L3 ICLK */
- const unsigned ss_scl_high = 4000; /* ns */
- const unsigned ss_scl_low = 4700; /* ns */
+ const unsigned ss_scl_high = 4600; /* ns */
+ const unsigned ss_scl_low = 5400; /* ns */
const unsigned fs_scl_high = 600; /* ns */
const unsigned fs_scl_low = 1300; /* ns */
const unsigned sda_hold = 1000; /* ns */
--
1.9.1
Hi,
On 21/04/16 03:02, J.D. Schroeder wrote:
> From: "Lodes, Jim" <[email protected]>
>
> The DDC scl high and low times were set to the minimum values
> from the i2c specification, but the i2c specification takes into
> account the rise time and fall time to calculate the frequency.
> To pass HDMI certification DDC can not exceed 100kHz therefore in
> a system where the rise times and fall times are negligible the high
> and low times for scl need to be 10us.
Thanks, makes sense. Did you measure the rise & fall times? Do you get
more or less exactly 100kHz with the new times?
> Signed-off-by: Lodes, Jim <[email protected]>
The email format should be
Firstname Lastname <[email protected]>
Or something similar, but not "Lastname, Firstname"
Tomi
On 04/21/2016 09:38 AM, Tomi Valkeinen wrote:
> Thanks, makes sense. Did you measure the rise & fall times? Do you get
> more or less exactly 100kHz with the new times?
Rise time is around 600 nsec and fall time is around 140 nsec. When the clock frequency is measured we get right at 100 kHz and the rise and fall times are negligible. When the HDMI certification test equipment is attached it is just slightly less than 100 kHz, which is okay. The HDMI specification states less than 100 kHz is acceptable not greater. If a particular system has slower rise and fall times then that should be okay also. This change ensures that we stay below 100 kHz regardless of the rise and fall times.
>> Signed-off-by: Lodes, Jim <[email protected]>
>
> The email format should be
>
> Firstname Lastname <[email protected]>
Yes. I'll fix the email and resubmit.
From: Jim Lodes <[email protected]>
The DDC scl high and low times were set to the minimum values
from the i2c specification, but the i2c specification takes into
account the rise time and fall time to calculate the frequency.
To pass HDMI certification DDC can not exceed 100kHz therefore in
a system where the rise times and fall times are negligible the high
and low times for scl need to be 10us.
Signed-off-by: Jim Lodes <[email protected]>
Signed-off-by: J.D. Schroeder <[email protected]>
---
drivers/gpu/drm/omapdrm/dss/hdmi5_core.c | 4 ++--
drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c b/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
index 6a39752..d993f78 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
@@ -51,8 +51,8 @@ static void hdmi_core_ddc_init(struct hdmi_core_data *core)
{
void __iomem *base = core->base;
const unsigned long long iclk = 266000000; /* DSS L3 ICLK */
- const unsigned ss_scl_high = 4000; /* ns */
- const unsigned ss_scl_low = 4700; /* ns */
+ const unsigned ss_scl_high = 4600; /* ns */
+ const unsigned ss_scl_low = 5400; /* ns */
const unsigned fs_scl_high = 600; /* ns */
const unsigned fs_scl_low = 1300; /* ns */
const unsigned sda_hold = 1000; /* ns */
diff --git a/drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c b/drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c
index 8ea531d..f3e4b81 100644
--- a/drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c
+++ b/drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c
@@ -51,8 +51,8 @@ static void hdmi_core_ddc_init(struct hdmi_core_data *core)
{
void __iomem *base = core->base;
const unsigned long long iclk = 266000000; /* DSS L3 ICLK */
- const unsigned ss_scl_high = 4000; /* ns */
- const unsigned ss_scl_low = 4700; /* ns */
+ const unsigned ss_scl_high = 4600; /* ns */
+ const unsigned ss_scl_low = 5400; /* ns */
const unsigned fs_scl_high = 600; /* ns */
const unsigned fs_scl_low = 1300; /* ns */
const unsigned sda_hold = 1000; /* ns */
--
1.9.1
On 21/04/16 20:27, J.D. Schroeder wrote:
> From: Jim Lodes <[email protected]>
>
> The DDC scl high and low times were set to the minimum values
> from the i2c specification, but the i2c specification takes into
> account the rise time and fall time to calculate the frequency.
> To pass HDMI certification DDC can not exceed 100kHz therefore in
> a system where the rise times and fall times are negligible the high
> and low times for scl need to be 10us.
>
> Signed-off-by: Jim Lodes <[email protected]>
> Signed-off-by: J.D. Schroeder <[email protected]>
> ---
> drivers/gpu/drm/omapdrm/dss/hdmi5_core.c | 4 ++--
> drivers/video/fbdev/omap2/omapfb/dss/hdmi5_core.c | 4 ++--
> 2 files changed, 4 insertions(+), 4 deletions(-)
Thanks! Queuing this for 4.7.
Tomi