2016-10-21 04:10:17

by Xing Zheng

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Subject: [PATCH] clk: rockchip: add 533.25MHz to rk3399 clock rates table

We need to get the accurate 533.25MHz for the DP display.

Signed-off-by: Xing Zheng <[email protected]>
---

drivers/clk/rockchip/clk-rk3399.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 2c7cba7..a87cb49 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -93,6 +93,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0),
RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
RK3036_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0),
+ RK3036_PLL_RATE( 533250000, 8, 711, 4, 1, 1, 0),
RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
--
2.7.4



2016-10-21 07:47:54

by Heiko Stuebner

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Subject: Re: [PATCH] clk: rockchip: add 533.25MHz to rk3399 clock rates table

Am Freitag, 21. Oktober 2016, 12:03:40 CEST schrieb Xing Zheng:
> We need to get the accurate 533.25MHz for the DP display.
>
> Signed-off-by: Xing Zheng <[email protected]>

applied to my clk-branch for 4.10


Thanks
Heiko