The Allwinner A10/A20 SoCs have an on-board CAN (Controller Area Network)
controller. This patch adds the CAN core to the SoC's include files,
sun4i-a10.dtsi and sun7i-a20.dtsi.
On linux-can mailing list was a discussion about updating the device tree bindings
https://lkml.org/lkml/2015/9/17/220
but it did not progress past writing the documentation file.
Documentation/devicetree/bindings/net/can/sun4i_can.txt
The CAN controller can be enabled in a board specific dts file as
described in the documentation file or by using a device tree overlay.
I have tested the patch on a Banana Pi (A20 SoC) with mainline kernel 4.9.13.
Patrick Menschel (2):
ARM: dts: sun4i: Add CAN node and can0_pins_a pinctrl settings
ARM: dts: sun7i: Add CAN node and can0_pins_a pinctrl settings
arch/arm/boot/dts/sun4i-a10.dtsi | 15 +++++++++++++++
arch/arm/boot/dts/sun7i-a20.dtsi | 15 +++++++++++++++
2 files changed, 30 insertions(+)
--
1.9.1
The A20 SoC has an on-board CAN controller. This patch adds the device node
and the corresponding pinctrl settings for pins PH20 and PH21.
The CAN controller is inherited from the A10 SoC and uses the same driver.
This patch is adapted from the description in
Documentation/devicetree/bindings/net/can/sun4i_can.txt
Signed-off-by: Patrick Menschel <[email protected]>
---
arch/arm/boot/dts/sun7i-a20.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index f7db067..a0417c0 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -1390,6 +1390,13 @@
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+
+ can0_pins_a: can0@0 {
+ allwinner,pins = "PH20","PH21";
+ allwinner,function = "can";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
};
timer@01c20c00 {
@@ -1711,5 +1718,13 @@
clocks = <&apb1_gates 7>;
status = "disabled";
};
+
+ can0: can@01c2bc00 {
+ compatible = "allwinner,sun4i-a10-can";
+ reg = <0x01c2bc00 0x400>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apb1_gates 4>;
+ status = "disabled";
+ };
};
};
--
1.9.1
The A10 SoC has an on-board CAN controller. This patch adds the device node
and the corresponding pinctrl settings for pins PH20 and PH21.
This patch is adapted from the description in
Documentation/devicetree/bindings/net/can/sun4i_can.txt
Signed-off-by: Patrick Menschel <[email protected]>
---
arch/arm/boot/dts/sun4i-a10.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index b14a428..210b616 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -1160,6 +1160,13 @@
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+
+ can0_pins_a: can0@0 {
+ allwinner,pins = "PH20","PH21";
+ allwinner,function = "can";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
};
timer@01c20c00 {
@@ -1376,5 +1383,13 @@
clocks = <&apb1_gates 7>;
status = "disabled";
};
+
+ can0: can@01c2bc00 {
+ compatible = "allwinner,sun4i-a10-can";
+ reg = <0x01c2bc00 0x400>;
+ interrupts = <26>;
+ clocks = <&apb1_gates 4>;
+ status = "disabled";
+ };
};
};
--
1.9.1
Hi Patrick,
On Sun, Mar 12, 2017 at 02:28:10PM +0100, Patrick Menschel wrote:
> The A10 SoC has an on-board CAN controller. This patch adds the device node
> and the corresponding pinctrl settings for pins PH20 and PH21.
>
> This patch is adapted from the description in
> Documentation/devicetree/bindings/net/can/sun4i_can.txt
>
> Signed-off-by: Patrick Menschel <[email protected]>
> ---
> arch/arm/boot/dts/sun4i-a10.dtsi | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
> index b14a428..210b616 100644
> --- a/arch/arm/boot/dts/sun4i-a10.dtsi
> +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
> @@ -1160,6 +1160,13 @@
> allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
> };
> +
> + can0_pins_a: can0@0 {
That should be ordered by alphabetical order.
> + allwinner,pins = "PH20","PH21";
> + allwinner,function = "can";
> + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
> + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
We've switched to a new, generic, binding recently for the pinctrl
nodes.
In your case, that would mean dropping "allwinner," from the pins and
functions properties, and droping the last two properties entirely.
> + };
> };
>
> timer@01c20c00 {
> @@ -1376,5 +1383,13 @@
> clocks = <&apb1_gates 7>;
> status = "disabled";
> };
> +
> + can0: can@01c2bc00 {
And this one should be ordered by rising physical addresses.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com