2017-06-22 08:43:59

by Erin Lo

[permalink] [raw]
Subject: [PATCH v2 0/4] Add some DT nodes for Mediatek MT2701

This patch series based on v4.12-rc1, include MT2701 ethernet/disp bls/display function DT nodes.

Change in v2:
1. Add reset properties in ethernet nodes
2. Split bls nodes into two patches for dtsi and actual board
3. Remove redundant dispsys@14000000 node

Sean Wang (1):
arm: dts: mt2701: Add ethernet device node

Weiqing Kong (2):
arm: dts: mt2701: Add display bls related nodes for MT2701
arm: dts: mt2701: Add display bls related nodes for MT2701

YT Shen (1):
arm: dts: mt2701: Add display subsystem related nodes for MT2701

arch/arm/boot/dts/mt2701-evb.dts | 29 ++++++++++
arch/arm/boot/dts/mt2701.dtsi | 117 +++++++++++++++++++++++++++++++++++++++
2 files changed, 146 insertions(+)

--
1.9.1


2017-06-22 08:44:02

by Erin Lo

[permalink] [raw]
Subject: [PATCH v2 1/4] arm: dts: mt2701: Add ethernet device node

From: Sean Wang <[email protected]>

Add ethernet device node for MT2701

Signed-off-by: Sean Wang <[email protected]>
Signed-off-by: Erin Lo <[email protected]>
---
arch/arm/boot/dts/mt2701.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 8037210..91ed40d 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -420,6 +420,30 @@
#clock-cells = <1>;
};

+ eth: ethernet@1b100000 {
+ compatible = "mediatek,mt2701-eth", "syscon";
+ reg = <0 0x1b100000 0 0x20000>;
+ interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
+ <&ethsys CLK_ETHSYS_ESW>,
+ <&ethsys CLK_ETHSYS_GP1>,
+ <&ethsys CLK_ETHSYS_GP2>,
+ <&apmixedsys CLK_APMIXED_TRGPLL>;
+ clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
+ resets = <&ethsys MT2701_ETHSYS_FE_RST>,
+ <&ethsys MT2701_ETHSYS_GMAC_RST>,
+ <&ethsys MT2701_ETHSYS_PPE_RST>;
+ reset-names = "fe", "gmac", "ppe";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
+ mediatek,ethsys = <&ethsys>;
+ mediatek,pctl = <&syscfg_pctl_a>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
bdpsys: syscon@1c000000 {
compatible = "mediatek,mt2701-bdpsys", "syscon";
reg = <0 0x1c000000 0 0x1000>;
--
1.9.1

2017-06-22 08:44:13

by Erin Lo

[permalink] [raw]
Subject: [PATCH v2 3/4] arm: dts: mt2701: Add display bls related nodes for MT2701

From: Weiqing Kong <[email protected]>

This patch adds board related config for backlight

Signed-off-by: Weiqing Kong <[email protected]>
Signed-off-by: Erin Lo <[email protected]>
---
arch/arm/boot/dts/mt2701-evb.dts | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)

diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts
index a483798..e49c2b7 100644
--- a/arch/arm/boot/dts/mt2701-evb.dts
+++ b/arch/arm/boot/dts/mt2701-evb.dts
@@ -22,6 +22,35 @@
memory {
reg = <0 0x80000000 0 0x40000000>;
};
+
+ backlight_lcd: backlight_lcd {
+ compatible = "pwm-backlight";
+ pwms = <&bls 0 100000>;
+ brightness-levels = <
+ 0 16 32 48 64 80 96 112
+ 128 144 160 176 192 208 224 240
+ 255
+ >;
+ default-brightness-level = <9>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_bls_gpio>;
+ };
+};
+
+&bls {
+ status = "okay";
+};
+
+&mmsys {
+ status = "okay";
+};
+
+&pio {
+ pwm_bls_gpio: pwm_bls_gpio {
+ pins_cmd_dat {
+ pinmux = <MT2701_PIN_208_AUD_EXT_CK1__FUNC_DISP_PWM>;
+ };
+ };
};

&auxadc {
--
1.9.1

2017-06-22 08:44:32

by Erin Lo

[permalink] [raw]
Subject: [PATCH v2 4/4] arm: dts: mt2701: Add display subsystem related nodes for MT2701

From: YT Shen <[email protected]>

This patch adds the device nodes for the DISP function blocks for MT2701

Signed-off-by: YT Shen <[email protected]>
Signed-off-by: Erin Lo <[email protected]>
---
arch/arm/boot/dts/mt2701.dtsi | 84 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 84 insertions(+)

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 8e574a0..150c4c7 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -17,6 +17,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/mt2701-resets.h>
+#include <dt-bindings/memory/mt2701-larb-port.h>
#include "skeleton64.dtsi"
#include "mt2701-pinfunc.h"

@@ -24,6 +25,11 @@
compatible = "mediatek,mt2701";
interrupt-parent = <&sysirq>;

+ aliases {
+ rdma0 = &rdma0;
+ rdma1 = &rdma1;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -201,6 +207,16 @@
power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
};

+ mipi_tx0: mipi-dphy@10010000 {
+ compatible = "mediatek,mt2701-mipi-tx";
+ reg = <0 0x10010000 0 0x90>;
+ clocks = <&clk26m>;
+ clock-output-names = "mipi_tx0_pll";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
sysirq: interrupt-controller@10200100 {
compatible = "mediatek,mt2701-sysirq",
"mediatek,mt6577-sysirq";
@@ -366,6 +382,39 @@
#clock-cells = <1>;
};

+ display_components: dispsys@14000000 {
+ compatible = "mediatek,mt2701-mmsys";
+ reg = <0 0x14000000 0 0x1000>;
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
+ };
+
+ ovl@14007000 {
+ compatible = "mediatek,mt2701-disp-ovl";
+ reg = <0 0x14007000 0 0x1000>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&mmsys CLK_MM_DISP_OVL>;
+ iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ rdma0: rdma@14008000 {
+ compatible = "mediatek,mt2701-disp-rdma";
+ reg = <0 0x14008000 0 0x1000>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA>;
+ iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>;
+ mediatek,larb = <&larb0>;
+ };
+
+ wdma@14009000 {
+ compatible = "mediatek,mt2701-disp-wdma";
+ reg = <0 0x14009000 0 0x1000>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&mmsys CLK_MM_DISP_WDMA>;
+ iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>;
+ mediatek,larb = <&larb0>;
+ };
+
bls: bls@1400a000 {
compatible = "mediatek,mt2701-disp-pwm";
reg = <0 0x1400a000 0 0x1000>;
@@ -375,6 +424,32 @@
status = "disabled";
};

+ color@1400b000 {
+ compatible = "mediatek,mt2701-disp-color";
+ reg = <0 0x1400b000 0 0x1000>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&mmsys CLK_MM_DISP_COLOR>;
+ };
+
+ dsi: dsi@1400c000 {
+ compatible = "mediatek,mt2701-dsi";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&mmsys CLK_MM_DSI_ENGINE>, <&mmsys CLK_MM_DSI_DIG>,
+ <&mipi_tx0>;
+ clock-names = "engine", "digital", "hs";
+ phys = <&mipi_tx0>;
+ phy-names = "dphy";
+ status = "disabled";
+ };
+
+ mutex: mutex@1400e000 {
+ compatible = "mediatek,mt2701-disp-mutex";
+ reg = <0 0x1400e000 0 0x1000>;
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&mmsys CLK_MM_MUTEX_32K>;
+ };
+
larb0: larb@14010000 {
compatible = "mediatek,mt2701-smi-larb";
reg = <0 0x14010000 0 0x1000>;
@@ -385,6 +460,15 @@
power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
};

+ rdma1: rdma@14012000 {
+ compatible = "mediatek,mt2701-disp-rdma";
+ reg = <0 0x14012000 0 0x1000>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA1>;
+ iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>;
+ mediatek,larb = <&larb0>;
+ };
+
imgsys: syscon@15000000 {
compatible = "mediatek,mt2701-imgsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
--
1.9.1

2017-06-22 08:44:11

by Erin Lo

[permalink] [raw]
Subject: [PATCH v2 2/4] arm: dts: mt2701: Add display bls related nodes for MT2701

From: Weiqing Kong <[email protected]>

This patch adds the device node of display backlight for MT2701

Signed-off-by: Weiqing Kong <[email protected]>
Signed-off-by: Erin Lo <[email protected]>
---
arch/arm/boot/dts/mt2701.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 91ed40d..8e574a0 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -366,6 +366,15 @@
#clock-cells = <1>;
};

+ bls: bls@1400a000 {
+ compatible = "mediatek,mt2701-disp-pwm";
+ reg = <0 0x1400a000 0 0x1000>;
+ #pwm-cells = <2>;
+ clocks = <&mmsys CLK_MM_MDP_BLS_26M>, <&mmsys CLK_MM_DISP_BLS>;
+ clock-names = "main", "mm";
+ status = "disabled";
+ };
+
larb0: larb@14010000 {
compatible = "mediatek,mt2701-smi-larb";
reg = <0 0x14010000 0 0x1000>;
--
1.9.1

2017-06-22 09:27:37

by Yingjoe Chen

[permalink] [raw]
Subject: Re: [PATCH v2 3/4] arm: dts: mt2701: Add display bls related nodes for MT2701

On Thu, 2017-06-22 at 16:43 +0800, Erin Lo wrote:
> From: Weiqing Kong <[email protected]>
>
> This patch adds board related config for backlight
>
> Signed-off-by: Weiqing Kong <[email protected]>
> Signed-off-by: Erin Lo <[email protected]>
> ---
> arch/arm/boot/dts/mt2701-evb.dts | 29 +++++++++++++++++++++++++++++
> 1 file changed, 29 insertions(+)
>
> diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts
> index a483798..e49c2b7 100644
> --- a/arch/arm/boot/dts/mt2701-evb.dts
> +++ b/arch/arm/boot/dts/mt2701-evb.dts

<...>

> +
> +&bls {
> + status = "okay";
> +};
> +
> +&mmsys {
> + status = "okay";
> +};
> +
> +&pio {
> + pwm_bls_gpio: pwm_bls_gpio {
> + pins_cmd_dat {
> + pinmux = <MT2701_PIN_208_AUD_EXT_CK1__FUNC_DISP_PWM>;
> + };
> + };
> };
>
> &auxadc {


To help merge, I think this should be sorted according to name.

Joe.C




2017-06-23 02:10:46

by Weiqing Kong

[permalink] [raw]
Subject: Re: [PATCH v2 3/4] arm: dts: mt2701: Add display bls related nodes for MT2701

On Thu, 2017-06-22 at 17:27 +0800, Yingjoe Chen wrote:
> On Thu, 2017-06-22 at 16:43 +0800, Erin Lo wrote:
> > From: Weiqing Kong <[email protected]>
> >
> > This patch adds board related config for backlight
> >
> > Signed-off-by: Weiqing Kong <[email protected]>
> > Signed-off-by: Erin Lo <[email protected]>
> > ---
> > arch/arm/boot/dts/mt2701-evb.dts | 29 +++++++++++++++++++++++++++++
> > 1 file changed, 29 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/mt2701-evb.dts b/arch/arm/boot/dts/mt2701-evb.dts
> > index a483798..e49c2b7 100644
> > --- a/arch/arm/boot/dts/mt2701-evb.dts
> > +++ b/arch/arm/boot/dts/mt2701-evb.dts
>
> <...>
>
> > +
> > +&bls {
> > + status = "okay";
> > +};
> > +
> > +&mmsys {
> > + status = "okay";
> > +};
> > +
> > +&pio {
> > + pwm_bls_gpio: pwm_bls_gpio {
> > + pins_cmd_dat {
> > + pinmux = <MT2701_PIN_208_AUD_EXT_CK1__FUNC_DISP_PWM>;
> > + };
> > + };
> > };
> >
> > &auxadc {
>
>
> To help merge, I think this should be sorted according to name.
>
> Joe.C

Thanks for your advice, I will refine this patch as quickly.

Weiqing Kong
>
>
>
>


2017-06-23 04:13:08

by Erin Lo

[permalink] [raw]
Subject: Re: [PATCH v2 4/4] arm: dts: mt2701: Add display subsystem related nodes for MT2701

On Thu, 2017-06-22 at 16:43 +0800, Erin Lo wrote:
> From: YT Shen <[email protected]>
>
> This patch adds the device nodes for the DISP function blocks for MT2701
>
> Signed-off-by: YT Shen <[email protected]>
> Signed-off-by: Erin Lo <[email protected]>
> ---
> arch/arm/boot/dts/mt2701.dtsi | 84 +++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 84 insertions(+)
>
> diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> index 8e574a0..150c4c7 100644
> --- a/arch/arm/boot/dts/mt2701.dtsi
> +++ b/arch/arm/boot/dts/mt2701.dtsi
> @@ -17,6 +17,7 @@
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/reset/mt2701-resets.h>
> +#include <dt-bindings/memory/mt2701-larb-port.h>
> #include "skeleton64.dtsi"
> #include "mt2701-pinfunc.h"
>
> @@ -24,6 +25,11 @@
> compatible = "mediatek,mt2701";
> interrupt-parent = <&sysirq>;
>
> + aliases {
> + rdma0 = &rdma0;
> + rdma1 = &rdma1;
> + };
> +
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -201,6 +207,16 @@
> power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> };
>
> + mipi_tx0: mipi-dphy@10010000 {
> + compatible = "mediatek,mt2701-mipi-tx";
> + reg = <0 0x10010000 0 0x90>;
> + clocks = <&clk26m>;
> + clock-output-names = "mipi_tx0_pll";
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> +
> sysirq: interrupt-controller@10200100 {
> compatible = "mediatek,mt2701-sysirq",
> "mediatek,mt6577-sysirq";
> @@ -366,6 +382,39 @@
> #clock-cells = <1>;
> };
>
> + display_components: dispsys@14000000 {
> + compatible = "mediatek,mt2701-mmsys";
> + reg = <0 0x14000000 0 0x1000>;
> + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> + };

Sorry for the edition error, I will remove this node in next version.
Regards,
Erin

> +
> + ovl@14007000 {
> + compatible = "mediatek,mt2701-disp-ovl";
> + reg = <0 0x14007000 0 0x1000>;
> + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&mmsys CLK_MM_DISP_OVL>;
> + iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>;
> + mediatek,larb = <&larb0>;
> + };
> +
> + rdma0: rdma@14008000 {
> + compatible = "mediatek,mt2701-disp-rdma";
> + reg = <0 0x14008000 0 0x1000>;
> + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&mmsys CLK_MM_DISP_RDMA>;
> + iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>;
> + mediatek,larb = <&larb0>;
> + };
> +
> + wdma@14009000 {
> + compatible = "mediatek,mt2701-disp-wdma";
> + reg = <0 0x14009000 0 0x1000>;
> + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&mmsys CLK_MM_DISP_WDMA>;
> + iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>;
> + mediatek,larb = <&larb0>;
> + };
> +
> bls: bls@1400a000 {
> compatible = "mediatek,mt2701-disp-pwm";
> reg = <0 0x1400a000 0 0x1000>;
> @@ -375,6 +424,32 @@
> status = "disabled";
> };
>
> + color@1400b000 {
> + compatible = "mediatek,mt2701-disp-color";
> + reg = <0 0x1400b000 0 0x1000>;
> + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&mmsys CLK_MM_DISP_COLOR>;
> + };
> +
> + dsi: dsi@1400c000 {
> + compatible = "mediatek,mt2701-dsi";
> + reg = <0 0x1400c000 0 0x1000>;
> + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&mmsys CLK_MM_DSI_ENGINE>, <&mmsys CLK_MM_DSI_DIG>,
> + <&mipi_tx0>;
> + clock-names = "engine", "digital", "hs";
> + phys = <&mipi_tx0>;
> + phy-names = "dphy";
> + status = "disabled";
> + };
> +
> + mutex: mutex@1400e000 {
> + compatible = "mediatek,mt2701-disp-mutex";
> + reg = <0 0x1400e000 0 0x1000>;
> + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&mmsys CLK_MM_MUTEX_32K>;
> + };
> +
> larb0: larb@14010000 {
> compatible = "mediatek,mt2701-smi-larb";
> reg = <0 0x14010000 0 0x1000>;
> @@ -385,6 +460,15 @@
> power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> };
>
> + rdma1: rdma@14012000 {
> + compatible = "mediatek,mt2701-disp-rdma";
> + reg = <0 0x14012000 0 0x1000>;
> + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> + iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>;
> + mediatek,larb = <&larb0>;
> + };
> +
> imgsys: syscon@15000000 {
> compatible = "mediatek,mt2701-imgsys", "syscon";
> reg = <0 0x15000000 0 0x1000>;