The rk3228 and rk3328 support internal mac phy inside, let's enable
it to work. And the internal phy need to do some special setting, so
register the rockchip mac internal phy driver, not use the genphy driver.
David Wu (11):
net: phy: Add rockchip phy driver support
multi_v7_defconfig: Make rockchip mac phy built-in
arm64: defconfig: Enable CONFIG_ROCKCHIP_MAC_PHY
net: stmmac: dwmac-rk: Remove unwanted code for rk3328_set_to_rmii()
net: stmmac: dwmac-rk: Add internal phy support
net: stmmac: dwmac-rk: Add internal phy support for rk3228
net: stmmac: dwmac-rk: Add internal phy supprot for rk3328
ARM: dts: rk322x: Add support internal phy for gmac
ARM: dts: rk3228-evb: Enable the internal phy for gmac
ARM64: dts: rockchip: Add gmac2phy node support for rk3328
ARM64: dts: rockchip: Enable gmac2phy for rk3328-evb
.../devicetree/bindings/net/rockchip-dwmac.txt | 3 +
arch/arm/boot/dts/rk3228-evb.dts | 20 ++++
arch/arm/boot/dts/rk322x.dtsi | 8 +-
arch/arm/configs/multi_v7_defconfig | 1 +
arch/arm64/boot/dts/rockchip/rk3328-evb.dts | 17 +++
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 25 +++++
arch/arm64/configs/defconfig | 1 +
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 123 ++++++++++++++++++++-
drivers/net/phy/Kconfig | 4 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/rockchip.c | 94 ++++++++++++++++
11 files changed, 287 insertions(+), 10 deletions(-)
create mode 100644 drivers/net/phy/rockchip.c
--
1.9.1
Support internal ephy currently.
Signed-off-by: David Wu <[email protected]>
---
drivers/net/phy/Kconfig | 4 ++
drivers/net/phy/Makefile | 1 +
drivers/net/phy/rockchip.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 99 insertions(+)
create mode 100644 drivers/net/phy/rockchip.c
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index c360dd6..86010d4 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -350,6 +350,10 @@ config XILINX_GMII2RGMII
the Reduced Gigabit Media Independent Interface(RGMII) between
Ethernet physical media devices and the Gigabit Ethernet controller.
+config ROCKCHIP_MAC_PHY
+ tristate "Drivers for ROCKCHIP MAC PHY"
+ ---help---
+ Currently supports the mac internal ephy.
endif # PHYLIB
config MICREL_KS8995MA
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index e36db9a..6d96779 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -69,3 +69,4 @@ obj-$(CONFIG_STE10XP) += ste10Xp.o
obj-$(CONFIG_TERANETICS_PHY) += teranetics.o
obj-$(CONFIG_VITESSE_PHY) += vitesse.o
obj-$(CONFIG_XILINX_GMII2RGMII) += xilinx_gmii2rgmii.o
+obj-$(CONFIG_ROCKCHIP_MAC_PHY) += rockchip.o
diff --git a/drivers/net/phy/rockchip.c b/drivers/net/phy/rockchip.c
new file mode 100644
index 0000000..69e96ec
--- /dev/null
+++ b/drivers/net/phy/rockchip.c
@@ -0,0 +1,94 @@
+/**
+ * Rockchip mac phy driver
+ *
+ * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * David Wu<[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mii.h>
+#include <linux/ethtool.h>
+#include <linux/phy.h>
+#include <linux/netdevice.h>
+
+static int internal_config_init(struct phy_device *phydev)
+{
+ int val;
+ u32 features;
+
+ /*enable auto mdix*/
+ phy_write(phydev, 0x11, 0x0080);
+
+ features = (SUPPORTED_TP | SUPPORTED_MII
+ | SUPPORTED_AUI | SUPPORTED_FIBRE |
+ SUPPORTED_BNC);
+
+ /* Do we support autonegotiation? */
+ val = phy_read(phydev, MII_BMSR);
+ if (val < 0)
+ return val;
+
+ if (val & BMSR_ANEGCAPABLE)
+ features |= SUPPORTED_Autoneg;
+
+ if (val & BMSR_100FULL)
+ features |= SUPPORTED_100baseT_Full;
+ if (val & BMSR_100HALF)
+ features |= SUPPORTED_100baseT_Half;
+ if (val & BMSR_10FULL)
+ features |= SUPPORTED_10baseT_Full;
+ if (val & BMSR_10HALF)
+ features |= SUPPORTED_10baseT_Half;
+
+ if (val & BMSR_ESTATEN) {
+ val = phy_read(phydev, MII_ESTATUS);
+ if (val < 0)
+ return val;
+
+ if (val & ESTATUS_1000_TFULL)
+ features |= SUPPORTED_1000baseT_Full;
+ if (val & ESTATUS_1000_THALF)
+ features |= SUPPORTED_1000baseT_Half;
+ }
+
+ phydev->supported = features;
+ phydev->advertising = features;
+
+ return 0;
+}
+
+static struct phy_driver rockchip_phy_driver[] = {
+{
+ .phy_id = 0x1234d400,
+ .phy_id_mask = 0xffffffff,
+ .name = "rockchip internal ephy",
+ .features = 0,
+ .config_init = internal_config_init,
+ .config_aneg = genphy_config_aneg,
+ .read_status = genphy_read_status,
+ .suspend = genphy_suspend,
+ .resume = genphy_resume,
+},
+};
+
+module_phy_driver(rockchip_phy_driver);
+
+static struct mdio_device_id __maybe_unused rockchip_phy_tbl[] = {
+ { 0x1234d400, 0xffffffff },
+ { }
+};
+
+MODULE_DEVICE_TABLE(mdio, rockchip_phy_tbl);
+
+MODULE_AUTHOR("David Wu<[email protected]>");
+MODULE_DESCRIPTION("Rockchip mac phy driver");
+MODULE_LICENSE("GPL v2");
--
1.9.1
Enable the rockchip mac phy for multi_v7_defconfig builds
Signed-off-by: David Wu <[email protected]>
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 2685e03..fc1986c 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -267,6 +267,7 @@ CONFIG_ICPLUS_PHY=y
CONFIG_REALTEK_PHY=y
CONFIG_MICREL_PHY=y
CONFIG_FIXED_PHY=y
+CONFIG_ROCKCHIP_MAC_PHY=y
CONFIG_USB_PEGASUS=y
CONFIG_USB_RTL8152=m
CONFIG_USB_USBNET=y
--
1.9.1
Make the rockchip mac phy driver built into the kernel.
Signed-off-by: David Wu <[email protected]>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 97c123e..b4abe7f 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -195,6 +195,7 @@ CONFIG_MDIO_BUS_MUX_MMIOREG=y
CONFIG_MESON_GXL_PHY=m
CONFIG_MICREL_PHY=y
CONFIG_REALTEK_PHY=m
+CONFIG_ROCKCHIP_MAC_PHY=y
CONFIG_USB_PEGASUS=m
CONFIG_USB_RTL8150=m
CONFIG_USB_RTL8152=m
--
1.9.1
This is wrong setting for rk3328_set_to_rmii(), so remove it.
Change-Id: I9953784ea44335d90710e5473960c95b3d68a5fd
Signed-off-by: David Wu <[email protected]>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index f0df519..a8e8fd5 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -365,9 +365,6 @@ static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
RK3328_GMAC_PHY_INTF_SEL_RMII |
RK3328_GMAC_RMII_MODE);
-
- /* set MAC to RMII mode */
- regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1, GRF_BIT(11));
}
static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
--
1.9.1
To make internal phy worked, need to configure the phy_clock,
phy cru_reset and related registers.
Change-Id: I6971c0a769754b824b1b908b56080cbaf7867d13
Signed-off-by: David Wu <[email protected]>
---
.../devicetree/bindings/net/rockchip-dwmac.txt | 3 +
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 82 ++++++++++++++++++++++
2 files changed, 85 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
index 8f42755..0514f69 100644
--- a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
@@ -22,6 +22,7 @@ Required properties:
<&cru SCLK_MACREF_OUT> clock gate for RMII reference clock output
<&cru ACLK_GMAC>: AXI clock gate for GMAC
<&cru PCLK_GMAC>: APB clock gate for GMAC
+ <&cru MAC_PHY>: clock for internal macphy
- clock-names: One name for each entry in the clocks property.
- phy-mode: See ethernet.txt file in the same directory.
- pinctrl-names: Names corresponding to the numbered pinctrl states.
@@ -35,6 +36,8 @@ Required properties:
- assigned-clocks: main clock, should be <&cru SCLK_MAC>;
- assigned-clock-parents = parent of main clock.
can be <&ext_gmac> or <&cru SCLK_MAC_PLL>.
+ - phy-type: For internal phy, it must be "internal"; For external phy, no need
+ to configure this.
Optional properties:
- tx_delay: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default.
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index a8e8fd5..c1a1413 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -41,6 +41,7 @@ struct rk_gmac_ops {
void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
+ void (*internal_phy_powerup)(struct rk_priv_data *bsp_priv);
};
struct rk_priv_data {
@@ -52,6 +53,7 @@ struct rk_priv_data {
bool clk_enabled;
bool clock_input;
+ bool internal_phy;
struct clk *clk_mac;
struct clk *gmac_clkin;
@@ -61,6 +63,9 @@ struct rk_priv_data {
struct clk *clk_mac_refout;
struct clk *aclk_mac;
struct clk *pclk_mac;
+ struct clk *clk_macphy;
+
+ struct reset_control *macphy_reset;
int tx_delay;
int rx_delay;
@@ -750,6 +755,48 @@ static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
.set_rmii_speed = rk3399_set_rmii_speed,
};
+#define RK_GRF_MACPHY_CON0 0xb00
+#define RK_GRF_MACPHY_CON1 0xb04
+#define RK_GRF_MACPHY_CON2 0xb08
+#define RK_GRF_MACPHY_CON3 0xb0c
+
+#define RK_MACPHY_ENABLE GRF_BIT(0)
+#define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
+#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
+#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7))
+#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0)
+#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0)
+
+static void rk_gmac_internal_phy_powerup(struct rk_priv_data *priv)
+{
+ if (priv->ops->internal_phy_powerup)
+ priv->ops->internal_phy_powerup(priv);
+
+ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
+ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
+
+ regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
+ regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
+
+ /* disable macphy, the default value is enabled */
+ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
+ if (priv->macphy_reset)
+ reset_control_assert(priv->macphy_reset);
+ usleep_range(10, 20);
+ if (priv->macphy_reset)
+ reset_control_deassert(priv->macphy_reset);
+ usleep_range(10, 20);
+ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
+ msleep(30);
+}
+
+static void rk_gmac_internal_phy_powerdown(struct rk_priv_data *priv)
+{
+ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
+ if (priv->macphy_reset)
+ reset_control_assert(priv->macphy_reset);
+}
+
static int gmac_clk_init(struct rk_priv_data *bsp_priv)
{
struct device *dev = &bsp_priv->pdev->dev;
@@ -803,6 +850,14 @@ static int gmac_clk_init(struct rk_priv_data *bsp_priv)
clk_set_rate(bsp_priv->clk_mac, 50000000);
}
+ if (bsp_priv->internal_phy) {
+ bsp_priv->clk_macphy = devm_clk_get(dev, "clk_macphy");
+ if (IS_ERR(bsp_priv->clk_macphy))
+ dev_err(dev, "cannot get %s clock\n", "clk_macphy");
+ else
+ clk_set_rate(bsp_priv->clk_macphy, 50000000);
+ }
+
return 0;
}
@@ -826,6 +881,9 @@ static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
bsp_priv->clk_mac_refout);
}
+ if (!IS_ERR(bsp_priv->clk_macphy))
+ clk_prepare_enable(bsp_priv->clk_macphy);
+
if (!IS_ERR(bsp_priv->aclk_mac))
clk_prepare_enable(bsp_priv->aclk_mac);
@@ -858,6 +916,9 @@ static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
bsp_priv->clk_mac_refout);
}
+ if (!IS_ERR(bsp_priv->clk_macphy))
+ clk_disable_unprepare(bsp_priv->clk_macphy);
+
if (!IS_ERR(bsp_priv->aclk_mac))
clk_disable_unprepare(bsp_priv->aclk_mac);
@@ -940,6 +1001,21 @@ static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
bsp_priv->clock_input = false;
}
+ ret = of_property_read_string(dev->of_node, "phy-type", &strings);
+ if (!ret && !strcmp(strings, "internal")) {
+ bsp_priv->internal_phy = true;
+ bsp_priv->macphy_reset = devm_reset_control_get(dev,
+ "mac-phy");
+ if (IS_ERR(bsp_priv->macphy_reset)) {
+ dev_info(dev, "no macphy_reset control found\n");
+ bsp_priv->macphy_reset = NULL;
+ }
+ } else {
+ bsp_priv->internal_phy = false;
+ }
+ dev_info(dev, "internal PHY? (%s).\n",
+ bsp_priv->internal_phy ? "yes" : "no");
+
ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
if (ret) {
bsp_priv->tx_delay = 0x30;
@@ -1014,6 +1090,9 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
pm_runtime_enable(dev);
pm_runtime_get_sync(dev);
+ if (bsp_priv->internal_phy)
+ rk_gmac_internal_phy_powerup(bsp_priv);
+
return 0;
}
@@ -1021,6 +1100,9 @@ static void rk_gmac_powerdown(struct rk_priv_data *gmac)
{
struct device *dev = &gmac->pdev->dev;
+ if (gmac->internal_phy)
+ rk_gmac_internal_phy_powerdown(gmac);
+
pm_runtime_put_sync(dev);
pm_runtime_disable(dev);
--
1.9.1
There is only one mac controller in rk3228, which could connect to
external phy or internal phy, use the grf_com_mux bit15 to route
external/internal phy.
Change-Id: I3a366677047b8032eb535abb0c3e56fa7722aa2e
Signed-off-by: David Wu <[email protected]>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index c1a1413..90e1fc8 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -86,6 +86,8 @@ struct rk_priv_data {
#define RK3228_GRF_MAC_CON0 0x0900
#define RK3228_GRF_MAC_CON1 0x0904
+#define RK3228_GRF_CON_MUX 0x50
+
/* RK3228_GRF_MAC_CON0 */
#define RK3228_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
#define RK3228_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
@@ -111,6 +113,9 @@ struct rk_priv_data {
#define RK3228_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
#define RK3228_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
+/* RK3228_GRF_COM_MUX */
+#define RK3228_GRF_CON_MUX_GMAC_INTERNAL_PHY GRF_BIT(15)
+
static void rk3228_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
{
@@ -191,11 +196,18 @@ static void rk3228_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
}
+static void rk3228_internal_phy_powerup(struct rk_priv_data *priv)
+{
+ regmap_write(priv->grf, RK3228_GRF_CON_MUX,
+ RK3228_GRF_CON_MUX_GMAC_INTERNAL_PHY);
+}
+
static const struct rk_gmac_ops rk3228_ops = {
.set_to_rgmii = rk3228_set_to_rgmii,
.set_to_rmii = rk3228_set_to_rmii,
.set_rgmii_speed = rk3228_set_rgmii_speed,
.set_rmii_speed = rk3228_set_rmii_speed,
+ .internal_phy_powerup = rk3228_internal_phy_powerup,
};
#define RK3288_GRF_SOC_CON1 0x0248
--
1.9.1
There are two mac controllers in the rk3328, the one connects
to external phy, and the other one connects to internal phy.
Like the mac of external phy, the internal phy's mac also needs to
configure the related mac registers at GRF.
Signed-off-by: David Wu <[email protected]>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 26 +++++++++++++++++++++++---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 90e1fc8..c4c58a2 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -323,6 +323,8 @@ static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
#define RK3328_GRF_MAC_CON0 0x0900
#define RK3328_GRF_MAC_CON1 0x0904
+#define RK3328_GRF_MAC_CON2 0x0908
+#define RK3328_GRF_MACPHY_CON1 0xb04
/* RK3328_GRF_MAC_CON0 */
#define RK3328_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
@@ -349,6 +351,9 @@ static void rk3288_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
#define RK3328_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
#define RK3328_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(0)
+/* RK3328_GRF_MACPHY_CON1 */
+#define RK3328_MACPHY_RMII_MODE GRF_BIT(9)
+
static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
{
@@ -373,13 +378,17 @@ static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv,
static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
{
struct device *dev = &bsp_priv->pdev->dev;
+ unsigned int reg;
if (IS_ERR(bsp_priv->grf)) {
dev_err(dev, "Missing rockchip,grf property\n");
return;
}
- regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
+ reg = bsp_priv->internal_phy ? RK3328_GRF_MAC_CON2 :
+ RK3328_GRF_MAC_CON1;
+
+ regmap_write(bsp_priv->grf, reg,
RK3328_GMAC_PHY_INTF_SEL_RMII |
RK3328_GMAC_RMII_MODE);
}
@@ -409,29 +418,40 @@ static void rk3328_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
static void rk3328_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
{
struct device *dev = &bsp_priv->pdev->dev;
+ unsigned int reg;
if (IS_ERR(bsp_priv->grf)) {
dev_err(dev, "Missing rockchip,grf property\n");
return;
}
+ reg = bsp_priv->internal_phy ? RK3328_GRF_MAC_CON2 :
+ RK3328_GRF_MAC_CON1;
+
if (speed == 10)
- regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
+ regmap_write(bsp_priv->grf, reg,
RK3328_GMAC_RMII_CLK_2_5M |
RK3328_GMAC_SPEED_10M);
else if (speed == 100)
- regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
+ regmap_write(bsp_priv->grf, reg,
RK3328_GMAC_RMII_CLK_25M |
RK3328_GMAC_SPEED_100M);
else
dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
}
+static void rk3328_internal_phy_powerup(struct rk_priv_data *priv)
+{
+ regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
+ RK3328_MACPHY_RMII_MODE);
+}
+
static const struct rk_gmac_ops rk3328_ops = {
.set_to_rgmii = rk3328_set_to_rgmii,
.set_to_rmii = rk3328_set_to_rmii,
.set_rgmii_speed = rk3328_set_rgmii_speed,
.set_rmii_speed = rk3328_set_rmii_speed,
+ .internal_phy_powerup = rk3328_internal_phy_powerup,
};
#define RK3366_GRF_SOC_CON6 0x0418
--
1.9.1
This patch adds internal mac phy clock and internal mac phy reset
for rk gmac using.
Signed-off-by: David Wu <[email protected]>
---
arch/arm/boot/dts/rk322x.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index 48a0c1c..203a583 100644
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -427,13 +427,13 @@
clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
<&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
<&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
- <&cru PCLK_GMAC>;
+ <&cru PCLK_GMAC>, <&cru SCLK_MAC_PHY>;
clock-names = "stmmaceth", "mac_clk_rx",
"mac_clk_tx", "clk_mac_ref",
"clk_mac_refout", "aclk_mac",
- "pclk_mac";
- resets = <&cru SRST_GMAC>;
- reset-names = "stmmaceth";
+ "pclk_mac", "clk_macphy";
+ resets = <&cru SRST_GMAC>, <&cru SRST_MACPHY>;
+ reset-names = "stmmaceth", "mac-phy";
rockchip,grf = <&grf>;
status = "disabled";
};
--
1.9.1
This patch enables the internal phy for rk3228 evb board
by default.
To use the external 1000M phy on evb board, need to make
some switch of evb board to be on.
Signed-off-by: David Wu <[email protected]>
---
arch/arm/boot/dts/rk3228-evb.dts | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/rk3228-evb.dts b/arch/arm/boot/dts/rk3228-evb.dts
index 5883433..c4002da 100644
--- a/arch/arm/boot/dts/rk3228-evb.dts
+++ b/arch/arm/boot/dts/rk3228-evb.dts
@@ -50,6 +50,16 @@
device_type = "memory";
reg = <0x60000000 0x40000000>;
};
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ regulator-name = "vcc_phy";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
};
&emmc {
@@ -60,6 +70,16 @@
status = "okay";
};
+&gmac {
+ assigned-clocks = <&cru SCLK_MAC_SRC>;
+ assigned-clock-rates = <50000000>;
+ clock_in_out = "output";
+ phy-supply = <&vcc_phy>;
+ phy-mode = "rmii";
+ phy-type = "internal";
+ status = "okay";
+};
+
&tsadc {
status = "okay";
--
1.9.1
The gmac2phy controller of rk3328 is connected to internal phy
directly inside, add the node for the internal phy support.
Signed-off-by: David Wu <[email protected]>
---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
index 7e69f1f..29b3800 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -63,6 +63,8 @@
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
+ ethernet0 = &gmac2io;
+ ethernet1 = &gmac2phy;
};
cpus {
@@ -391,6 +393,29 @@
status = "disabled";
};
+ gmac2phy: eth@ff550000 {
+ compatible = "rockchip,rk3328-gmac";
+ reg = <0x0 0xff550000 0x0 0x10000>;
+ rockchip,grf = <&grf>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
+ <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
+ <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
+ <&cru SCLK_MAC2PHY_OUT>;
+ clock-names = "stmmaceth", "mac_clk_rx",
+ "mac_clk_tx", "clk_mac_ref",
+ "aclk_mac", "pclk_mac",
+ "clk_macphy";
+ resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;
+ reset-names = "stmmaceth", "mac-phy";
+ phy-mode = "rmii";
+ phy-type = "internal";
+ pinctrl-names = "default";
+ pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@ff811000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
1.9.1
Let's enable the gmac2phy, make the gmac2phy work on
the rk3328-evb board.
Signed-off-by: David Wu <[email protected]>
---
arch/arm64/boot/dts/rockchip/rk3328-evb.dts | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
index cf27239..b9f36da 100644
--- a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
@@ -50,6 +50,23 @@
chosen {
stdout-path = "serial2:1500000n8";
};
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_phy";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&gmac2phy {
+ phy-supply = <&vcc_phy>;
+ clock_in_out = "output";
+ assigned-clocks = <&cru SCLK_MAC2PHY_SRC>;
+ assigned-clock-rate = <50000000>;
+ assigned-clocks = <&cru SCLK_MAC2PHY>;
+ assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>;
+ status = "okay";
};
&uart2 {
--
1.9.1
On Fri, Jun 23, 2017 at 12:41:59PM +0800, David Wu wrote:
> Support internal ephy currently.
>
> Signed-off-by: David Wu <[email protected]>
> ---
> drivers/net/phy/Kconfig | 4 ++
> drivers/net/phy/Makefile | 1 +
> drivers/net/phy/rockchip.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 99 insertions(+)
> create mode 100644 drivers/net/phy/rockchip.c
>
> diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
> index c360dd6..86010d4 100644
> --- a/drivers/net/phy/Kconfig
> +++ b/drivers/net/phy/Kconfig
> @@ -350,6 +350,10 @@ config XILINX_GMII2RGMII
> the Reduced Gigabit Media Independent Interface(RGMII) between
> Ethernet physical media devices and the Gigabit Ethernet controller.
>
> +config ROCKCHIP_MAC_PHY
> + tristate "Drivers for ROCKCHIP MAC PHY"
> + ---help---
> + Currently supports the mac internal ephy.
> endif # PHYLIB
Alphabetic order please for Kconfig and Makefile.
I will review the rest later today/tomorrow.
Andrew
On 06/22/2017 09:41 PM, David Wu wrote:
> Support internal ephy currently.
>
> Signed-off-by: David Wu <[email protected]>
> ---
> drivers/net/phy/Kconfig | 4 ++
> drivers/net/phy/Makefile | 1 +
> drivers/net/phy/rockchip.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 99 insertions(+)
> create mode 100644 drivers/net/phy/rockchip.c
>
> diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
> index c360dd6..86010d4 100644
> --- a/drivers/net/phy/Kconfig
> +++ b/drivers/net/phy/Kconfig
> @@ -350,6 +350,10 @@ config XILINX_GMII2RGMII
> the Reduced Gigabit Media Independent Interface(RGMII) between
> Ethernet physical media devices and the Gigabit Ethernet controller.
>
> +config ROCKCHIP_MAC_PHY
> + tristate "Drivers for ROCKCHIP MAC PHY"
> + ---help---
> + Currently supports the mac internal ephy.
> endif # PHYLIB
>
> config MICREL_KS8995MA
> diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
> index e36db9a..6d96779 100644
> --- a/drivers/net/phy/Makefile
> +++ b/drivers/net/phy/Makefile
> @@ -69,3 +69,4 @@ obj-$(CONFIG_STE10XP) += ste10Xp.o
> obj-$(CONFIG_TERANETICS_PHY) += teranetics.o
> obj-$(CONFIG_VITESSE_PHY) += vitesse.o
> obj-$(CONFIG_XILINX_GMII2RGMII) += xilinx_gmii2rgmii.o
> +obj-$(CONFIG_ROCKCHIP_MAC_PHY) += rockchip.o
> diff --git a/drivers/net/phy/rockchip.c b/drivers/net/phy/rockchip.c
> new file mode 100644
> index 0000000..69e96ec
> --- /dev/null
> +++ b/drivers/net/phy/rockchip.c
> @@ -0,0 +1,94 @@
> +/**
> + * Rockchip mac phy driver
MAC and PHY, capitalized.
> + *
> + * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
> + *
> + * David Wu<[email protected]>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + */
> +
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/mii.h>
> +#include <linux/ethtool.h>
> +#include <linux/phy.h>
> +#include <linux/netdevice.h>
> +
> +static int internal_config_init(struct phy_device *phydev)
> +{
> + int val;
> + u32 features;
> +
> + /*enable auto mdix*/
> + phy_write(phydev, 0x11, 0x0080);
That is probably the only meaningful change needed by this driver, and
even that is not quite correct because auto MDI-X can be changed from
user-space through ethtool, see
drivers/net/phy/marvell.c::marvell_config_aneg()
> +
> + features = (SUPPORTED_TP | SUPPORTED_MII
> + | SUPPORTED_AUI | SUPPORTED_FIBRE |
> + SUPPORTED_BNC);
This is not necessary, using driver::features set to PHY_GBIT_FEATURES
> +
> + /* Do we support autonegotiation? */
> + val = phy_read(phydev, MII_BMSR);
> + if (val < 0)
> + return val;
> +
> + if (val & BMSR_ANEGCAPABLE)
> + features |= SUPPORTED_Autoneg;
If we have disabled auto-negotiation prior to probing this driver, and
somehow the PHY is not reset, then you are falsely not advertising
support for auto-negotiation just because it *currently is* disabled.
> +
> + if (val & BMSR_100FULL)
> + features |= SUPPORTED_100baseT_Full;
> + if (val & BMSR_100HALF)
> + features |= SUPPORTED_100baseT_Half;
> + if (val & BMSR_10FULL)
> + features |= SUPPORTED_10baseT_Full;
> + if (val & BMSR_10HALF)
> + features |= SUPPORTED_10baseT_Half;
> +
> + if (val & BMSR_ESTATEN) {
> + val = phy_read(phydev, MII_ESTATUS);
> + if (val < 0)
> + return val;
> +
> + if (val & ESTATUS_1000_TFULL)
> + features |= SUPPORTED_1000baseT_Full;
> + if (val & ESTATUS_1000_THALF)
> + features |= SUPPORTED_1000baseT_Half;
> + }
> +
> + phydev->supported = features;
> + phydev->advertising = features;
> +
> + return 0;
> +}
> +
> +static struct phy_driver rockchip_phy_driver[] = {
> +{
> + .phy_id = 0x1234d400,
> + .phy_id_mask = 0xffffffff,
Last 4 digits are supposed to hold the revision, do you really need to
have such a strict mask here?
> + .name = "rockchip internal ephy",
> + .features = 0,
features shoul dbe set to what you support: PHY_GBIT_FEAUTERS
> + .config_init = internal_config_init,
> + .config_aneg = genphy_config_aneg,
> + .read_status = genphy_read_status,
> + .suspend = genphy_suspend,
> + .resume = genphy_resume,
> +},
> +};
> +
> +module_phy_driver(rockchip_phy_driver);
> +
> +static struct mdio_device_id __maybe_unused rockchip_phy_tbl[] = {
> + { 0x1234d400, 0xffffffff },
> + { }
> +};
> +
> +MODULE_DEVICE_TABLE(mdio, rockchip_phy_tbl);
> +
> +MODULE_AUTHOR("David Wu<[email protected]>");
> +MODULE_DESCRIPTION("Rockchip mac phy driver");
> +MODULE_LICENSE("GPL v2");
>
--
Florian
On 06/22/2017 09:59 PM, David Wu wrote:
> To make internal phy worked, need to configure the phy_clock,
> phy cru_reset and related registers.
>
> Change-Id: I6971c0a769754b824b1b908b56080cbaf7867d13
> Signed-off-by: David Wu <[email protected]>
> ---
> .../devicetree/bindings/net/rockchip-dwmac.txt | 3 +
> drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 82 ++++++++++++++++++++++
> 2 files changed, 85 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
> index 8f42755..0514f69 100644
> --- a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
> +++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
> @@ -22,6 +22,7 @@ Required properties:
> <&cru SCLK_MACREF_OUT> clock gate for RMII reference clock output
> <&cru ACLK_GMAC>: AXI clock gate for GMAC
> <&cru PCLK_GMAC>: APB clock gate for GMAC
> + <&cru MAC_PHY>: clock for internal macphy
> - clock-names: One name for each entry in the clocks property.
> - phy-mode: See ethernet.txt file in the same directory.
> - pinctrl-names: Names corresponding to the numbered pinctrl states.
> @@ -35,6 +36,8 @@ Required properties:
> - assigned-clocks: main clock, should be <&cru SCLK_MAC>;
> - assigned-clock-parents = parent of main clock.
> can be <&ext_gmac> or <&cru SCLK_MAC_PLL>.
> + - phy-type: For internal phy, it must be "internal"; For external phy, no need
> + to configure this.
Use the standard "phy-mode" property. You will see
drivers/net/ethernet/broadcom/genet/ actually define a phy-mode =
"internal" property specifically for that. This should probably be
generalized so it is useful to other drivers a well, I will do just that.
>
> Optional properties:
> - tx_delay: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default.
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> index a8e8fd5..c1a1413 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> @@ -41,6 +41,7 @@ struct rk_gmac_ops {
> void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
> void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
> void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
> + void (*internal_phy_powerup)(struct rk_priv_data *bsp_priv);
> };
>
> struct rk_priv_data {
> @@ -52,6 +53,7 @@ struct rk_priv_data {
>
> bool clk_enabled;
> bool clock_input;
> + bool internal_phy;
>
> struct clk *clk_mac;
> struct clk *gmac_clkin;
> @@ -61,6 +63,9 @@ struct rk_priv_data {
> struct clk *clk_mac_refout;
> struct clk *aclk_mac;
> struct clk *pclk_mac;
> + struct clk *clk_macphy;
> +
> + struct reset_control *macphy_reset;
>
> int tx_delay;
> int rx_delay;
> @@ -750,6 +755,48 @@ static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
> .set_rmii_speed = rk3399_set_rmii_speed,
> };
>
> +#define RK_GRF_MACPHY_CON0 0xb00
> +#define RK_GRF_MACPHY_CON1 0xb04
> +#define RK_GRF_MACPHY_CON2 0xb08
> +#define RK_GRF_MACPHY_CON3 0xb0c
> +
> +#define RK_MACPHY_ENABLE GRF_BIT(0)
> +#define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
> +#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
> +#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7))
> +#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0)
> +#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0)
> +
> +static void rk_gmac_internal_phy_powerup(struct rk_priv_data *priv)
> +{
> + if (priv->ops->internal_phy_powerup)
> + priv->ops->internal_phy_powerup(priv);
> +
> + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
> + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
> +
> + regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
> + regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
> +
> + /* disable macphy, the default value is enabled */
> + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
> + if (priv->macphy_reset)
> + reset_control_assert(priv->macphy_reset);
> + usleep_range(10, 20);
> + if (priv->macphy_reset)
> + reset_control_deassert(priv->macphy_reset);
> + usleep_range(10, 20);
> + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
> + msleep(30);
> +}
> +
> +static void rk_gmac_internal_phy_powerdown(struct rk_priv_data *priv)
> +{
> + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
> + if (priv->macphy_reset)
> + reset_control_assert(priv->macphy_reset);
> +}
> +
> static int gmac_clk_init(struct rk_priv_data *bsp_priv)
> {
> struct device *dev = &bsp_priv->pdev->dev;
> @@ -803,6 +850,14 @@ static int gmac_clk_init(struct rk_priv_data *bsp_priv)
> clk_set_rate(bsp_priv->clk_mac, 50000000);
> }
>
> + if (bsp_priv->internal_phy) {
> + bsp_priv->clk_macphy = devm_clk_get(dev, "clk_macphy");
> + if (IS_ERR(bsp_priv->clk_macphy))
> + dev_err(dev, "cannot get %s clock\n", "clk_macphy");
> + else
> + clk_set_rate(bsp_priv->clk_macphy, 50000000);
> + }
> +
> return 0;
> }
>
> @@ -826,6 +881,9 @@ static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
> bsp_priv->clk_mac_refout);
> }
>
> + if (!IS_ERR(bsp_priv->clk_macphy))
> + clk_prepare_enable(bsp_priv->clk_macphy);
> +
> if (!IS_ERR(bsp_priv->aclk_mac))
> clk_prepare_enable(bsp_priv->aclk_mac);
>
> @@ -858,6 +916,9 @@ static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
> bsp_priv->clk_mac_refout);
> }
>
> + if (!IS_ERR(bsp_priv->clk_macphy))
> + clk_disable_unprepare(bsp_priv->clk_macphy);
> +
> if (!IS_ERR(bsp_priv->aclk_mac))
> clk_disable_unprepare(bsp_priv->aclk_mac);
>
> @@ -940,6 +1001,21 @@ static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
> bsp_priv->clock_input = false;
> }
>
> + ret = of_property_read_string(dev->of_node, "phy-type", &strings);
> + if (!ret && !strcmp(strings, "internal")) {
> + bsp_priv->internal_phy = true;
> + bsp_priv->macphy_reset = devm_reset_control_get(dev,
> + "mac-phy");
> + if (IS_ERR(bsp_priv->macphy_reset)) {
> + dev_info(dev, "no macphy_reset control found\n");
> + bsp_priv->macphy_reset = NULL;
> + }
> + } else {
> + bsp_priv->internal_phy = false;
> + }
> + dev_info(dev, "internal PHY? (%s).\n",
> + bsp_priv->internal_phy ? "yes" : "no");
> +
> ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
> if (ret) {
> bsp_priv->tx_delay = 0x30;
> @@ -1014,6 +1090,9 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
> pm_runtime_enable(dev);
> pm_runtime_get_sync(dev);
>
> + if (bsp_priv->internal_phy)
> + rk_gmac_internal_phy_powerup(bsp_priv);
> +
> return 0;
> }
>
> @@ -1021,6 +1100,9 @@ static void rk_gmac_powerdown(struct rk_priv_data *gmac)
> {
> struct device *dev = &gmac->pdev->dev;
>
> + if (gmac->internal_phy)
> + rk_gmac_internal_phy_powerdown(gmac);
> +
> pm_runtime_put_sync(dev);
> pm_runtime_disable(dev);
>
>
--
Florian
Hi David,
Am Freitag, 23. Juni 2017, 12:59:07 CEST schrieb David Wu:
> To make internal phy worked, need to configure the phy_clock,
> phy cru_reset and related registers.
>
> Change-Id: I6971c0a769754b824b1b908b56080cbaf7867d13
please remove all Change-Ids from patches before sending upstream.
There were more affected patches in this series.
> Signed-off-by: David Wu <[email protected]>
> ---
> .../devicetree/bindings/net/rockchip-dwmac.txt | 3 +
> drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 82 ++++++++++++++++++++++
> 2 files changed, 85 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
> index 8f42755..0514f69 100644
> --- a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
> +++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
> @@ -22,6 +22,7 @@ Required properties:
> <&cru SCLK_MACREF_OUT> clock gate for RMII reference clock output
> <&cru ACLK_GMAC>: AXI clock gate for GMAC
> <&cru PCLK_GMAC>: APB clock gate for GMAC
> + <&cru MAC_PHY>: clock for internal macphy
that clock should not be listed as always "Required" like it is here.
Make it some sort of extra paragraph marking it as required when using
an internal phy.
> - clock-names: One name for each entry in the clocks property.
> - phy-mode: See ethernet.txt file in the same directory.
> - pinctrl-names: Names corresponding to the numbered pinctrl states.
> @@ -35,6 +36,8 @@ Required properties:
> - assigned-clocks: main clock, should be <&cru SCLK_MAC>;
> - assigned-clock-parents = parent of main clock.
> can be <&ext_gmac> or <&cru SCLK_MAC_PLL>.
> + - phy-type: For internal phy, it must be "internal"; For external phy, no need
> + to configure this.
>
> Optional properties:
> - tx_delay: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default.
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> index a8e8fd5..c1a1413 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> @@ -41,6 +41,7 @@ struct rk_gmac_ops {
> void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
> void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
> void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
> + void (*internal_phy_powerup)(struct rk_priv_data *bsp_priv);
> };
>
> struct rk_priv_data {
> @@ -52,6 +53,7 @@ struct rk_priv_data {
>
> bool clk_enabled;
> bool clock_input;
> + bool internal_phy;
>
> struct clk *clk_mac;
> struct clk *gmac_clkin;
> @@ -61,6 +63,9 @@ struct rk_priv_data {
> struct clk *clk_mac_refout;
> struct clk *aclk_mac;
> struct clk *pclk_mac;
> + struct clk *clk_macphy;
> +
> + struct reset_control *macphy_reset;
>
> int tx_delay;
> int rx_delay;
> @@ -750,6 +755,48 @@ static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
> .set_rmii_speed = rk3399_set_rmii_speed,
> };
>
> +#define RK_GRF_MACPHY_CON0 0xb00
> +#define RK_GRF_MACPHY_CON1 0xb04
> +#define RK_GRF_MACPHY_CON2 0xb08
> +#define RK_GRF_MACPHY_CON3 0xb0c
> +
> +#define RK_MACPHY_ENABLE GRF_BIT(0)
> +#define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
> +#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
> +#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7))
> +#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0)
> +#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0)
These are primarily registers for the rk3328 and come from the GRF which is
somehow prone to chip-designers moving bits around in registers and also
especially the register offsets (*_CONx) will probably not stay the same
on future socs.
> +static void rk_gmac_internal_phy_powerup(struct rk_priv_data *priv)
> +{
> + if (priv->ops->internal_phy_powerup)
> + priv->ops->internal_phy_powerup(priv);
> +
> + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
> + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
> +
> + regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
> + regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
> +
> + /* disable macphy, the default value is enabled */
that comment is not providing useful information, maybe
/* macphy needs to be disabled before trying to reset it */
> + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
> + if (priv->macphy_reset)
> + reset_control_assert(priv->macphy_reset);
> + usleep_range(10, 20);
> + if (priv->macphy_reset)
> + reset_control_deassert(priv->macphy_reset);
> + usleep_range(10, 20);
> + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
> + msleep(30);
does this do anything useful if priv->macphy_reset is not set, or could
we just change that to
if (priv->macphy_reset) {
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
reset_control_assert(priv->macphy_reset);
usleep_range(10, 20);
reset_control_deassert(priv->macphy_reset);
usleep_range(10, 20);
regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
msleep(30);
}
Heiko
> +
> +static int internal_config_init(struct phy_device *phydev)
> +{
internal_ is a bit generic. The Marvell Ethernet switches have
internal phy, etc. rockchip_ would be a better prefix.
Andrew
On Fri, Jun 23, 2017 at 12:41:59PM +0800, David Wu wrote:
> Support internal ephy currently.
>
> Signed-off-by: David Wu <[email protected]>
> ---
> drivers/net/phy/Kconfig | 4 ++
> drivers/net/phy/Makefile | 1 +
> drivers/net/phy/rockchip.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 99 insertions(+)
> create mode 100644 drivers/net/phy/rockchip.c
>
> diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
> index c360dd6..86010d4 100644
> --- a/drivers/net/phy/Kconfig
> +++ b/drivers/net/phy/Kconfig
> @@ -350,6 +350,10 @@ config XILINX_GMII2RGMII
> the Reduced Gigabit Media Independent Interface(RGMII) between
> Ethernet physical media devices and the Gigabit Ethernet controller.
>
> +config ROCKCHIP_MAC_PHY
This is a bit of an odd name, having both MAC and PHY in it. Are there
any other RockChip PHYs? Any external PHYS? Are they register
incompatible with the internal PHY? Is it even RockChip IP? Or has it
been licensed from somebody else?
I would more likely just call it ROCKCHIP_PHY.
Andrew
On Fri, Jun 23, 2017 at 12:42:02PM +0800, David Wu wrote:
> This is wrong setting for rk3328_set_to_rmii(), so remove it.
>
> Change-Id: I9953784ea44335d90710e5473960c95b3d68a5fd
Hi David
This is not a reconsigned tag for a patch.
Andrew
On Fri, Jun 23, 2017 at 12:59:07PM +0800, David Wu wrote:
> To make internal phy worked, need to configure the phy_clock,
> phy cru_reset and related registers.
>
> Change-Id: I6971c0a769754b824b1b908b56080cbaf7867d13
> Signed-off-by: David Wu <[email protected]>
> ---
> .../devicetree/bindings/net/rockchip-dwmac.txt | 3 +
> drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 82 ++++++++++++++++++++++
> 2 files changed, 85 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
> index 8f42755..0514f69 100644
> --- a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
> +++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
> @@ -22,6 +22,7 @@ Required properties:
> <&cru SCLK_MACREF_OUT> clock gate for RMII reference clock output
> <&cru ACLK_GMAC>: AXI clock gate for GMAC
> <&cru PCLK_GMAC>: APB clock gate for GMAC
> + <&cru MAC_PHY>: clock for internal macphy
If this is the PHY clock, should it actually be specified in the PHY
binding? Can you read the PHY ID registers with this clock off?
Andrew
Am Samstag, 24. Juni 2017, 04:19:10 CEST schrieb Andrew Lunn:
> On Fri, Jun 23, 2017 at 12:41:59PM +0800, David Wu wrote:
> > Support internal ephy currently.
> >
> > Signed-off-by: David Wu <[email protected]>
> > ---
> > drivers/net/phy/Kconfig | 4 ++
> > drivers/net/phy/Makefile | 1 +
> > drivers/net/phy/rockchip.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 99 insertions(+)
> > create mode 100644 drivers/net/phy/rockchip.c
> >
> > diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
> > index c360dd6..86010d4 100644
> > --- a/drivers/net/phy/Kconfig
> > +++ b/drivers/net/phy/Kconfig
> > @@ -350,6 +350,10 @@ config XILINX_GMII2RGMII
> > the Reduced Gigabit Media Independent Interface(RGMII) between
> > Ethernet physical media devices and the Gigabit Ethernet controller.
> >
> > +config ROCKCHIP_MAC_PHY
>
> This is a bit of an odd name, having both MAC and PHY in it. Are there
> any other RockChip PHYs? Any external PHYS? Are they register
> incompatible with the internal PHY? Is it even RockChip IP? Or has it
> been licensed from somebody else?
>
> I would more likely just call it ROCKCHIP_PHY.
hmm, we do have quite a number of non-net phys in the phy subsystem
(DP, PCIe, ...) and given that the above would be CONFIG_ROCKCHIP_PHY
in a global sense, sounds like it could make things confusing.
So some addition sounds reasonable ... ROCKCHIP_ETH_PHY or so?
Heiko
> hmm, we do have quite a number of non-net phys in the phy subsystem
> (DP, PCIe, ...) and given that the above would be CONFIG_ROCKCHIP_PHY
> in a global sense, sounds like it could make things confusing.
>
> So some addition sounds reasonable ... ROCKCHIP_ETH_PHY or so?
I follow you reasoning, but generic phy is the new kid on the
block. It is well established that Ethernet PHYs are called
<MANUFACTURER>_PHY.
If you do want to consider generic phy, the logical name would be
ROCKCHIP_PHY_PHY, since generic phy postfixes with _SATA, _USB, _PCIE,
etc. But that does leave an issues when we have an Ethernet PHY which
needs a generic PHY. In some sense, SERDES could be considered as
something supported by a generic PHY...
Andrew
Am Samstag, 24. Juni 2017, 16:04:06 CEST schrieb Andrew Lunn:
> > hmm, we do have quite a number of non-net phys in the phy subsystem
> > (DP, PCIe, ...) and given that the above would be CONFIG_ROCKCHIP_PHY
> > in a global sense, sounds like it could make things confusing.
> >
> > So some addition sounds reasonable ... ROCKCHIP_ETH_PHY or so?
>
> I follow you reasoning, but generic phy is the new kid on the
> block. It is well established that Ethernet PHYs are called
> <MANUFACTURER>_PHY.
Ok, then without further bikeshedding, let's just go with your
naming then (ROCKCHIP_PHY) :-) .
Heiko
> If you do want to consider generic phy, the logical name would be
> ROCKCHIP_PHY_PHY, since generic phy postfixes with _SATA, _USB, _PCIE,
> etc. But that does leave an issues when we have an Ethernet PHY which
> needs a generic PHY. In some sense, SERDES could be considered as
> something supported by a generic PHY...
>
> Andrew
>
>
Hi Florian,
Sorry for reply late.
在 2017/6/24 0:22, Florian Fainelli 写道:
> On 06/22/2017 09:59 PM, David Wu wrote:
>> To make internal phy worked, need to configure the phy_clock,
>> phy cru_reset and related registers.
>>
>> Change-Id: I6971c0a769754b824b1b908b56080cbaf7867d13
>> Signed-off-by: David Wu <[email protected]>
>> ---
>> .../devicetree/bindings/net/rockchip-dwmac.txt | 3 +
>> drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 82 ++++++++++++++++++++++
>> 2 files changed, 85 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
>> index 8f42755..0514f69 100644
>> --- a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
>> +++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
>> @@ -22,6 +22,7 @@ Required properties:
>> <&cru SCLK_MACREF_OUT> clock gate for RMII reference clock output
>> <&cru ACLK_GMAC>: AXI clock gate for GMAC
>> <&cru PCLK_GMAC>: APB clock gate for GMAC
>> + <&cru MAC_PHY>: clock for internal macphy
>> - clock-names: One name for each entry in the clocks property.
>> - phy-mode: See ethernet.txt file in the same directory.
>> - pinctrl-names: Names corresponding to the numbered pinctrl states.
>> @@ -35,6 +36,8 @@ Required properties:
>> - assigned-clocks: main clock, should be <&cru SCLK_MAC>;
>> - assigned-clock-parents = parent of main clock.
>> can be <&ext_gmac> or <&cru SCLK_MAC_PLL>.
>> + - phy-type: For internal phy, it must be "internal"; For external phy, no need
>> + to configure this.
>
> Use the standard "phy-mode" property. You will see
> drivers/net/ethernet/broadcom/genet/ actually define a phy-mode =
> "internal" property specifically for that. This should probably be
> generalized so it is useful to other drivers a well, I will do just that.
>
I'm a little confused for the property of phy-mode = "internal".
If the property of phy-mode is configured as "internal" from DT , i
could not get the rmii or rgmii mode for the phy.
I use it to differentiate rmii or rgmii for different configuration.
>>
>> Optional properties:
>> - tx_delay: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default.
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
>> index a8e8fd5..c1a1413 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
>> @@ -41,6 +41,7 @@ struct rk_gmac_ops {
>> void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
>> void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
>> void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
>> + void (*internal_phy_powerup)(struct rk_priv_data *bsp_priv);
>> };
>>
>> struct rk_priv_data {
>> @@ -52,6 +53,7 @@ struct rk_priv_data {
>>
>> bool clk_enabled;
>> bool clock_input;
>> + bool internal_phy;
>>
>> struct clk *clk_mac;
>> struct clk *gmac_clkin;
>> @@ -61,6 +63,9 @@ struct rk_priv_data {
>> struct clk *clk_mac_refout;
>> struct clk *aclk_mac;
>> struct clk *pclk_mac;
>> + struct clk *clk_macphy;
>> +
>> + struct reset_control *macphy_reset;
>>
>> int tx_delay;
>> int rx_delay;
>> @@ -750,6 +755,48 @@ static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
>> .set_rmii_speed = rk3399_set_rmii_speed,
>> };
>>
>> +#define RK_GRF_MACPHY_CON0 0xb00
>> +#define RK_GRF_MACPHY_CON1 0xb04
>> +#define RK_GRF_MACPHY_CON2 0xb08
>> +#define RK_GRF_MACPHY_CON3 0xb0c
>> +
>> +#define RK_MACPHY_ENABLE GRF_BIT(0)
>> +#define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
>> +#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
>> +#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7))
>> +#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0)
>> +#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0)
>> +
>> +static void rk_gmac_internal_phy_powerup(struct rk_priv_data *priv)
>> +{
>> + if (priv->ops->internal_phy_powerup)
>> + priv->ops->internal_phy_powerup(priv);
>> +
>> + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
>> + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
>> +
>> + regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
>> + regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
>> +
>> + /* disable macphy, the default value is enabled */
>> + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
>> + if (priv->macphy_reset)
>> + reset_control_assert(priv->macphy_reset);
>> + usleep_range(10, 20);
>> + if (priv->macphy_reset)
>> + reset_control_deassert(priv->macphy_reset);
>> + usleep_range(10, 20);
>> + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
>> + msleep(30);
>> +}
>> +
>> +static void rk_gmac_internal_phy_powerdown(struct rk_priv_data *priv)
>> +{
>> + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
>> + if (priv->macphy_reset)
>> + reset_control_assert(priv->macphy_reset);
>> +}
>> +
>> static int gmac_clk_init(struct rk_priv_data *bsp_priv)
>> {
>> struct device *dev = &bsp_priv->pdev->dev;
>> @@ -803,6 +850,14 @@ static int gmac_clk_init(struct rk_priv_data *bsp_priv)
>> clk_set_rate(bsp_priv->clk_mac, 50000000);
>> }
>>
>> + if (bsp_priv->internal_phy) {
>> + bsp_priv->clk_macphy = devm_clk_get(dev, "clk_macphy");
>> + if (IS_ERR(bsp_priv->clk_macphy))
>> + dev_err(dev, "cannot get %s clock\n", "clk_macphy");
>> + else
>> + clk_set_rate(bsp_priv->clk_macphy, 50000000);
>> + }
>> +
>> return 0;
>> }
>>
>> @@ -826,6 +881,9 @@ static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
>> bsp_priv->clk_mac_refout);
>> }
>>
>> + if (!IS_ERR(bsp_priv->clk_macphy))
>> + clk_prepare_enable(bsp_priv->clk_macphy);
>> +
>> if (!IS_ERR(bsp_priv->aclk_mac))
>> clk_prepare_enable(bsp_priv->aclk_mac);
>>
>> @@ -858,6 +916,9 @@ static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
>> bsp_priv->clk_mac_refout);
>> }
>>
>> + if (!IS_ERR(bsp_priv->clk_macphy))
>> + clk_disable_unprepare(bsp_priv->clk_macphy);
>> +
>> if (!IS_ERR(bsp_priv->aclk_mac))
>> clk_disable_unprepare(bsp_priv->aclk_mac);
>>
>> @@ -940,6 +1001,21 @@ static struct rk_priv_data *rk_gmac_setup(struct platform_device *pdev,
>> bsp_priv->clock_input = false;
>> }
>>
>> + ret = of_property_read_string(dev->of_node, "phy-type", &strings);
>> + if (!ret && !strcmp(strings, "internal")) {
>> + bsp_priv->internal_phy = true;
>> + bsp_priv->macphy_reset = devm_reset_control_get(dev,
>> + "mac-phy");
>> + if (IS_ERR(bsp_priv->macphy_reset)) {
>> + dev_info(dev, "no macphy_reset control found\n");
>> + bsp_priv->macphy_reset = NULL;
>> + }
>> + } else {
>> + bsp_priv->internal_phy = false;
>> + }
>> + dev_info(dev, "internal PHY? (%s).\n",
>> + bsp_priv->internal_phy ? "yes" : "no");
>> +
>> ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
>> if (ret) {
>> bsp_priv->tx_delay = 0x30;
>> @@ -1014,6 +1090,9 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp_priv)
>> pm_runtime_enable(dev);
>> pm_runtime_get_sync(dev);
>>
>> + if (bsp_priv->internal_phy)
>> + rk_gmac_internal_phy_powerup(bsp_priv);
>> +
>> return 0;
>> }
>>
>> @@ -1021,6 +1100,9 @@ static void rk_gmac_powerdown(struct rk_priv_data *gmac)
>> {
>> struct device *dev = &gmac->pdev->dev;
>>
>> + if (gmac->internal_phy)
>> + rk_gmac_internal_phy_powerdown(gmac);
>> +
>> pm_runtime_put_sync(dev);
>> pm_runtime_disable(dev);
>>
>>
>
>
Hi Heiko,
?? 2017/6/24 1:19, Heiko Stuebner д??:
> Hi David,
>
> Am Freitag, 23. Juni 2017, 12:59:07 CEST schrieb David Wu:
>> To make internal phy worked, need to configure the phy_clock,
>> phy cru_reset and related registers.
>>
>> Change-Id: I6971c0a769754b824b1b908b56080cbaf7867d13
>
> please remove all Change-Ids from patches before sending upstream.
> There were more affected patches in this series.
>
>> Signed-off-by: David Wu <[email protected]>
>> ---
>> .../devicetree/bindings/net/rockchip-dwmac.txt | 3 +
>> drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 82 ++++++++++++++++++++++
>> 2 files changed, 85 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
>> index 8f42755..0514f69 100644
>> --- a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
>> +++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
>> @@ -22,6 +22,7 @@ Required properties:
>> <&cru SCLK_MACREF_OUT> clock gate for RMII reference clock output
>> <&cru ACLK_GMAC>: AXI clock gate for GMAC
>> <&cru PCLK_GMAC>: APB clock gate for GMAC
>> + <&cru MAC_PHY>: clock for internal macphy
>
> that clock should not be listed as always "Required" like it is here.
> Make it some sort of extra paragraph marking it as required when using
> an internal phy.
>
Okay, move it to the option.
>> - clock-names: One name for each entry in the clocks property.
>> - phy-mode: See ethernet.txt file in the same directory.
>> - pinctrl-names: Names corresponding to the numbered pinctrl states.
>> @@ -35,6 +36,8 @@ Required properties:
>> - assigned-clocks: main clock, should be <&cru SCLK_MAC>;
>> - assigned-clock-parents = parent of main clock.
>> can be <&ext_gmac> or <&cru SCLK_MAC_PLL>.
>> + - phy-type: For internal phy, it must be "internal"; For external phy, no need
>> + to configure this.
>>
>> Optional properties:
>> - tx_delay: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default.
>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
>> index a8e8fd5..c1a1413 100644
>> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
>> @@ -41,6 +41,7 @@ struct rk_gmac_ops {
>> void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
>> void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
>> void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
>> + void (*internal_phy_powerup)(struct rk_priv_data *bsp_priv);
>> };
>>
>> struct rk_priv_data {
>> @@ -52,6 +53,7 @@ struct rk_priv_data {
>>
>> bool clk_enabled;
>> bool clock_input;
>> + bool internal_phy;
>>
>> struct clk *clk_mac;
>> struct clk *gmac_clkin;
>> @@ -61,6 +63,9 @@ struct rk_priv_data {
>> struct clk *clk_mac_refout;
>> struct clk *aclk_mac;
>> struct clk *pclk_mac;
>> + struct clk *clk_macphy;
>> +
>> + struct reset_control *macphy_reset;
>>
>> int tx_delay;
>> int rx_delay;
>> @@ -750,6 +755,48 @@ static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
>> .set_rmii_speed = rk3399_set_rmii_speed,
>> };
>>
>> +#define RK_GRF_MACPHY_CON0 0xb00
>> +#define RK_GRF_MACPHY_CON1 0xb04
>> +#define RK_GRF_MACPHY_CON2 0xb08
>> +#define RK_GRF_MACPHY_CON3 0xb0c
>> +
>> +#define RK_MACPHY_ENABLE GRF_BIT(0)
>> +#define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
>> +#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
>> +#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7))
>> +#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0)
>> +#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0)
>
> These are primarily registers for the rk3328 and come from the GRF which is
> somehow prone to chip-designers moving bits around in registers and also
> especially the register offsets (*_CONx) will probably not stay the same
> on future socs.
>
I think they should try to keep the same. But what you said is very
reasonable. So let's give rk3228 and rk3328 different
internal_phy_powerup() in the rk_gmac_ops to set their own configuration?
>
>> +static void rk_gmac_internal_phy_powerup(struct rk_priv_data *priv)
>> +{
>> + if (priv->ops->internal_phy_powerup)
>> + priv->ops->internal_phy_powerup(priv);
>> +
>> + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
>> + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
>> +
>> + regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
>> + regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
>> +
>> + /* disable macphy, the default value is enabled */
>
> that comment is not providing useful information, maybe
> /* macphy needs to be disabled before trying to reset it */
>
>
>> + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
>> + if (priv->macphy_reset)
>> + reset_control_assert(priv->macphy_reset);
>> + usleep_range(10, 20);
>> + if (priv->macphy_reset)
>> + reset_control_deassert(priv->macphy_reset);
>> + usleep_range(10, 20);
>> + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
>> + msleep(30);
>
> does this do anything useful if priv->macphy_reset is not set, or could
> we just change that to
>
Okay.
> if (priv->macphy_reset) {
> regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
> reset_control_assert(priv->macphy_reset);
> usleep_range(10, 20);
> reset_control_deassert(priv->macphy_reset);
> usleep_range(10, 20);
> regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
> msleep(30);
> }
>
>
> Heiko
>
>
>
Hi Andrew,
?? 2017/6/24 10:19, Andrew Lunn д??:
> On Fri, Jun 23, 2017 at 12:41:59PM +0800, David Wu wrote:
>> Support internal ephy currently.
>>
>> Signed-off-by: David Wu <[email protected]>
>> ---
>> drivers/net/phy/Kconfig | 4 ++
>> drivers/net/phy/Makefile | 1 +
>> drivers/net/phy/rockchip.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 99 insertions(+)
>> create mode 100644 drivers/net/phy/rockchip.c
>>
>> diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
>> index c360dd6..86010d4 100644
>> --- a/drivers/net/phy/Kconfig
>> +++ b/drivers/net/phy/Kconfig
>> @@ -350,6 +350,10 @@ config XILINX_GMII2RGMII
>> the Reduced Gigabit Media Independent Interface(RGMII) between
>> Ethernet physical media devices and the Gigabit Ethernet controller.
>>
>> +config ROCKCHIP_MAC_PHY
>
> This is a bit of an odd name, having both MAC and PHY in it. Are there
> any other RockChip PHYs? Any external PHYS? Are they register
> incompatible with the internal PHY? Is it even RockChip IP? Or has it
> been licensed from somebody else?
>
Maybe I just want to highlight it applies to the PHY with Mac
connection, actually I was named Rockchip at the beginning, as Heiko
said, PHY is a wide range, so add a modifier to restrict it.
Yes, we use other external phys, like realtek and etc...
If we have any other phy in our socs, it also could be expanded at
rockchip_phy_tbl{} at rockchip.c
it has been licensed from somebody.
> I would more likely just call it ROCKCHIP_PHY.
>
> Andrew
>
>
>
> it has been licensed from somebody.
And does that somebody already have a driver for it? There is no point
adding a driver, if all you need to do is add the ID to another
driver.
Andrew
> I'm a little confused for the property of phy-mode = "internal".
> If the property of phy-mode is configured as "internal" from DT , i
> could not get the rmii or rgmii mode for the phy.
> I use it to differentiate rmii or rgmii for different configuration.
phy-mode is about the bus between the MAC and the PHY. Internal means
there is not a standard bus between the MAC and the PHY, something
proprietary is being used to embed the PHY in the MAC.
If you are using RMII or RGMII, then it is not internal, in that as
standard bus is being used. It does not matter if that bus is not
available external to the SoC, it still exists.
Andrew
Hi Andrew,
?? 2017/6/27 22:46, Andrew Lunn д??:
>> it has been licensed from somebody.
>
> And does that somebody already have a driver for it? There is no point
> adding a driver, if all you need to do is add the ID to another
> driver.
>
I didn't find it.
Maybe use the same, but the configuration is different.
But this may also be possible, upstream with a new driver.
> Andrew
>
>
>
Hi David,
Am Dienstag, 27. Juni 2017, 22:33:20 CEST schrieb David.Wu:
> 在 2017/6/24 1:19, Heiko Stuebner 写道:
> > Am Freitag, 23. Juni 2017, 12:59:07 CEST schrieb David Wu:
> >> To make internal phy worked, need to configure the phy_clock,
> >> phy cru_reset and related registers.
> >>
> >> Change-Id: I6971c0a769754b824b1b908b56080cbaf7867d13
> >
> > please remove all Change-Ids from patches before sending upstream.
> > There were more affected patches in this series.
> >
> >> Signed-off-by: David Wu <[email protected]>
> >> ---
> >> .../devicetree/bindings/net/rockchip-dwmac.txt | 3 +
> >> drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 82 ++++++++++++++++++++++
> >> 2 files changed, 85 insertions(+)
> >>
> >> diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
> >> index 8f42755..0514f69 100644
> >> --- a/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
> >> +++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.txt
> >> @@ -22,6 +22,7 @@ Required properties:
> >> <&cru SCLK_MACREF_OUT> clock gate for RMII reference clock output
> >> <&cru ACLK_GMAC>: AXI clock gate for GMAC
> >> <&cru PCLK_GMAC>: APB clock gate for GMAC
> >> + <&cru MAC_PHY>: clock for internal macphy
> >
> > that clock should not be listed as always "Required" like it is here.
> > Make it some sort of extra paragraph marking it as required when using
> > an internal phy.
> >
>
> Okay, move it to the option.
>
> >> - clock-names: One name for each entry in the clocks property.
> >> - phy-mode: See ethernet.txt file in the same directory.
> >> - pinctrl-names: Names corresponding to the numbered pinctrl states.
> >> @@ -35,6 +36,8 @@ Required properties:
> >> - assigned-clocks: main clock, should be <&cru SCLK_MAC>;
> >> - assigned-clock-parents = parent of main clock.
> >> can be <&ext_gmac> or <&cru SCLK_MAC_PLL>.
> >> + - phy-type: For internal phy, it must be "internal"; For external phy, no need
> >> + to configure this.
> >>
> >> Optional properties:
> >> - tx_delay: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default.
> >> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> >> index a8e8fd5..c1a1413 100644
> >> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> >> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
> >> @@ -41,6 +41,7 @@ struct rk_gmac_ops {
> >> void (*set_to_rmii)(struct rk_priv_data *bsp_priv);
> >> void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
> >> void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
> >> + void (*internal_phy_powerup)(struct rk_priv_data *bsp_priv);
> >> };
> >>
> >> struct rk_priv_data {
> >> @@ -52,6 +53,7 @@ struct rk_priv_data {
> >>
> >> bool clk_enabled;
> >> bool clock_input;
> >> + bool internal_phy;
> >>
> >> struct clk *clk_mac;
> >> struct clk *gmac_clkin;
> >> @@ -61,6 +63,9 @@ struct rk_priv_data {
> >> struct clk *clk_mac_refout;
> >> struct clk *aclk_mac;
> >> struct clk *pclk_mac;
> >> + struct clk *clk_macphy;
> >> +
> >> + struct reset_control *macphy_reset;
> >>
> >> int tx_delay;
> >> int rx_delay;
> >> @@ -750,6 +755,48 @@ static void rk3399_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
> >> .set_rmii_speed = rk3399_set_rmii_speed,
> >> };
> >>
> >> +#define RK_GRF_MACPHY_CON0 0xb00
> >> +#define RK_GRF_MACPHY_CON1 0xb04
> >> +#define RK_GRF_MACPHY_CON2 0xb08
> >> +#define RK_GRF_MACPHY_CON3 0xb0c
> >> +
> >> +#define RK_MACPHY_ENABLE GRF_BIT(0)
> >> +#define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
> >> +#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
> >> +#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7))
> >> +#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0)
> >> +#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0)
> >
> > These are primarily registers for the rk3328 and come from the GRF which is
> > somehow prone to chip-designers moving bits around in registers and also
> > especially the register offsets (*_CONx) will probably not stay the same
> > on future socs.
> >
>
> I think they should try to keep the same. But what you said is very
> reasonable. So let's give rk3228 and rk3328 different
> internal_phy_powerup() in the rk_gmac_ops to set their own configuration?
I just looked at both the rk3228 and rk3328 GRFs and really this seems
to be the first time I see GRF-parts that are similar :-) .
There is no need to duplicate code unnecessarily, if the registers really
are the same for both. So I guess, just prefix everything with a rk3228_*
and add a comment that the rk3328 uses the same GRF layout.
That way future socs, can then add their (likely) changed register setups
as needed.
Heiko
Hi Andrew,
?? 2017/6/24 10:29, Andrew Lunn д??:
> If this is the PHY clock, should it actually be specified in the PHY
> binding? Can you read the PHY ID registers with this clock off?
If the phy clock is closed, we can not read the PHYID.