From: John Crispin <[email protected]>
Add a driver to setup the USB phy on Mediatek/Ralink SoCs.
The driver is trivial and only sets up power and host mode.
Signed-off-by: John Crispin <[email protected]>
Signed-off-by: Harvey Hunt <[email protected]>
Cc: [email protected]
Cc: [email protected]
---
Changes in V4
* Remove Allwinner from comment
* Depend on COMPILE_TEST
Changes in V3
* Separate DT bindings
* Update Kconfig text
* Modify John's email address
* Rebase onto v4.13-rc3
Changes in V2
* remove refcounting
* drop empty functions
* dont use static globals
* use explicit compatible strings
drivers/phy/Kconfig | 8 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-ralink-usb.c | 173 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 182 insertions(+)
create mode 100644 drivers/phy/phy-ralink-usb.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index c1807d4..8fb5260 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -41,6 +41,14 @@ config PHY_PISTACHIO_USB
help
Enable this to support the USB2.0 PHY on the IMG Pistachio SoC.
+config PHY_RALINK_USB
+ tristate "Ralink USB PHY driver"
+ select GENERIC_PHY
+ depends on RALINK || COMPILE_TEST
+ help
+ This option enables support for the Ralink USB PHY found inside
+ RT3352, MT7620, MT7628 and MT7688.
+
config PHY_XGENE
tristate "APM X-Gene 15Gbps PHY support"
depends on HAS_IOMEM && OF && (ARM64 || COMPILE_TEST)
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index f252201..60ed30b 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o
obj-$(CONFIG_PHY_MT65XX_USB3) += phy-mt65xx-usb3.o
obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
+obj-$(CONFIG_PHY_RALINK_USB) += phy-ralink-usb.o
obj-$(CONFIG_ARCH_SUNXI) += allwinner/
obj-$(CONFIG_ARCH_MESON) += amlogic/
diff --git a/drivers/phy/phy-ralink-usb.c b/drivers/phy/phy-ralink-usb.c
new file mode 100644
index 0000000..14a254a
--- /dev/null
+++ b/drivers/phy/phy-ralink-usb.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright (C) 2016 John Crispin <[email protected]>
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd. <http://www.allwinnertech.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/of_platform.h>
+
+#include <asm/mach-ralink/ralink_regs.h>
+
+#define RT_SYSC_REG_SYSCFG1 0x014
+#define RT_SYSC_REG_CLKCFG1 0x030
+#define RT_SYSC_REG_USB_PHY_CFG 0x05c
+
+#define RT_RSTCTRL_UDEV BIT(25)
+#define RT_RSTCTRL_UHST BIT(22)
+#define RT_SYSCFG1_USB0_HOST_MODE BIT(10)
+
+#define MT7620_CLKCFG1_UPHY0_CLK_EN BIT(25)
+#define MT7620_CLKCFG1_UPHY1_CLK_EN BIT(22)
+#define RT_CLKCFG1_UPHY1_CLK_EN BIT(20)
+#define RT_CLKCFG1_UPHY0_CLK_EN BIT(18)
+
+#define USB_PHY_UTMI_8B60M BIT(1)
+#define UDEV_WAKEUP BIT(0)
+
+struct ralink_usb_phy {
+ struct reset_control *rstdev;
+ struct reset_control *rsthost;
+ u32 clk;
+ struct phy *phy;
+};
+
+static int ralink_usb_phy_power_on(struct phy *_phy)
+{
+ struct ralink_usb_phy *phy = phy_get_drvdata(_phy);
+ u32 t;
+
+ /* enable the phy */
+ rt_sysc_m32(0, phy->clk, RT_SYSC_REG_CLKCFG1);
+
+ /* setup host mode */
+ rt_sysc_m32(0, RT_SYSCFG1_USB0_HOST_MODE, RT_SYSC_REG_SYSCFG1);
+
+ /* deassert the reset lines */
+ reset_control_deassert(phy->rsthost);
+ reset_control_deassert(phy->rstdev);
+
+ /*
+ * The SDK kernel had a delay of 100ms. however on device
+ * testing showed that 10ms is enough
+ */
+ mdelay(10);
+
+ /* print some status info */
+ t = rt_sysc_r32(RT_SYSC_REG_USB_PHY_CFG);
+ dev_info(&phy->phy->dev, "remote usb device wakeup %s\n",
+ (t & UDEV_WAKEUP) ? ("enabled") : ("disabled"));
+ if (t & USB_PHY_UTMI_8B60M)
+ dev_info(&phy->phy->dev, "UTMI 8bit 60MHz\n");
+ else
+ dev_info(&phy->phy->dev, "UTMI 16bit 30MHz\n");
+
+ return 0;
+}
+
+static int ralink_usb_phy_power_off(struct phy *_phy)
+{
+ struct ralink_usb_phy *phy = phy_get_drvdata(_phy);
+
+ /* disable the phy */
+ rt_sysc_m32(phy->clk, 0, RT_SYSC_REG_CLKCFG1);
+
+ /* assert the reset lines */
+ reset_control_assert(phy->rstdev);
+ reset_control_assert(phy->rsthost);
+
+ return 0;
+}
+
+static struct phy_ops ralink_usb_phy_ops = {
+ .power_on = ralink_usb_phy_power_on,
+ .power_off = ralink_usb_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static const struct of_device_id ralink_usb_phy_of_match[] = {
+ {
+ .compatible = "ralink,rt3352-usbphy",
+ .data = (void *) (RT_CLKCFG1_UPHY1_CLK_EN |
+ RT_CLKCFG1_UPHY0_CLK_EN)
+ },
+ {
+ .compatible = "mediatek,mt7620-usbphy",
+ .data = (void *) (MT7620_CLKCFG1_UPHY1_CLK_EN |
+ MT7620_CLKCFG1_UPHY0_CLK_EN) },
+ { },
+};
+MODULE_DEVICE_TABLE(of, ralink_usb_phy_of_match);
+
+static int ralink_usb_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct phy_provider *phy_provider;
+ const struct of_device_id *match;
+ struct ralink_usb_phy *phy;
+
+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
+ if (!phy)
+ return -ENOMEM;
+
+ match = of_match_device(ralink_usb_phy_of_match, &pdev->dev);
+ if (!match)
+ return -ENODEV;
+
+ phy->clk = (int) match->data;
+
+ phy->rsthost = devm_reset_control_get(&pdev->dev, "host");
+ if (IS_ERR(phy->rsthost)) {
+ dev_err(dev, "host reset is missing\n");
+ return PTR_ERR(phy->rsthost);
+ }
+
+ phy->rstdev = devm_reset_control_get(&pdev->dev, "device");
+ if (IS_ERR(phy->rstdev)) {
+ dev_err(dev, "device reset is missing\n");
+ return PTR_ERR(phy->rstdev);
+ }
+
+ phy->phy = devm_phy_create(dev, NULL, &ralink_usb_phy_ops);
+ if (IS_ERR(phy->phy)) {
+ dev_err(dev, "failed to create PHY\n");
+ return PTR_ERR(phy->phy);
+ }
+ phy_set_drvdata(phy->phy, phy);
+
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static struct platform_driver ralink_usb_phy_driver = {
+ .probe = ralink_usb_phy_probe,
+ .driver = {
+ .of_match_table = ralink_usb_phy_of_match,
+ .name = "ralink-usb-phy",
+ }
+};
+module_platform_driver(ralink_usb_phy_driver);
+
+MODULE_DESCRIPTION("Ralink USB phy driver");
+MODULE_AUTHOR("John Crispin <[email protected]>");
+MODULE_LICENSE("GPL v2");
--
2.7.4
From: John Crispin <[email protected]>
Add a binding for the USB phy on Mediatek/Ralink SoCs.
Signed-off-by: John Crispin <[email protected]>
Signed-off-by: Harvey Hunt <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
Changes in V4:
* None
Changes in V3:
* Split out from first patch
.../devicetree/bindings/phy/ralink-usb-phy.txt | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/ralink-usb-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/ralink-usb-phy.txt b/Documentation/devicetree/bindings/phy/ralink-usb-phy.txt
new file mode 100644
index 0000000..5b27cad
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/ralink-usb-phy.txt
@@ -0,0 +1,17 @@
+Mediatek/Ralink USB PHY
+
+Required properties:
+ - compatible: ralink,rt3352-usbphy or mediatek,mt7620-usbphy
+ - #phy-cells: should be 0
+ - resets: the two reset controllers for host and device
+ - reset-names: the names of the 2 reset controllers
+
+Example:
+
+usbphy: phy {
+ compatible = "mediatek,mt7620-usbphy";
+ #phy-cells = <0>;
+
+ resets = <&rstctrl 22 &rstctrl 25>;
+ reset-names = "host", "device";
+};
--
2.7.4
On 9 August 2017 10:35:39 BST, Harvey Hunt <[email protected]> wrote:
>From: John Crispin <[email protected]>
>
>Add a driver to setup the USB phy on Mediatek/Ralink SoCs.
>The driver is trivial and only sets up power and host mode.
>
>Signed-off-by: John Crispin <[email protected]>
>Signed-off-by: Harvey Hunt <[email protected]>
>Cc: [email protected]
>Cc: [email protected]
>---
>Changes in V4
>* Remove Allwinner from comment
>* Depend on COMPILE_TEST
>
>Changes in V3
>* Separate DT bindings
>* Update Kconfig text
>* Modify John's email address
>* Rebase onto v4.13-rc3
>
>Changes in V2
>* remove refcounting
>* drop empty functions
>* dont use static globals
>* use explicit compatible strings
>
> drivers/phy/Kconfig | 8 ++
> drivers/phy/Makefile | 1 +
>drivers/phy/phy-ralink-usb.c | 173
>+++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 182 insertions(+)
> create mode 100644 drivers/phy/phy-ralink-usb.c
>
>diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>index c1807d4..8fb5260 100644
>--- a/drivers/phy/Kconfig
>+++ b/drivers/phy/Kconfig
>@@ -41,6 +41,14 @@ config PHY_PISTACHIO_USB
> help
> Enable this to support the USB2.0 PHY on the IMG Pistachio SoC.
>
>+config PHY_RALINK_USB
>+ tristate "Ralink USB PHY driver"
>+ select GENERIC_PHY
>+ depends on RALINK || COMPILE_TEST
given that the driver includes a asm/mach-ralink header, the COMPILE_TEST bit may break x86 allmodconfig?
maybe the header should be moved out of arch/mips or it should depend on MIPS only (so a mips allmodconfig catches it, but cant be enabled on x86 even with COMPILE_TEST=y)
cheers
James
>+ help
>+ This option enables support for the Ralink USB PHY found inside
>+ RT3352, MT7620, MT7628 and MT7688.
>+
> config PHY_XGENE
> tristate "APM X-Gene 15Gbps PHY support"
> depends on HAS_IOMEM && OF && (ARM64 || COMPILE_TEST)
>diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>index f252201..60ed30b 100644
>--- a/drivers/phy/Makefile
>+++ b/drivers/phy/Makefile
>@@ -7,6 +7,7 @@ obj-$(CONFIG_PHY_LPC18XX_USB_OTG) +=
>phy-lpc18xx-usb-otg.o
> obj-$(CONFIG_PHY_MT65XX_USB3) += phy-mt65xx-usb3.o
> obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
> obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
>+obj-$(CONFIG_PHY_RALINK_USB) += phy-ralink-usb.o
>
> obj-$(CONFIG_ARCH_SUNXI) += allwinner/
> obj-$(CONFIG_ARCH_MESON) += amlogic/
>diff --git a/drivers/phy/phy-ralink-usb.c
>b/drivers/phy/phy-ralink-usb.c
>new file mode 100644
>index 0000000..14a254a
>--- /dev/null
>+++ b/drivers/phy/phy-ralink-usb.c
>@@ -0,0 +1,173 @@
>+/*
>+ * Copyright (C) 2016 John Crispin <[email protected]>
>+ *
>+ * Based on code from
>+ * Allwinner Technology Co., Ltd. <http://www.allwinnertech.com>
>+ *
>+ * This program is free software; you can redistribute it and/or
>modify
>+ * it under the terms of the GNU General Public License as published
>by
>+ * the Free Software Foundation; either version 2 of the License, or
>+ * (at your option) any later version.
>+ *
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>+ * GNU General Public License for more details.
>+ */
>+
>+#include <linux/delay.h>
>+#include <linux/err.h>
>+#include <linux/io.h>
>+#include <linux/kernel.h>
>+#include <linux/module.h>
>+#include <linux/mutex.h>
>+#include <linux/phy/phy.h>
>+#include <linux/platform_device.h>
>+#include <linux/reset.h>
>+#include <linux/of_platform.h>
>+
>+#include <asm/mach-ralink/ralink_regs.h>
>+
>+#define RT_SYSC_REG_SYSCFG1 0x014
>+#define RT_SYSC_REG_CLKCFG1 0x030
>+#define RT_SYSC_REG_USB_PHY_CFG 0x05c
>+
>+#define RT_RSTCTRL_UDEV BIT(25)
>+#define RT_RSTCTRL_UHST BIT(22)
>+#define RT_SYSCFG1_USB0_HOST_MODE BIT(10)
>+
>+#define MT7620_CLKCFG1_UPHY0_CLK_EN BIT(25)
>+#define MT7620_CLKCFG1_UPHY1_CLK_EN BIT(22)
>+#define RT_CLKCFG1_UPHY1_CLK_EN BIT(20)
>+#define RT_CLKCFG1_UPHY0_CLK_EN BIT(18)
>+
>+#define USB_PHY_UTMI_8B60M BIT(1)
>+#define UDEV_WAKEUP BIT(0)
>+
>+struct ralink_usb_phy {
>+ struct reset_control *rstdev;
>+ struct reset_control *rsthost;
>+ u32 clk;
>+ struct phy *phy;
>+};
>+
>+static int ralink_usb_phy_power_on(struct phy *_phy)
>+{
>+ struct ralink_usb_phy *phy = phy_get_drvdata(_phy);
>+ u32 t;
>+
>+ /* enable the phy */
>+ rt_sysc_m32(0, phy->clk, RT_SYSC_REG_CLKCFG1);
>+
>+ /* setup host mode */
>+ rt_sysc_m32(0, RT_SYSCFG1_USB0_HOST_MODE, RT_SYSC_REG_SYSCFG1);
>+
>+ /* deassert the reset lines */
>+ reset_control_deassert(phy->rsthost);
>+ reset_control_deassert(phy->rstdev);
>+
>+ /*
>+ * The SDK kernel had a delay of 100ms. however on device
>+ * testing showed that 10ms is enough
>+ */
>+ mdelay(10);
>+
>+ /* print some status info */
>+ t = rt_sysc_r32(RT_SYSC_REG_USB_PHY_CFG);
>+ dev_info(&phy->phy->dev, "remote usb device wakeup %s\n",
>+ (t & UDEV_WAKEUP) ? ("enabled") : ("disabled"));
>+ if (t & USB_PHY_UTMI_8B60M)
>+ dev_info(&phy->phy->dev, "UTMI 8bit 60MHz\n");
>+ else
>+ dev_info(&phy->phy->dev, "UTMI 16bit 30MHz\n");
>+
>+ return 0;
>+}
>+
>+static int ralink_usb_phy_power_off(struct phy *_phy)
>+{
>+ struct ralink_usb_phy *phy = phy_get_drvdata(_phy);
>+
>+ /* disable the phy */
>+ rt_sysc_m32(phy->clk, 0, RT_SYSC_REG_CLKCFG1);
>+
>+ /* assert the reset lines */
>+ reset_control_assert(phy->rstdev);
>+ reset_control_assert(phy->rsthost);
>+
>+ return 0;
>+}
>+
>+static struct phy_ops ralink_usb_phy_ops = {
>+ .power_on = ralink_usb_phy_power_on,
>+ .power_off = ralink_usb_phy_power_off,
>+ .owner = THIS_MODULE,
>+};
>+
>+static const struct of_device_id ralink_usb_phy_of_match[] = {
>+ {
>+ .compatible = "ralink,rt3352-usbphy",
>+ .data = (void *) (RT_CLKCFG1_UPHY1_CLK_EN |
>+ RT_CLKCFG1_UPHY0_CLK_EN)
>+ },
>+ {
>+ .compatible = "mediatek,mt7620-usbphy",
>+ .data = (void *) (MT7620_CLKCFG1_UPHY1_CLK_EN |
>+ MT7620_CLKCFG1_UPHY0_CLK_EN) },
>+ { },
>+};
>+MODULE_DEVICE_TABLE(of, ralink_usb_phy_of_match);
>+
>+static int ralink_usb_phy_probe(struct platform_device *pdev)
>+{
>+ struct device *dev = &pdev->dev;
>+ struct phy_provider *phy_provider;
>+ const struct of_device_id *match;
>+ struct ralink_usb_phy *phy;
>+
>+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
>+ if (!phy)
>+ return -ENOMEM;
>+
>+ match = of_match_device(ralink_usb_phy_of_match, &pdev->dev);
>+ if (!match)
>+ return -ENODEV;
>+
>+ phy->clk = (int) match->data;
>+
>+ phy->rsthost = devm_reset_control_get(&pdev->dev, "host");
>+ if (IS_ERR(phy->rsthost)) {
>+ dev_err(dev, "host reset is missing\n");
>+ return PTR_ERR(phy->rsthost);
>+ }
>+
>+ phy->rstdev = devm_reset_control_get(&pdev->dev, "device");
>+ if (IS_ERR(phy->rstdev)) {
>+ dev_err(dev, "device reset is missing\n");
>+ return PTR_ERR(phy->rstdev);
>+ }
>+
>+ phy->phy = devm_phy_create(dev, NULL, &ralink_usb_phy_ops);
>+ if (IS_ERR(phy->phy)) {
>+ dev_err(dev, "failed to create PHY\n");
>+ return PTR_ERR(phy->phy);
>+ }
>+ phy_set_drvdata(phy->phy, phy);
>+
>+ phy_provider = devm_of_phy_provider_register(dev,
>of_phy_simple_xlate);
>+
>+ return PTR_ERR_OR_ZERO(phy_provider);
>+}
>+
>+static struct platform_driver ralink_usb_phy_driver = {
>+ .probe = ralink_usb_phy_probe,
>+ .driver = {
>+ .of_match_table = ralink_usb_phy_of_match,
>+ .name = "ralink-usb-phy",
>+ }
>+};
>+module_platform_driver(ralink_usb_phy_driver);
>+
>+MODULE_DESCRIPTION("Ralink USB phy driver");
>+MODULE_AUTHOR("John Crispin <[email protected]>");
>+MODULE_LICENSE("GPL v2");
--
James Hogan
Hi James,
On 09/08/17 23:23, James Hogan wrote:
> On 9 August 2017 10:35:39 BST, Harvey Hunt <[email protected]> wrote:
>> From: John Crispin <[email protected]>
>>
>> Add a driver to setup the USB phy on Mediatek/Ralink SoCs.
>> The driver is trivial and only sets up power and host mode.
>>
>> Signed-off-by: John Crispin <[email protected]>
>> Signed-off-by: Harvey Hunt <[email protected]>
>> Cc: [email protected]
>> Cc: [email protected]
>> ---
>> Changes in V4
>> * Remove Allwinner from comment
>> * Depend on COMPILE_TEST
>>
>> Changes in V3
>> * Separate DT bindings
>> * Update Kconfig text
>> * Modify John's email address
>> * Rebase onto v4.13-rc3
>>
>> Changes in V2
>> * remove refcounting
>> * drop empty functions
>> * dont use static globals
>> * use explicit compatible strings
>>
>> drivers/phy/Kconfig | 8 ++
>> drivers/phy/Makefile | 1 +
>> drivers/phy/phy-ralink-usb.c | 173
>> +++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 182 insertions(+)
>> create mode 100644 drivers/phy/phy-ralink-usb.c
>>
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index c1807d4..8fb5260 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -41,6 +41,14 @@ config PHY_PISTACHIO_USB
>> help
>> Enable this to support the USB2.0 PHY on the IMG Pistachio SoC.
>>
>> +config PHY_RALINK_USB
>> + tristate "Ralink USB PHY driver"
>> + select GENERIC_PHY
>> + depends on RALINK || COMPILE_TEST
>
> given that the driver includes a asm/mach-ralink header, the COMPILE_TEST bit may break x86 allmodconfig?
>
> maybe the header should be moved out of arch/mips or it should depend on MIPS only (so a mips allmodconfig catches it, but cant be enabled on x86 even with COMPILE_TEST=y)
>
> cheers
> James
>
[...]
Well spotted - the build does indeed fail for ARCH=x86 allmodconfig.
I could either use:
depends on RALINK || (COMPILE_TEST && MIPS)
or just drop the COMPILE_TEST altogether, as I don't know how many
people are running compile test only on MIPS.
Thanks,
Harvey