2017-11-02 08:34:50

by Wanpeng Li

Subject: [PATCH v3 1/3] KVM: X86: Fix operand size during instruction decoding

From: Wanpeng Li <[email protected]>

Pedro reported:
During tests that we conducted on KVM, we noticed that executing a "PUSH %ES"
instruction under KVM produces different results on both memory and the SP
register depending on whether EPT support is enabled. With EPT the SP is
reduced by 4 bytes (and the written value is 0-padded) but without EPT support
it is only reduced by 2 bytes. The difference can be observed when the CS.DB
field is 1 (32-bit) but not when it's 0 (16-bit).

The internal segment descriptor cache exist even in real/vm8096 mode. The CS.D
also should be respected instead of just default operand-size/66H prefix during
instruction decoding. This patch fixes it by also adjusting operand-size according
to CS.D.

Reported-by: Pedro Fonseca <[email protected]>
Tested-by: Pedro Fonseca <[email protected]>
Cc: Paolo Bonzini <[email protected]>
Cc: Radim Krčmář <[email protected]>
Cc: Nadav Amit <[email protected]>
Cc: Pedro Fonseca <[email protected]>
Signed-off-by: Wanpeng Li <[email protected]>
---
v2 -> v3:
* cleanup the codes
v1 -> v2:
* respect cs.d for real/vm8096, other modes have already
been considered in init_emulate_ctxt().

arch/x86/kvm/emulate.c | 7 +++++++
1 file changed, 7 insertions(+)

diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index 8079d14..6ebc4cb 100644
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate.c
@@ -5000,6 +5000,8 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
bool op_prefix = false;
bool has_seg_override = false;
struct opcode opcode;
+ u16 dummy;
+ struct desc_struct desc;

ctxt->memop.type = OP_NONE;
ctxt->memopp = NULL;
@@ -5020,6 +5022,11 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
case X86EMUL_MODE_VM86:
case X86EMUL_MODE_PROT16:
def_op_bytes = def_ad_bytes = 2;
+ if (mode < X86EMUL_MODE_PROT16) {
+ ctxt->ops->get_segment(ctxt, &dummy, &desc, NULL, VCPU_SREG_CS);
+ if (desc.d)
+ def_op_bytes = 4;
+ }
break;
case X86EMUL_MODE_PROT32:
def_op_bytes = def_ad_bytes = 4;
--
2.7.4


From 1582915622519508071@xxx Thu Nov 02 01:26:14 +0000 2017
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2017-11-02 08:33:01

by Wanpeng Li

Subject: [PATCH v3 2/3] KVM: nVMX: Validate the IA32_BNDCFGS on nested VM-entry

From: Wanpeng Li <[email protected]>

According to the SDM, if the "load IA32_BNDCFGS" VM-entry controls is 1, the
following checks are performed on the field for the IA32_BNDCFGS MSR:
- Bits reserved in the IA32_BNDCFGS MSR must be 0.
- The linear address in bits 63:12 must be canonical.

Cc: Paolo Bonzini <[email protected]>
Cc: Radim Krčmář <[email protected]>
Cc: Jim Mattson <[email protected]>
Signed-off-by: Wanpeng Li <[email protected]>
---
arch/x86/kvm/vmx.c | 7 +++++++
1 file changed, 7 insertions(+)

diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index e6c8ffa..f29f57d 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -10805,6 +10805,13 @@ static int check_vmentry_postreqs(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
return 1;
}

+ if (kvm_mpx_supported() &&
+ (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)) {
+ if (is_noncanonical_address(vmcs12->guest_bndcfgs & PAGE_MASK, vcpu) ||
+ (vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD))
+ return 1;
+ }
+
return 0;
}

--
2.7.4


From 1582903362611613002@xxx Wed Nov 01 22:11:22 +0000 2017
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