2018-01-01 19:34:47

by Bryan O'Donoghue

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Subject: [PATCH v2 15/34] clk: vc5: change vc5_dbl_round_rate() return logic

This patch updates the round_rate() logic here to return zero instead of a
negative number on error.

In conjunction with higher-level changes associated with acting on the
return value of clk_ops->round_rate() it is then possible to have
clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of
the current limitation of 1 Hz to LONG_MAX Hz.

Signed-off-by: Bryan O'Donoghue <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: Vladimir Barinov <[email protected]>
Cc: Alexey Firago <[email protected]>
---
drivers/clk/clk-versaclock5.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c
index 9432122..733b402 100644
--- a/drivers/clk/clk-versaclock5.c
+++ b/drivers/clk/clk-versaclock5.c
@@ -294,7 +294,7 @@ static unsigned long vc5_dbl_round_rate(struct clk_hw *hw, unsigned long rate,
if ((*parent_rate == rate) || ((*parent_rate * 2) == rate))
return rate;
else
- return -EINVAL;
+ return 0;
}

static int vc5_dbl_set_rate(struct clk_hw *hw, unsigned long rate,
--
2.7.4