From: Wadim Egorov <[email protected]>
The DP83867 has a muxing option for the CLK_OUT pin. It is possible
to set CLK_OUT for different channels.
Create a binding to select a specific clock for CLK_OUT pin.
Signed-off-by: Wadim Egorov <[email protected]>
Signed-off-by: Daniel Schultz <[email protected]>
---
drivers/net/phy/dp83867.c | 14 ++++++++++++++
include/dt-bindings/net/ti-dp83867.h | 14 ++++++++++++++
2 files changed, 28 insertions(+)
diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index c1ab976..ffb97c2 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -75,6 +75,8 @@
#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
+#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
+#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
/* CFG4 bits */
#define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
@@ -92,6 +94,7 @@ struct dp83867_private {
int io_impedance;
int port_mirroring;
bool rxctrl_strap_quirk;
+ int clk_output_sel;
};
static int dp83867_ack_interrupt(struct phy_device *phydev)
@@ -160,6 +163,11 @@ static int dp83867_of_init(struct phy_device *phydev)
dp83867->io_impedance = -EINVAL;
/* Optional configuration */
+ if (of_property_read_u32(of_node, "ti,clk-output-sel",
+ &dp83867->clk_output_sel))
+ /* Keep the default value if ti,clk-output-sel is not set */
+ dp83867->clk_output_sel = DP83867_CLK_O_SEL_REF_CLK;
+
if (of_property_read_bool(of_node, "ti,max-output-impedance"))
dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
@@ -295,6 +303,12 @@ static int dp83867_config_init(struct phy_device *phydev)
if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
dp83867_config_port_mirroring(phydev);
+ /* Clock output selection */
+ val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG);
+ val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
+ val |= (dp83867->clk_output_sel << DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);
+ phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, val);
+
return 0;
}
diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h
index 172744a..7b16564 100644
--- a/include/dt-bindings/net/ti-dp83867.h
+++ b/include/dt-bindings/net/ti-dp83867.h
@@ -42,4 +42,18 @@
#define DP83867_RGMIIDCTL_3_75_NS 0xe
#define DP83867_RGMIIDCTL_4_00_NS 0xf
+/* IO_MUX_CFG - Clock output selection */
+#define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0
+#define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1
+#define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2
+#define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3
+#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4
+#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5
+#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6
+#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7
+#define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8
+#define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9
+#define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA
+#define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB
+#define DP83867_CLK_O_SEL_REF_CLK 0xC
#endif
--
2.7.4
From: Wadim Egorov <[email protected]>
Add documentation of ti,clk-output-sel which can be used to select
a specific clock for CLK_OUT.
Signed-off-by: Wadim Egorov <[email protected]>
Signed-off-by: Daniel Schultz <[email protected]>
---
Documentation/devicetree/bindings/net/ti,dp83867.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/ti,dp83867.txt b/Documentation/devicetree/bindings/net/ti,dp83867.txt
index 02c4353..56060c0 100644
--- a/Documentation/devicetree/bindings/net/ti,dp83867.txt
+++ b/Documentation/devicetree/bindings/net/ti,dp83867.txt
@@ -25,6 +25,8 @@ Optional property:
software needs to take when this pin is
strapped in these modes. See data manual
for details.
+ - ti,clk-output-sel - Muxing option for CLK_OUT pin - see dt-bindings/net/ti-dp83867.h
+ for applicable values.
Note: ti,min-output-impedance and ti,max-output-impedance are mutually
exclusive. When both properties are present ti,max-output-impedance
--
2.7.4
On Tue, Feb 13, 2018 at 10:42:31AM +0100, Daniel Schultz wrote:
> From: Wadim Egorov <[email protected]>
>
> The DP83867 has a muxing option for the CLK_OUT pin. It is possible
> to set CLK_OUT for different channels.
> Create a binding to select a specific clock for CLK_OUT pin.
>
> Signed-off-by: Wadim Egorov <[email protected]>
> Signed-off-by: Daniel Schultz <[email protected]>
> ---
> drivers/net/phy/dp83867.c | 14 ++++++++++++++
> include/dt-bindings/net/ti-dp83867.h | 14 ++++++++++++++
> 2 files changed, 28 insertions(+)
>
> diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
> index c1ab976..ffb97c2 100644
> --- a/drivers/net/phy/dp83867.c
> +++ b/drivers/net/phy/dp83867.c
> @@ -75,6 +75,8 @@
>
> #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
> #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
> +#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
> +#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
>
> /* CFG4 bits */
> #define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
> @@ -92,6 +94,7 @@ struct dp83867_private {
> int io_impedance;
> int port_mirroring;
> bool rxctrl_strap_quirk;
> + int clk_output_sel;
> };
>
> static int dp83867_ack_interrupt(struct phy_device *phydev)
> @@ -160,6 +163,11 @@ static int dp83867_of_init(struct phy_device *phydev)
> dp83867->io_impedance = -EINVAL;
>
> /* Optional configuration */
> + if (of_property_read_u32(of_node, "ti,clk-output-sel",
> + &dp83867->clk_output_sel))
> + /* Keep the default value if ti,clk-output-sel is not set */
> + dp83867->clk_output_sel = DP83867_CLK_O_SEL_REF_CLK;
> +
Hi Daniel
Normally you don't put registers values into device tree. But in this
case, i don't see a better alternative.
Please add a range check. Values > 01101 are reserved.
> if (of_property_read_bool(of_node, "ti,max-output-impedance"))
> dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
> else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
> @@ -295,6 +303,12 @@ static int dp83867_config_init(struct phy_device *phydev)
> if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
> dp83867_config_port_mirroring(phydev);
>
> + /* Clock output selection */
> + val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG);
> + val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
This could be a problem. If i'm reading the datasheet correctly,
clearing this bit will override the strapping. A hardware engineer
might of included a resistor to disable the clock output, saving some
power. And here you unconditionally turn it back on again. Since
ti,clk-output-sel is optional, i would prefer that you don't touch
this register if the property is not present.
Andrew