Rockchip recommends to run the CPU cores only with operations points of
1.6 GHz or lower.
Removed the cpu0 node with too high operation points and use the default
values instead.
Signed-off-by: Daniel Schultz <[email protected]>
---
arch/arm/boot/dts/rk3288-phycore-som.dtsi | 20 --------------------
1 file changed, 20 deletions(-)
diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rk3288-phycore-som.dtsi
index 99cfae8..5eae477 100644
--- a/arch/arm/boot/dts/rk3288-phycore-som.dtsi
+++ b/arch/arm/boot/dts/rk3288-phycore-som.dtsi
@@ -110,26 +110,6 @@
};
};
-&cpu0 {
- cpu0-supply = <&vdd_cpu>;
- operating-points = <
- /* KHz uV */
- 1800000 1400000
- 1608000 1350000
- 1512000 1300000
- 1416000 1200000
- 1200000 1100000
- 1008000 1050000
- 816000 1000000
- 696000 950000
- 600000 900000
- 408000 900000
- 312000 900000
- 216000 900000
- 126000 900000
- >;
-};
-
&emmc {
status = "okay";
bus-width = <8>;
--
2.7.4
From: Wadim Egorov <[email protected]>
The card is powered by the RK818 switch vdd_sd which is supplied
by VCC9 (VDD_3V3_IO).
Signed-off-by: Wadim Egorov <[email protected]>
Signed-off-by: Daniel Schultz <[email protected]>
---
arch/arm/boot/dts/rk3288-phycore-rdk.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/rk3288-phycore-rdk.dts b/arch/arm/boot/dts/rk3288-phycore-rdk.dts
index 1241cbc..ecb26f0 100644
--- a/arch/arm/boot/dts/rk3288-phycore-rdk.dts
+++ b/arch/arm/boot/dts/rk3288-phycore-rdk.dts
@@ -265,7 +265,7 @@
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
- vmmc-supply = <&vdd_io_sd>;
+ vmmc-supply = <&vdd_sd>;
vqmmc-supply = <&vdd_io_sd>;
status = "okay";
};
--
2.7.4
From: Wadim Egorov <[email protected]>
The phyCORE-RK3288 RDK could enable SD3.0 card but need vdd_io_sd to
support the voltage range from 1.8V to 3.3V.
And we have also to add relevant UHS modes to the sdmmc node.
Let's also turn off the vdd_io_sd regulator in suspend state.
Signed-off-by: Wadim Egorov <[email protected]>
Signed-off-by: Daniel Schultz <[email protected]>
---
arch/arm/boot/dts/rk3288-phycore-rdk.dts | 4 ++++
arch/arm/boot/dts/rk3288-phycore-som.dtsi | 5 ++---
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/rk3288-phycore-rdk.dts b/arch/arm/boot/dts/rk3288-phycore-rdk.dts
index ecb26f0..985743f 100644
--- a/arch/arm/boot/dts/rk3288-phycore-rdk.dts
+++ b/arch/arm/boot/dts/rk3288-phycore-rdk.dts
@@ -265,6 +265,10 @@
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
vmmc-supply = <&vdd_sd>;
vqmmc-supply = <&vdd_io_sd>;
status = "okay";
diff --git a/arch/arm/boot/dts/rk3288-phycore-som.dtsi b/arch/arm/boot/dts/rk3288-phycore-som.dtsi
index 5eae477..f13bcb1 100644
--- a/arch/arm/boot/dts/rk3288-phycore-som.dtsi
+++ b/arch/arm/boot/dts/rk3288-phycore-som.dtsi
@@ -336,11 +336,10 @@
regulator-name = "vdd_io_sd";
regulator-always-on;
regulator-boot-on;
- regulator-min-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-state-mem {
- regulator-on-in-suspend;
- regulator-suspend-microvolt = <3300000>;
+ regulator-off-in-suspend;
};
};
};
--
2.7.4
Am Dienstag, 13. Februar 2018, 10:44:32 CET schrieb Daniel Schultz:
> Rockchip recommends to run the CPU cores only with operations points of
> 1.6 GHz or lower.
>
> Removed the cpu0 node with too high operation points and use the default
> values instead.
>
> Signed-off-by: Daniel Schultz <[email protected]>
applied all 3 for 4.17
Thanks
Heiko
On 02/14/2018 09:07 AM, Heiko Stübner wrote:
> Am Dienstag, 13. Februar 2018, 10:44:32 CET schrieb Daniel Schultz:
>> Rockchip recommends to run the CPU cores only with operations points of
>> 1.6 GHz or lower.
>>
>> Removed the cpu0 node with too high operation points and use the default
>> values instead.
>>
>> Signed-off-by: Daniel Schultz <[email protected]>
> applied all 3 for 4.17
>
Thanks! I think I should have mentioned this earlier, but can you please add
ARM: dts: rockchip: phycore: Remove 1.8 GHz operation point
to the stable tree v4.14?
--
Mit freundlichen Grüßen,
With best regards,
Daniel Schultz
Hi Daniel,
Am Mittwoch, 14. Februar 2018, 16:32:44 CET schrieb Daniel Schultz:
> On 02/14/2018 09:07 AM, Heiko St?bner wrote:
> > Am Dienstag, 13. Februar 2018, 10:44:32 CET schrieb Daniel Schultz:
> >> Rockchip recommends to run the CPU cores only with operations points of
> >> 1.6 GHz or lower.
> >>
> >> Removed the cpu0 node with too high operation points and use the default
> >> values instead.
> >>
> >> Signed-off-by: Daniel Schultz <[email protected]>
> >
> > applied all 3 for 4.17
>
> Thanks! I think I should have mentioned this earlier, but can you please add
> ARM: dts: rockchip: phycore: Remove 1.8 GHz operation point
> to the stable tree v4.14?
I've moved that patch to the fixes branch and added the necessary
Fixes and cc-stable tags, so it should eventually reach stable kernels
as well.
Heiko