2018-08-04 07:34:59

by Levin

Subject: [PATCH v0] clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399

From: Levin Du <[email protected]>

PWM2 is commonly used to control voltage of PWM regulator of VDD_LOG in
RK3399. On the Firefly-RK3399 board, PWM2 outputs 40 KHz square wave
from power on and the VDD_LOG is about 0.9V. When the kernel boots
normally into the system, the PWM2 keeps outputing PWM signal.

But the kernel hangs randomly after "Starting kernel ..." line on that
board. When it happens, PWM2 outputs high level which causes VDD_LOG
drops to 0.4V below the normal operating voltage.

By adding "pclk_rkpwm_pmu" to the rk3399_pmucru_critical_clocks array,
PWM clock is ensured to be prepared at startup and the PWM2 output is
normal. After repeated tests, the early boot hang is gone.

This patch works on both Firefly-RK3399 and ROC-RK3399-PC boards.

Signed-off-by: Levin Du <[email protected]>

---

drivers/clk/rockchip/clk-rk3399.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 2a8634a..5a62814 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -1523,6 +1523,7 @@ static const char *const rk3399_pmucru_critical_clocks[] __initconst = {
"pclk_pmu_src",
"fclk_cm0s_src_pmu",
"clk_timer_src_pmu",
+ "pclk_rkpwm_pmu",
};

static void __init rk3399_clk_init(struct device_node *np)
--
2.7.4

2018-08-06 08:11:30

by Heiko Stuebner

Subject: Re: [PATCH v0] clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399

Hi Levin,

Am Samstag, 4. August 2018, 09:31:02 CEST schrieb [email protected]:
> From: Levin Du <[email protected]>
>
> PWM2 is commonly used to control voltage of PWM regulator of VDD_LOG in
> RK3399. On the Firefly-RK3399 board, PWM2 outputs 40 KHz square wave
> from power on and the VDD_LOG is about 0.9V. When the kernel boots
> normally into the system, the PWM2 keeps outputing PWM signal.
>
> But the kernel hangs randomly after "Starting kernel ..." line on that
> board. When it happens, PWM2 outputs high level which causes VDD_LOG
> drops to 0.4V below the normal operating voltage.
>
> By adding "pclk_rkpwm_pmu" to the rk3399_pmucru_critical_clocks array,
> PWM clock is ensured to be prepared at startup and the PWM2 output is
> normal. After repeated tests, the early boot hang is gone.
>
> This patch works on both Firefly-RK3399 and ROC-RK3399-PC boards.
>
> Signed-off-by: Levin Du <[email protected]>

applied to my clk-branch

Thanks for tracking that down
Heiko