Add MFR_ID information, 0x002C, related to the Micron flash.
Currently, MFR_ID 0x0020 is being specified as Micron flash ID but
these are actually CFI ID of STMicro flashes.
Rename SNOR_MFR_MICRON to SNOR_MFR_ST and add entry for
SNOR_MFR_MICRON having CFI ID value of Micron flash.
Add entry of mt35xu512aba [1] flash in spi_nor_ids table.
[1] https://www.micron.com/resource-details/0b74b806-bbf1-4c24-b07b-35e2799bb6ff
Yogesh Gaur (2):
mtd: spi-nor: add macros related to MICRON flash
mtd: spi-nor: add entry for mt35xu512aba flash
Changes for v2:
- Removed checkpatch warning, 80 character limit, in patch
'mtd: spi-nor: add entry for mt35xu512aba flash'.
drivers/mtd/spi-nor/spi-nor.c | 13 ++++++++++---
include/linux/mtd/cfi.h | 1 +
include/linux/mtd/spi-nor.h | 3 ++-
3 files changed, 13 insertions(+), 4 deletions(-)
--
2.7.4
Some MICRON related macros in spi-nor domain were ST.
Rename entries related to STMicroelectronics under macro SNOR_MFR_ST.
Added entry of MFR Id for Micron flashes, 0x002C.
Signed-off-by: Yogesh Gaur <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
---
Changes for v2:
- None
drivers/mtd/spi-nor/spi-nor.c | 9 ++++++---
include/linux/mtd/cfi.h | 1 +
include/linux/mtd/spi-nor.h | 3 ++-
3 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 9407ca5..b8b494f 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -284,6 +284,7 @@ static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
u8 cmd;
switch (JEDEC_MFR(info)) {
+ case SNOR_MFR_ST:
case SNOR_MFR_MICRON:
/* Some Micron need WREN command; all will accept it */
need_wren = true;
@@ -1388,7 +1389,7 @@ static const struct flash_info spi_nor_ids[] = {
{ "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
- /* Micron */
+ /* Micron <--> ST Micro */
{ "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) },
{ "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
{ "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
@@ -3223,6 +3224,7 @@ static int spi_nor_init_params(struct spi_nor *nor,
params->quad_enable = macronix_quad_enable;
break;
+ case SNOR_MFR_ST:
case SNOR_MFR_MICRON:
break;
@@ -3671,8 +3673,9 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
mtd->_resume = spi_nor_resume;
/* NOR protection support for STmicro/Micron chips and similar */
- if (JEDEC_MFR(info) == SNOR_MFR_MICRON ||
- info->flags & SPI_NOR_HAS_LOCK) {
+ if (JEDEC_MFR(info) == SNOR_MFR_ST ||
+ JEDEC_MFR(info) == SNOR_MFR_MICRON ||
+ info->flags & SPI_NOR_HAS_LOCK) {
nor->flash_lock = stm_lock;
nor->flash_unlock = stm_unlock;
nor->flash_is_locked = stm_is_locked;
diff --git a/include/linux/mtd/cfi.h b/include/linux/mtd/cfi.h
index 9b57a9b..cbf7716 100644
--- a/include/linux/mtd/cfi.h
+++ b/include/linux/mtd/cfi.h
@@ -377,6 +377,7 @@ struct cfi_fixup {
#define CFI_MFR_SHARP 0x00B0
#define CFI_MFR_SST 0x00BF
#define CFI_MFR_ST 0x0020 /* STMicroelectronics */
+#define CFI_MFR_MICRON 0x002C /* Micron */
#define CFI_MFR_TOSHIBA 0x0098
#define CFI_MFR_WINBOND 0x00DA
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 7f0c730..8b1acf6 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -23,7 +23,8 @@
#define SNOR_MFR_ATMEL CFI_MFR_ATMEL
#define SNOR_MFR_GIGADEVICE 0xc8
#define SNOR_MFR_INTEL CFI_MFR_INTEL
-#define SNOR_MFR_MICRON CFI_MFR_ST /* ST Micro <--> Micron */
+#define SNOR_MFR_ST CFI_MFR_ST /* ST Micro */
+#define SNOR_MFR_MICRON CFI_MFR_MICRON /* Micron */
#define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
#define SNOR_MFR_SPANSION CFI_MFR_AMD
#define SNOR_MFR_SST CFI_MFR_SST
--
2.7.4
Add entry for mt35xu512aba Micron NOR flash.
This flash is having uniform sector erase size of 128KB, have
support of FSR(flag status register), flash size is 64MB and
supports 4-byte commands.
Signed-off-by: Yogesh Gaur <[email protected]>
---
Changes for v2:
- Removed checkpatch warning, 80 character limit.
drivers/mtd/spi-nor/spi-nor.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index b8b494f..e0d95ac 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1405,6 +1405,10 @@ static const struct flash_info spi_nor_ids[] = {
{ "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
+ /* Micron */
+ { "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
+ SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES) },
+
/* PMC */
{ "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
{ "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
--
2.7.4
On 10/11/2018 11:15 AM, Yogesh Narayan Gaur wrote:
> Add entry for mt35xu512aba Micron NOR flash.
> This flash is having uniform sector erase size of 128KB, have
> support of FSR(flag status register), flash size is 64MB and
> supports 4-byte commands.
>
> Signed-off-by: Yogesh Gaur <[email protected]>
> ---
> Changes for v2:
> - Removed checkpatch warning, 80 character limit.
>
> drivers/mtd/spi-nor/spi-nor.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index b8b494f..e0d95ac 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -1405,6 +1405,10 @@ static const struct flash_info spi_nor_ids[] = {
> { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>
> + /* Micron */
> + { "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
> + SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES) },
> +
The style is slightly different from what Brian proposed back in
9648388fc7737365be7a8092e77df78ccc2cd1a4. For consistency reasons, I think we
should use the same style in all entries.
Since I verified the correctness of the patch and my comment targets just a
cosmetic change, I'll let the maintainers decide:
Reviewed-by: Tudor Ambarus <[email protected]>
Hi Tudor,
> -----Original Message-----
> From: Tudor Ambarus [mailto:[email protected]]
> Sent: Thursday, October 11, 2018 9:33 PM
> To: Yogesh Narayan Gaur <[email protected]>; linux-
> [email protected]; [email protected]
> Cc: [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]
> Subject: Re: [PATCH v2 2/2] mtd: spi-nor: add entry for mt35xu512aba flash
>
>
>
> On 10/11/2018 11:15 AM, Yogesh Narayan Gaur wrote:
> > Add entry for mt35xu512aba Micron NOR flash.
> > This flash is having uniform sector erase size of 128KB, have support
> > of FSR(flag status register), flash size is 64MB and supports 4-byte
> > commands.
> >
> > Signed-off-by: Yogesh Gaur <[email protected]>
> > ---
> > Changes for v2:
> > - Removed checkpatch warning, 80 character limit.
> >
> > drivers/mtd/spi-nor/spi-nor.c | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/mtd/spi-nor/spi-nor.c
> > b/drivers/mtd/spi-nor/spi-nor.c index b8b494f..e0d95ac 100644
> > --- a/drivers/mtd/spi-nor/spi-nor.c
> > +++ b/drivers/mtd/spi-nor/spi-nor.c
> > @@ -1405,6 +1405,10 @@ static const struct flash_info spi_nor_ids[] = {
> > { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR
> | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> > { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K |
> USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> >
> > + /* Micron */
> > + { "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
> > + SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES) },
> > +
>
> The style is slightly different from what Brian proposed back in
> 9648388fc7737365be7a8092e77df78ccc2cd1a4. For consistency reasons, I think
> we should use the same style in all entries.
>
Ok, I have send the next version of the patches with the style changes as proposed by Brian.
--
Regards
Yogesh Gaur.
> Since I verified the correctness of the patch and my comment targets just a
> cosmetic change, I'll let the maintainers decide:
>
> Reviewed-by: Tudor Ambarus <[email protected]>