this series of patch include below changes:
1. Add MT8183 SoC support in Mediatek MMC DT bindings
2. Fill mmc->actual_clock
3. Fix cannot receive new request issue
4. Tune CMD/DATA together to save tuning time
5. Add MT8183 MMC driver support
6. Refine the tuning method to drop too much redundant code
Chaotian Jing (6):
mmc: dt-bindings: add support for MT8183 SoC
mmc: mediatek: fill the actual clock for mmc debugfs
mmc: mediatek: fix cannot receive new request when msdc_cmd_is_ready
fail
mmc: mediatek: tune CMD/DATA together
mmc: mediatek: add MT8183 MMC driver support
mmc: mediatek: drop too much code of tuning method
Documentation/devicetree/bindings/mmc/mtk-sd.txt | 1 +
drivers/mmc/host/mtk-sd.c | 292 ++++++++++++++++++++---
2 files changed, 254 insertions(+), 39 deletions(-)
--
1.8.1.1.dirty
Add the devicetree binding for MT8183 SoC
Signed-off-by: Chaotian Jing <[email protected]>
---
Documentation/devicetree/bindings/mmc/mtk-sd.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
index f2208f4..f5bcda3 100644
--- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt
+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt
@@ -10,6 +10,7 @@ Required properties:
- compatible: value should be either of the following.
"mediatek,mt8135-mmc": for mmc host ip compatible with mt8135
"mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
+ "mediatek,mt8183-mmc": for mmc host ip compatible with mt8183
"mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
"mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
"mediatek,mt7622-mmc": for MT7622 SoC
--
1.8.1.1.dirty
for MSDC IP which supports both data tune and async fifo, it can
tune cmd/data together. which can save the time and make the tune
result of CMD more stable as data line are 4bit or 8bit.
Signed-off-by: Chaotian Jing <[email protected]>
---
drivers/mmc/host/mtk-sd.c | 87 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 87 insertions(+)
diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index fe80a1d..09d7e44 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -1773,12 +1773,98 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
return final_delay == 0xff ? -EIO : 0;
}
+/*
+ * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
+ * together, which can save the tuning time.
+ */
+static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
+{
+ struct msdc_host *host = mmc_priv(mmc);
+ u32 rise_delay = 0, fall_delay = 0;
+ struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
+ u8 final_delay, final_maxlen;
+ u32 tune_reg = host->dev_comp->pad_tune_reg;
+ int i, ret;
+
+ sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
+ host->latch_ck);
+
+ sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
+ sdr_clr_bits(host->base + MSDC_IOCON,
+ MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
+ for (i = 0 ; i < PAD_DELAY_MAX; i++) {
+ sdr_set_field(host->base + tune_reg,
+ MSDC_PAD_TUNE_CMDRDLY, i);
+ sdr_set_field(host->base + tune_reg,
+ MSDC_PAD_TUNE_DATRRDLY, i);
+ ret = mmc_send_tuning(mmc, opcode, NULL);
+ if (!ret)
+ rise_delay |= (1 << i);
+ }
+ final_rise_delay = get_best_delay(host, rise_delay);
+ /* if rising edge has enough margin, then do not scan falling edge */
+ if (final_rise_delay.maxlen >= 12 ||
+ (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
+ goto skip_fall;
+
+ sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
+ sdr_set_bits(host->base + MSDC_IOCON,
+ MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
+ for (i = 0; i < PAD_DELAY_MAX; i++) {
+ sdr_set_field(host->base + tune_reg,
+ MSDC_PAD_TUNE_CMDRDLY, i);
+ sdr_set_field(host->base + tune_reg,
+ MSDC_PAD_TUNE_DATRRDLY, i);
+ ret = mmc_send_tuning(mmc, opcode, NULL);
+ if (!ret)
+ fall_delay |= (1 << i);
+ }
+ final_fall_delay = get_best_delay(host, fall_delay);
+
+skip_fall:
+ final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
+ if (final_maxlen == final_rise_delay.maxlen) {
+ sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
+ sdr_clr_bits(host->base + MSDC_IOCON,
+ MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
+ sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
+ final_rise_delay.final_phase);
+ sdr_set_field(host->base + tune_reg,
+ MSDC_PAD_TUNE_DATRRDLY,
+ final_rise_delay.final_phase);
+ final_delay = final_rise_delay.final_phase;
+ } else {
+ sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
+ sdr_set_bits(host->base + MSDC_IOCON,
+ MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
+ sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
+ final_fall_delay.final_phase);
+ sdr_set_field(host->base + tune_reg,
+ MSDC_PAD_TUNE_DATRRDLY,
+ final_fall_delay.final_phase);
+ final_delay = final_fall_delay.final_phase;
+ }
+
+ dev_dbg(host->dev, "Final pad delay: %x\n", final_delay);
+ return final_delay == 0xff ? -EIO : 0;
+}
+
static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
{
struct msdc_host *host = mmc_priv(mmc);
int ret;
u32 tune_reg = host->dev_comp->pad_tune_reg;
+ if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
+ ret = msdc_tune_together(mmc, opcode);
+ if (host->hs400_mode) {
+ sdr_clr_bits(host->base + MSDC_IOCON,
+ MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
+ sdr_set_field(host->base + tune_reg,
+ MSDC_PAD_TUNE_DATRRDLY, 0);
+ }
+ goto tune_done;
+ }
if (host->hs400_mode &&
host->dev_comp->hs400_tune)
ret = hs400_tune_response(mmc, opcode);
@@ -1794,6 +1880,7 @@ static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
dev_err(host->dev, "Tune data fail!\n");
}
+tune_done:
host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
--
1.8.1.1.dirty
when msdc_cmd_is_ready return fail, the req_timeout work has not been
inited and cancel_delayed_work() will return false, then, the request
return directly and never call mmc_request_done().
so need call mod_delayed_work() before msdc_cmd_is_ready()
Signed-off-by: Chaotian Jing <[email protected]>
---
drivers/mmc/host/mtk-sd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index ef45f1d..fe80a1d 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -1059,6 +1059,7 @@ static void msdc_start_command(struct msdc_host *host,
WARN_ON(host->cmd);
host->cmd = cmd;
+ mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
if (!msdc_cmd_is_ready(host, mrq, cmd))
return;
@@ -1070,7 +1071,6 @@ static void msdc_start_command(struct msdc_host *host,
cmd->error = 0;
rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
- mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
writel(cmd->arg, host->base + SDC_ARG);
--
1.8.1.1.dirty
MT8183 puts the tune register at top layer, so need add new code
to support it.
Signed-off-by: Chaotian Jing <[email protected]>
---
drivers/mmc/host/mtk-sd.c | 283 ++++++++++++++++++++++++++++++++++++++--------
1 file changed, 233 insertions(+), 50 deletions(-)
diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index 09d7e44..5b26f2f 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -87,6 +87,13 @@
#define SDC_FIFO_CFG 0x228
/*--------------------------------------------------------------------------*/
+/* Top Pad Register Offset */
+/*--------------------------------------------------------------------------*/
+#define EMMC_TOP_CONTROL 0x00
+#define EMMC_TOP_CMD 0x04
+#define EMMC50_PAD_DS_TUNE 0x0c
+
+/*--------------------------------------------------------------------------*/
/* Register Mask */
/*--------------------------------------------------------------------------*/
@@ -261,6 +268,23 @@
#define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */
#define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */
+/* EMMC_TOP_CONTROL mask */
+#define PAD_RXDLY_SEL (0x1 << 0) /* RW */
+#define DELAY_EN (0x1 << 1) /* RW */
+#define PAD_DAT_RD_RXDLY2 (0x1f << 2) /* RW */
+#define PAD_DAT_RD_RXDLY (0x1f << 7) /* RW */
+#define PAD_DAT_RD_RXDLY2_SEL (0x1 << 12) /* RW */
+#define PAD_DAT_RD_RXDLY_SEL (0x1 << 13) /* RW */
+#define DATA_K_VALUE_SEL (0x1 << 14) /* RW */
+#define SDC_RX_ENH_EN (0x1 << 15) /* TW */
+
+/* EMMC_TOP_CMD mask */
+#define PAD_CMD_RXDLY2 (0x1f << 0) /* RW */
+#define PAD_CMD_RXDLY (0x1f << 5) /* RW */
+#define PAD_CMD_RD_RXDLY2_SEL (0x1 << 10) /* RW */
+#define PAD_CMD_RD_RXDLY_SEL (0x1 << 11) /* RW */
+#define PAD_CMD_TX_DLY (0x1f << 12) /* RW */
+
#define REQ_CMD_EIO (0x1 << 0)
#define REQ_CMD_TMO (0x1 << 1)
#define REQ_DAT_ERR (0x1 << 2)
@@ -333,6 +357,9 @@ struct msdc_save_para {
u32 emmc50_cfg0;
u32 emmc50_cfg3;
u32 sdc_fifo_cfg;
+ u32 emmc_top_control;
+ u32 emmc_top_cmd;
+ u32 emmc50_pad_ds_tune;
};
struct mtk_mmc_compatible {
@@ -351,6 +378,8 @@ struct msdc_tune_para {
u32 iocon;
u32 pad_tune;
u32 pad_cmd_tune;
+ u32 emmc_top_control;
+ u32 emmc_top_cmd;
};
struct msdc_delay_phase {
@@ -372,6 +401,7 @@ struct msdc_host {
int error;
void __iomem *base; /* host base address */
+ void __iomem *top_base; /* host top register base address */
struct msdc_dma dma; /* dma channel */
u64 dma_mask;
@@ -429,6 +459,18 @@ struct msdc_host {
.support_64g = false,
};
+static const struct mtk_mmc_compatible mt8183_compat = {
+ .clk_div_bits = 12,
+ .hs400_tune = false,
+ .pad_tune_reg = MSDC_PAD_TUNE0,
+ .async_fifo = true,
+ .data_tune = true,
+ .busy_check = true,
+ .stop_clk_fix = true,
+ .enhance_rx = true,
+ .support_64g = true,
+};
+
static const struct mtk_mmc_compatible mt2701_compat = {
.clk_div_bits = 12,
.hs400_tune = false,
@@ -468,6 +510,7 @@ struct msdc_host {
static const struct of_device_id msdc_of_ids[] = {
{ .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
{ .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
+ { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
{ .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
{ .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
{ .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
@@ -777,12 +820,28 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
*/
if (host->mmc->actual_clock <= 52000000) {
writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
- writel(host->def_tune_para.pad_tune, host->base + tune_reg);
+ if (host->top_base) {
+ writel(host->def_tune_para.emmc_top_control,
+ host->top_base + EMMC_TOP_CONTROL);
+ writel(host->def_tune_para.emmc_top_cmd,
+ host->top_base + EMMC_TOP_CMD);
+ } else {
+ writel(host->def_tune_para.pad_tune,
+ host->base + tune_reg);
+ }
} else {
writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
- writel(host->saved_tune_para.pad_tune, host->base + tune_reg);
writel(host->saved_tune_para.pad_cmd_tune,
host->base + PAD_CMD_TUNE);
+ if (host->top_base) {
+ writel(host->saved_tune_para.emmc_top_control,
+ host->top_base + EMMC_TOP_CONTROL);
+ writel(host->saved_tune_para.emmc_top_cmd,
+ host->top_base + EMMC_TOP_CMD);
+ } else {
+ writel(host->saved_tune_para.pad_tune,
+ host->base + tune_reg);
+ }
}
if (timing == MMC_TIMING_MMC_HS400 &&
@@ -1355,7 +1414,12 @@ static void msdc_init_hw(struct msdc_host *host)
val = readl(host->base + MSDC_INT);
writel(val, host->base + MSDC_INT);
- writel(0, host->base + tune_reg);
+ if (host->top_base) {
+ writel(0, host->top_base + EMMC_TOP_CONTROL);
+ writel(0, host->top_base + EMMC_TOP_CMD);
+ } else {
+ writel(0, host->base + tune_reg);
+ }
writel(0, host->base + MSDC_IOCON);
sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
writel(0x403c0046, host->base + MSDC_PATCH_BIT);
@@ -1379,8 +1443,12 @@ static void msdc_init_hw(struct msdc_host *host)
sdr_set_field(host->base + MSDC_PATCH_BIT2,
MSDC_PB2_RESPWAIT, 3);
if (host->dev_comp->enhance_rx) {
- sdr_set_bits(host->base + SDC_ADV_CFG0,
- SDC_RX_ENHANCE_EN);
+ if (host->top_base)
+ sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
+ SDC_RX_ENH_EN);
+ else
+ sdr_set_bits(host->base + SDC_ADV_CFG0,
+ SDC_RX_ENHANCE_EN);
} else {
sdr_set_field(host->base + MSDC_PATCH_BIT2,
MSDC_PB2_RESPSTSENSEL, 2);
@@ -1398,11 +1466,26 @@ static void msdc_init_hw(struct msdc_host *host)
sdr_set_bits(host->base + MSDC_PATCH_BIT2,
MSDC_PB2_SUPPORT_64G);
if (host->dev_comp->data_tune) {
- sdr_set_bits(host->base + tune_reg,
- MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL);
+ if (host->top_base) {
+ sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
+ PAD_DAT_RD_RXDLY_SEL);
+ sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL,
+ DATA_K_VALUE_SEL);
+ sdr_set_bits(host->top_base + EMMC_TOP_CMD,
+ PAD_CMD_RD_RXDLY_SEL);
+ } else {
+ sdr_set_bits(host->base + tune_reg,
+ MSDC_PAD_TUNE_RD_SEL |
+ MSDC_PAD_TUNE_CMD_SEL);
+ }
} else {
/* choose clock tune */
- sdr_set_bits(host->base + tune_reg, MSDC_PAD_TUNE_RXDLYSEL);
+ if (host->top_base)
+ sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
+ PAD_RXDLY_SEL);
+ else
+ sdr_set_bits(host->base + tune_reg,
+ MSDC_PAD_TUNE_RXDLYSEL);
}
/* Configure to enable SDIO mode.
@@ -1417,9 +1500,20 @@ static void msdc_init_hw(struct msdc_host *host)
sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
- host->def_tune_para.pad_tune = readl(host->base + tune_reg);
host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
- host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
+ if (host->top_base) {
+ host->def_tune_para.emmc_top_control =
+ readl(host->top_base + EMMC_TOP_CONTROL);
+ host->def_tune_para.emmc_top_cmd =
+ readl(host->top_base + EMMC_TOP_CMD);
+ host->saved_tune_para.emmc_top_control =
+ readl(host->top_base + EMMC_TOP_CONTROL);
+ host->saved_tune_para.emmc_top_cmd =
+ readl(host->top_base + EMMC_TOP_CMD);
+ } else {
+ host->def_tune_para.pad_tune = readl(host->base + tune_reg);
+ host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
+ }
dev_dbg(host->dev, "init hardware done!");
}
@@ -1587,8 +1681,12 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
for (i = 0 ; i < PAD_DELAY_MAX; i++) {
- sdr_set_field(host->base + tune_reg,
- MSDC_PAD_TUNE_CMDRDLY, i);
+ if (host->top_base)
+ sdr_set_field(host->top_base + EMMC_TOP_CMD,
+ PAD_CMD_RXDLY, i);
+ else
+ sdr_set_field(host->base + tune_reg,
+ MSDC_PAD_TUNE_CMDRDLY, i);
/*
* Using the same parameters, it may sometimes pass the test,
* but sometimes it may fail. To make sure the parameters are
@@ -1612,8 +1710,12 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
for (i = 0; i < PAD_DELAY_MAX; i++) {
- sdr_set_field(host->base + tune_reg,
- MSDC_PAD_TUNE_CMDRDLY, i);
+ if (host->top_base)
+ sdr_set_field(host->top_base + EMMC_TOP_CMD,
+ PAD_CMD_RXDLY, i);
+ else
+ sdr_set_field(host->base + tune_reg,
+ MSDC_PAD_TUNE_CMDRDLY, i);
/*
* Using the same parameters, it may sometimes pass the test,
* but sometimes it may fail. To make sure the parameters are
@@ -1637,13 +1739,23 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
final_maxlen = final_fall_delay.maxlen;
if (final_maxlen == final_rise_delay.maxlen) {
sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
- sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
- final_rise_delay.final_phase);
+ if (host->top_base)
+ sdr_set_field(host->base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
+ final_rise_delay.final_phase);
+ else
+ sdr_set_field(host->base + tune_reg,
+ MSDC_PAD_TUNE_CMDRDLY,
+ final_rise_delay.final_phase);
final_delay = final_rise_delay.final_phase;
} else {
sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
- sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
- final_fall_delay.final_phase);
+ if (host->top_base)
+ sdr_set_field(host->base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
+ final_fall_delay.final_phase);
+ else
+ sdr_set_field(host->base + tune_reg,
+ MSDC_PAD_TUNE_CMDRDLY,
+ final_fall_delay.final_phase);
final_delay = final_fall_delay.final_phase;
}
if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
@@ -1728,8 +1840,12 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
for (i = 0 ; i < PAD_DELAY_MAX; i++) {
- sdr_set_field(host->base + tune_reg,
- MSDC_PAD_TUNE_DATRRDLY, i);
+ if (host->top_base)
+ sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
+ PAD_DAT_RD_RXDLY, i);
+ else
+ sdr_set_field(host->base + tune_reg,
+ MSDC_PAD_TUNE_DATRRDLY, i);
ret = mmc_send_tuning(mmc, opcode, NULL);
if (!ret)
rise_delay |= (1 << i);
@@ -1743,8 +1859,12 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
for (i = 0; i < PAD_DELAY_MAX; i++) {
- sdr_set_field(host->base + tune_reg,
- MSDC_PAD_TUNE_DATRRDLY, i);
+ if (host->top_base)
+ sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
+ PAD_DAT_RD_RXDLY, i);
+ else
+ sdr_set_field(host->base + tune_reg,
+ MSDC_PAD_TUNE_DATRRDLY, i);
ret = mmc_send_tuning(mmc, opcode, NULL);
if (!ret)
fall_delay |= (1 << i);
@@ -1756,16 +1876,26 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
if (final_maxlen == final_rise_delay.maxlen) {
sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
- sdr_set_field(host->base + tune_reg,
- MSDC_PAD_TUNE_DATRRDLY,
- final_rise_delay.final_phase);
+ if (host->top_base)
+ sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
+ PAD_DAT_RD_RXDLY,
+ final_rise_delay.final_phase);
+ else
+ sdr_set_field(host->base + tune_reg,
+ MSDC_PAD_TUNE_DATRRDLY,
+ final_rise_delay.final_phase);
final_delay = final_rise_delay.final_phase;
} else {
sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
- sdr_set_field(host->base + tune_reg,
- MSDC_PAD_TUNE_DATRRDLY,
- final_fall_delay.final_phase);
+ if (host->top_base)
+ sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
+ PAD_DAT_RD_RXDLY,
+ final_fall_delay.final_phase);
+ else
+ sdr_set_field(host->base + tune_reg,
+ MSDC_PAD_TUNE_DATRRDLY,
+ final_fall_delay.final_phase);
final_delay = final_fall_delay.final_phase;
}
@@ -1793,10 +1923,17 @@ static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
sdr_clr_bits(host->base + MSDC_IOCON,
MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
for (i = 0 ; i < PAD_DELAY_MAX; i++) {
- sdr_set_field(host->base + tune_reg,
- MSDC_PAD_TUNE_CMDRDLY, i);
- sdr_set_field(host->base + tune_reg,
- MSDC_PAD_TUNE_DATRRDLY, i);
+ if (host->top_base) {
+ sdr_set_field(host->top_base + EMMC_TOP_CMD,
+ PAD_CMD_RXDLY, i);
+ sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
+ PAD_DAT_RD_RXDLY, i);
+ } else {
+ sdr_set_field(host->base + tune_reg,
+ MSDC_PAD_TUNE_CMDRDLY, i);
+ sdr_set_field(host->base + tune_reg,
+ MSDC_PAD_TUNE_DATRRDLY, i);
+ }
ret = mmc_send_tuning(mmc, opcode, NULL);
if (!ret)
rise_delay |= (1 << i);
@@ -1811,10 +1948,17 @@ static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
sdr_set_bits(host->base + MSDC_IOCON,
MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
for (i = 0; i < PAD_DELAY_MAX; i++) {
- sdr_set_field(host->base + tune_reg,
- MSDC_PAD_TUNE_CMDRDLY, i);
- sdr_set_field(host->base + tune_reg,
- MSDC_PAD_TUNE_DATRRDLY, i);
+ if (host->top_base) {
+ sdr_set_field(host->top_base + EMMC_TOP_CMD,
+ PAD_CMD_RXDLY, i);
+ sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
+ PAD_DAT_RD_RXDLY, i);
+ } else {
+ sdr_set_field(host->base + tune_reg,
+ MSDC_PAD_TUNE_CMDRDLY, i);
+ sdr_set_field(host->base + tune_reg,
+ MSDC_PAD_TUNE_DATRRDLY, i);
+ }
ret = mmc_send_tuning(mmc, opcode, NULL);
if (!ret)
fall_delay |= (1 << i);
@@ -1827,22 +1971,24 @@ static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
sdr_clr_bits(host->base + MSDC_IOCON,
MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
- sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
- final_rise_delay.final_phase);
- sdr_set_field(host->base + tune_reg,
- MSDC_PAD_TUNE_DATRRDLY,
- final_rise_delay.final_phase);
final_delay = final_rise_delay.final_phase;
} else {
sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
sdr_set_bits(host->base + MSDC_IOCON,
MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
+ final_delay = final_fall_delay.final_phase;
+ }
+
+ if (host->top_base) {
+ sdr_set_field(host->top_base + EMMC_TOP_CMD,
+ PAD_CMD_RXDLY, final_delay);
+ sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
+ PAD_DAT_RD_RXDLY, final_delay);
+ } else {
sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
- final_fall_delay.final_phase);
+ final_delay);
sdr_set_field(host->base + tune_reg,
- MSDC_PAD_TUNE_DATRRDLY,
- final_fall_delay.final_phase);
- final_delay = final_fall_delay.final_phase;
+ MSDC_PAD_TUNE_DATRRDLY, final_delay);
}
dev_dbg(host->dev, "Final pad delay: %x\n", final_delay);
@@ -1860,8 +2006,12 @@ static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
if (host->hs400_mode) {
sdr_clr_bits(host->base + MSDC_IOCON,
MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
- sdr_set_field(host->base + tune_reg,
- MSDC_PAD_TUNE_DATRRDLY, 0);
+ if (host->top_base)
+ sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
+ PAD_DAT_RD_RXDLY, 0);
+ else
+ sdr_set_field(host->base + tune_reg,
+ MSDC_PAD_TUNE_DATRRDLY, 0);
}
goto tune_done;
}
@@ -1884,6 +2034,12 @@ static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
+ if (host->top_base) {
+ host->saved_tune_para.emmc_top_control = readl(host->top_base +
+ EMMC_TOP_CONTROL);
+ host->saved_tune_para.emmc_top_cmd = readl(host->top_base +
+ EMMC_TOP_CMD);
+ }
return ret;
}
@@ -1892,7 +2048,11 @@ static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
struct msdc_host *host = mmc_priv(mmc);
host->hs400_mode = true;
- writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
+ if (host->top_base)
+ writel(host->hs400_ds_delay,
+ host->top_base + EMMC50_PAD_DS_TUNE);
+ else
+ writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
/* hs400 mode must set it to 0 */
sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
/* to improve read performance, set outstanding to 2 */
@@ -1975,6 +2135,11 @@ static int msdc_drv_probe(struct platform_device *pdev)
goto host_free;
}
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ host->top_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(host->top_base))
+ host->top_base = NULL;
+
ret = mmc_regulator_get_supply(mmc);
if (ret)
goto host_free;
@@ -2143,7 +2308,6 @@ static void msdc_save_reg(struct msdc_host *host)
host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
host->save_para.iocon = readl(host->base + MSDC_IOCON);
host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
- host->save_para.pad_tune = readl(host->base + tune_reg);
host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
@@ -2152,6 +2316,16 @@ static void msdc_save_reg(struct msdc_host *host)
host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
+ if (host->top_base) {
+ host->save_para.emmc_top_control =
+ readl(host->top_base + EMMC_TOP_CONTROL);
+ host->save_para.emmc_top_cmd =
+ readl(host->top_base + EMMC_TOP_CMD);
+ host->save_para.emmc50_pad_ds_tune =
+ readl(host->top_base + EMMC50_PAD_DS_TUNE);
+ } else {
+ host->save_para.pad_tune = readl(host->base + tune_reg);
+ }
}
static void msdc_restore_reg(struct msdc_host *host)
@@ -2161,7 +2335,6 @@ static void msdc_restore_reg(struct msdc_host *host)
writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
writel(host->save_para.iocon, host->base + MSDC_IOCON);
writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
- writel(host->save_para.pad_tune, host->base + tune_reg);
writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
@@ -2170,6 +2343,16 @@ static void msdc_restore_reg(struct msdc_host *host)
writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
+ if (host->top_base) {
+ writel(host->save_para.emmc_top_control,
+ host->top_base + EMMC_TOP_CONTROL);
+ writel(host->save_para.emmc_top_cmd,
+ host->top_base + EMMC_TOP_CMD);
+ writel(host->save_para.emmc50_pad_ds_tune,
+ host->top_base + EMMC50_PAD_DS_TUNE);
+ } else {
+ writel(host->save_para.pad_tune, host->base + tune_reg);
+ }
}
static int msdc_runtime_suspend(struct device *dev)
--
1.8.1.1.dirty
the tuning code is becoming more and more bloated, let's make the
set cmd/data delay to inline function to avoid too much redundant code.
Signed-off-by: Chaotian Jing <[email protected]>
---
drivers/mmc/host/mtk-sd.c | 133 +++++++++++++---------------------------------
1 file changed, 38 insertions(+), 95 deletions(-)
diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index 5b26f2f..6334cc7 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -1661,6 +1661,30 @@ static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
return delay_phase;
}
+static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
+{
+ u32 tune_reg = host->dev_comp->pad_tune_reg;
+
+ if (host->top_base)
+ sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
+ value);
+ else
+ sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
+ value);
+}
+
+static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
+{
+ u32 tune_reg = host->dev_comp->pad_tune_reg;
+
+ if (host->top_base)
+ sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
+ PAD_DAT_RD_RXDLY, value);
+ else
+ sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY,
+ value);
+}
+
static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
{
struct msdc_host *host = mmc_priv(mmc);
@@ -1681,12 +1705,7 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
for (i = 0 ; i < PAD_DELAY_MAX; i++) {
- if (host->top_base)
- sdr_set_field(host->top_base + EMMC_TOP_CMD,
- PAD_CMD_RXDLY, i);
- else
- sdr_set_field(host->base + tune_reg,
- MSDC_PAD_TUNE_CMDRDLY, i);
+ msdc_set_cmd_delay(host, i);
/*
* Using the same parameters, it may sometimes pass the test,
* but sometimes it may fail. To make sure the parameters are
@@ -1710,12 +1729,7 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
for (i = 0; i < PAD_DELAY_MAX; i++) {
- if (host->top_base)
- sdr_set_field(host->top_base + EMMC_TOP_CMD,
- PAD_CMD_RXDLY, i);
- else
- sdr_set_field(host->base + tune_reg,
- MSDC_PAD_TUNE_CMDRDLY, i);
+ msdc_set_cmd_delay(host, i);
/*
* Using the same parameters, it may sometimes pass the test,
* but sometimes it may fail. To make sure the parameters are
@@ -1739,25 +1753,13 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
final_maxlen = final_fall_delay.maxlen;
if (final_maxlen == final_rise_delay.maxlen) {
sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
- if (host->top_base)
- sdr_set_field(host->base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
- final_rise_delay.final_phase);
- else
- sdr_set_field(host->base + tune_reg,
- MSDC_PAD_TUNE_CMDRDLY,
- final_rise_delay.final_phase);
final_delay = final_rise_delay.final_phase;
} else {
sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
- if (host->top_base)
- sdr_set_field(host->base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
- final_fall_delay.final_phase);
- else
- sdr_set_field(host->base + tune_reg,
- MSDC_PAD_TUNE_CMDRDLY,
- final_fall_delay.final_phase);
final_delay = final_fall_delay.final_phase;
}
+ msdc_set_cmd_delay(host, final_delay);
+
if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
goto skip_internal;
@@ -1832,7 +1834,6 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
u32 rise_delay = 0, fall_delay = 0;
struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
u8 final_delay, final_maxlen;
- u32 tune_reg = host->dev_comp->pad_tune_reg;
int i, ret;
sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
@@ -1840,12 +1841,7 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
for (i = 0 ; i < PAD_DELAY_MAX; i++) {
- if (host->top_base)
- sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
- PAD_DAT_RD_RXDLY, i);
- else
- sdr_set_field(host->base + tune_reg,
- MSDC_PAD_TUNE_DATRRDLY, i);
+ msdc_set_data_delay(host, i);
ret = mmc_send_tuning(mmc, opcode, NULL);
if (!ret)
rise_delay |= (1 << i);
@@ -1859,12 +1855,7 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
for (i = 0; i < PAD_DELAY_MAX; i++) {
- if (host->top_base)
- sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
- PAD_DAT_RD_RXDLY, i);
- else
- sdr_set_field(host->base + tune_reg,
- MSDC_PAD_TUNE_DATRRDLY, i);
+ msdc_set_data_delay(host, i);
ret = mmc_send_tuning(mmc, opcode, NULL);
if (!ret)
fall_delay |= (1 << i);
@@ -1876,28 +1867,13 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
if (final_maxlen == final_rise_delay.maxlen) {
sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
- if (host->top_base)
- sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
- PAD_DAT_RD_RXDLY,
- final_rise_delay.final_phase);
- else
- sdr_set_field(host->base + tune_reg,
- MSDC_PAD_TUNE_DATRRDLY,
- final_rise_delay.final_phase);
final_delay = final_rise_delay.final_phase;
} else {
sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
- if (host->top_base)
- sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
- PAD_DAT_RD_RXDLY,
- final_fall_delay.final_phase);
- else
- sdr_set_field(host->base + tune_reg,
- MSDC_PAD_TUNE_DATRRDLY,
- final_fall_delay.final_phase);
final_delay = final_fall_delay.final_phase;
}
+ msdc_set_data_delay(host, final_delay);
dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay);
return final_delay == 0xff ? -EIO : 0;
@@ -1913,7 +1889,6 @@ static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
u32 rise_delay = 0, fall_delay = 0;
struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
u8 final_delay, final_maxlen;
- u32 tune_reg = host->dev_comp->pad_tune_reg;
int i, ret;
sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
@@ -1923,17 +1898,8 @@ static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
sdr_clr_bits(host->base + MSDC_IOCON,
MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
for (i = 0 ; i < PAD_DELAY_MAX; i++) {
- if (host->top_base) {
- sdr_set_field(host->top_base + EMMC_TOP_CMD,
- PAD_CMD_RXDLY, i);
- sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
- PAD_DAT_RD_RXDLY, i);
- } else {
- sdr_set_field(host->base + tune_reg,
- MSDC_PAD_TUNE_CMDRDLY, i);
- sdr_set_field(host->base + tune_reg,
- MSDC_PAD_TUNE_DATRRDLY, i);
- }
+ msdc_set_cmd_delay(host, i);
+ msdc_set_data_delay(host, i);
ret = mmc_send_tuning(mmc, opcode, NULL);
if (!ret)
rise_delay |= (1 << i);
@@ -1948,17 +1914,8 @@ static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
sdr_set_bits(host->base + MSDC_IOCON,
MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
for (i = 0; i < PAD_DELAY_MAX; i++) {
- if (host->top_base) {
- sdr_set_field(host->top_base + EMMC_TOP_CMD,
- PAD_CMD_RXDLY, i);
- sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
- PAD_DAT_RD_RXDLY, i);
- } else {
- sdr_set_field(host->base + tune_reg,
- MSDC_PAD_TUNE_CMDRDLY, i);
- sdr_set_field(host->base + tune_reg,
- MSDC_PAD_TUNE_DATRRDLY, i);
- }
+ msdc_set_cmd_delay(host, i);
+ msdc_set_data_delay(host, i);
ret = mmc_send_tuning(mmc, opcode, NULL);
if (!ret)
fall_delay |= (1 << i);
@@ -1979,17 +1936,8 @@ static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
final_delay = final_fall_delay.final_phase;
}
- if (host->top_base) {
- sdr_set_field(host->top_base + EMMC_TOP_CMD,
- PAD_CMD_RXDLY, final_delay);
- sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
- PAD_DAT_RD_RXDLY, final_delay);
- } else {
- sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
- final_delay);
- sdr_set_field(host->base + tune_reg,
- MSDC_PAD_TUNE_DATRRDLY, final_delay);
- }
+ msdc_set_cmd_delay(host, final_delay);
+ msdc_set_data_delay(host, final_delay);
dev_dbg(host->dev, "Final pad delay: %x\n", final_delay);
return final_delay == 0xff ? -EIO : 0;
@@ -2006,12 +1954,7 @@ static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
if (host->hs400_mode) {
sdr_clr_bits(host->base + MSDC_IOCON,
MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
- if (host->top_base)
- sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
- PAD_DAT_RD_RXDLY, 0);
- else
- sdr_set_field(host->base + tune_reg,
- MSDC_PAD_TUNE_DATRRDLY, 0);
+ msdc_set_data_delay(host, 0);
}
goto tune_done;
}
--
1.8.1.1.dirty
as the mmc core layer has the mmc->actual_clock, so fill it
and drop msdc_host->sclk.
Signed-off-by: Chaotian Jing <[email protected]>
---
drivers/mmc/host/mtk-sd.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index 1c1c967..ef45f1d 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -391,7 +391,6 @@ struct msdc_host {
struct clk *src_clk_cg; /* msdc source clock control gate */
u32 mclk; /* mmc subsystem clock frequency */
u32 src_clk_freq; /* source clock frequency */
- u32 sclk; /* SD/MS bus clock frequency */
unsigned char timing;
bool vqmmc_enabled;
u32 latch_ck;
@@ -636,10 +635,10 @@ static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
host->timeout_ns = ns;
host->timeout_clks = clks;
- if (host->sclk == 0) {
+ if (host->mmc->actual_clock == 0) {
timeout = 0;
} else {
- clk_ns = 1000000000UL / host->sclk;
+ clk_ns = 1000000000UL / host->mmc->actual_clock;
timeout = (ns + clk_ns - 1) / clk_ns + clks;
/* in 1048576 sclk cycle unit */
timeout = (timeout + (0x1 << 20) - 1) >> 20;
@@ -686,6 +685,7 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
if (!hz) {
dev_dbg(host->dev, "set mclk to 0\n");
host->mclk = 0;
+ host->mmc->actual_clock = 0;
sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
return;
}
@@ -764,7 +764,7 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB))
cpu_relax();
sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
- host->sclk = sclk;
+ host->mmc->actual_clock = sclk;
host->mclk = hz;
host->timing = timing;
/* need because clk changed. */
@@ -775,7 +775,7 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
* mmc_select_hs400() will drop to 50Mhz and High speed mode,
* tune result of hs200/200Mhz is not suitable for 50Mhz
*/
- if (host->sclk <= 52000000) {
+ if (host->mmc->actual_clock <= 52000000) {
writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
writel(host->def_tune_para.pad_tune, host->base + tune_reg);
} else {
@@ -790,7 +790,8 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
sdr_set_field(host->base + PAD_CMD_TUNE,
MSDC_PAD_TUNE_CMDRRDLY,
host->hs400_cmd_int_delay);
- dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->sclk, timing);
+ dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->mmc->actual_clock,
+ timing);
}
static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
--
1.8.1.1.dirty
On 13 October 2018 at 09:20, Chaotian Jing <[email protected]> wrote:
> this series of patch include below changes:
> 1. Add MT8183 SoC support in Mediatek MMC DT bindings
> 2. Fill mmc->actual_clock
> 3. Fix cannot receive new request issue
> 4. Tune CMD/DATA together to save tuning time
> 5. Add MT8183 MMC driver support
> 6. Refine the tuning method to drop too much redundant code
>
> Chaotian Jing (6):
> mmc: dt-bindings: add support for MT8183 SoC
> mmc: mediatek: fill the actual clock for mmc debugfs
> mmc: mediatek: fix cannot receive new request when msdc_cmd_is_ready
> fail
> mmc: mediatek: tune CMD/DATA together
> mmc: mediatek: add MT8183 MMC driver support
> mmc: mediatek: drop too much code of tuning method
>
> Documentation/devicetree/bindings/mmc/mtk-sd.txt | 1 +
> drivers/mmc/host/mtk-sd.c | 292 ++++++++++++++++++++---
> 2 files changed, 254 insertions(+), 39 deletions(-)
>
> --
> 1.8.1.1.dirty
>
Applied for next, thanks!
Kind regards
Uffe
On 13/10/2018 09:20, Chaotian Jing wrote:
> for MSDC IP which supports both data tune and async fifo, it can
> tune cmd/data together. which can save the time and make the tune
> result of CMD more stable as data line are 4bit or 8bit.
>
> Signed-off-by: Chaotian Jing <[email protected]>
> ---
> drivers/mmc/host/mtk-sd.c | 87 +++++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 87 insertions(+)
>
> diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
> index fe80a1d..09d7e44 100644
> --- a/drivers/mmc/host/mtk-sd.c
> +++ b/drivers/mmc/host/mtk-sd.c
> @@ -1773,12 +1773,98 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
> return final_delay == 0xff ? -EIO : 0;
> }
>
> +/*
> + * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
> + * together, which can save the tuning time.
> + */
> +static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
> +{
> + struct msdc_host *host = mmc_priv(mmc);
> + u32 rise_delay = 0, fall_delay = 0;
> + struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
> + u8 final_delay, final_maxlen;
> + u32 tune_reg = host->dev_comp->pad_tune_reg;
> + int i, ret;
> +
> + sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
> + host->latch_ck);
> +
> + sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
> + sdr_clr_bits(host->base + MSDC_IOCON,
> + MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
> + for (i = 0 ; i < PAD_DELAY_MAX; i++) {
> + sdr_set_field(host->base + tune_reg,
> + MSDC_PAD_TUNE_CMDRDLY, i);
> + sdr_set_field(host->base + tune_reg,
> + MSDC_PAD_TUNE_DATRRDLY, i);
> + ret = mmc_send_tuning(mmc, opcode, NULL);
> + if (!ret)
> + rise_delay |= (1 << i);
> + }
> + final_rise_delay = get_best_delay(host, rise_delay);
> + /* if rising edge has enough margin, then do not scan falling edge */
> + if (final_rise_delay.maxlen >= 12 ||
> + (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
> + goto skip_fall;
> +
> + sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
> + sdr_set_bits(host->base + MSDC_IOCON,
> + MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
> + for (i = 0; i < PAD_DELAY_MAX; i++) {
> + sdr_set_field(host->base + tune_reg,
> + MSDC_PAD_TUNE_CMDRDLY, i);
> + sdr_set_field(host->base + tune_reg,
> + MSDC_PAD_TUNE_DATRRDLY, i);
> + ret = mmc_send_tuning(mmc, opcode, NULL);
> + if (!ret)
> + fall_delay |= (1 << i);
> + }
> + final_fall_delay = get_best_delay(host, fall_delay);
> +
> +skip_fall:
> + final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
> + if (final_maxlen == final_rise_delay.maxlen) {
> + sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
> + sdr_clr_bits(host->base + MSDC_IOCON,
> + MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
> + sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
> + final_rise_delay.final_phase);
> + sdr_set_field(host->base + tune_reg,
> + MSDC_PAD_TUNE_DATRRDLY,
> + final_rise_delay.final_phase);
> + final_delay = final_rise_delay.final_phase;
> + } else {
> + sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
> + sdr_set_bits(host->base + MSDC_IOCON,
> + MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
> + sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
> + final_fall_delay.final_phase);
> + sdr_set_field(host->base + tune_reg,
> + MSDC_PAD_TUNE_DATRRDLY,
> + final_fall_delay.final_phase);
> + final_delay = final_fall_delay.final_phase;
> + }
> +
> + dev_dbg(host->dev, "Final pad delay: %x\n", final_delay);
> + return final_delay == 0xff ? -EIO : 0;
> +}
> +
> static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
> {
> struct msdc_host *host = mmc_priv(mmc);
> int ret;
> u32 tune_reg = host->dev_comp->pad_tune_reg;
>
> + if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
> + ret = msdc_tune_together(mmc, opcode);
> + if (host->hs400_mode) {
> + sdr_clr_bits(host->base + MSDC_IOCON,
> + MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
> + sdr_set_field(host->base + tune_reg,
> + MSDC_PAD_TUNE_DATRRDLY, 0);
> + }
> + goto tune_done;
> + }
> if (host->hs400_mode &&
Couldn't we put a else if here instead of using a goto?
Regards,
Matthias
> host->dev_comp->hs400_tune)
> ret = hs400_tune_response(mmc, opcode);
> @@ -1794,6 +1880,7 @@ static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
> dev_err(host->dev, "Tune data fail!\n");
> }
>
> +tune_done:
> host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
> host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
> host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
>
On 13/10/2018 09:20, Chaotian Jing wrote:
> the tuning code is becoming more and more bloated, let's make the
> set cmd/data delay to inline function to avoid too much redundant code.
>
> Signed-off-by: Chaotian Jing <[email protected]>
> ---
> drivers/mmc/host/mtk-sd.c | 133 +++++++++++++---------------------------------
> 1 file changed, 38 insertions(+), 95 deletions(-)
>
> diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
[...]> @@ -1923,17 +1898,8 @@ static int msdc_tune_together(struct mmc_host
*mmc, u32 opcode)
> sdr_clr_bits(host->base + MSDC_IOCON,
> MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
> for (i = 0 ; i < PAD_DELAY_MAX; i++) {
> - if (host->top_base) {
> - sdr_set_field(host->top_base + EMMC_TOP_CMD,
> - PAD_CMD_RXDLY, i);
> - sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
> - PAD_DAT_RD_RXDLY, i);
> - } else {
> - sdr_set_field(host->base + tune_reg,
> - MSDC_PAD_TUNE_CMDRDLY, i);
> - sdr_set_field(host->base + tune_reg,
> - MSDC_PAD_TUNE_DATRRDLY, i);
> - }
> + msdc_set_cmd_delay(host, i);
> + msdc_set_data_delay(host, i);
Put the clean-up before introducing msdc_tune_together, that makes the series
much easier to read.
Thanks,
Matthias
On 13/10/2018 09:20, Chaotian Jing wrote:
> MT8183 puts the tune register at top layer, so need add new code
> to support it.
>
> Signed-off-by: Chaotian Jing <[email protected]>
> ---
> drivers/mmc/host/mtk-sd.c | 283 ++++++++++++++++++++++++++++++++++++++--------
> 1 file changed, 233 insertions(+), 50 deletions(-)
>
> diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
> index 09d7e44..5b26f2f 100644
> --- a/drivers/mmc/host/mtk-sd.c
> +++ b/drivers/mmc/host/mtk-sd.c
> @@ -87,6 +87,13 @@
> #define SDC_FIFO_CFG 0x228
>
> /*--------------------------------------------------------------------------*/
> +/* Top Pad Register Offset */
> +/*--------------------------------------------------------------------------*/
> +#define EMMC_TOP_CONTROL 0x00
> +#define EMMC_TOP_CMD 0x04
> +#define EMMC50_PAD_DS_TUNE 0x0c
> +
> +/*--------------------------------------------------------------------------*/
> /* Register Mask */
> /*--------------------------------------------------------------------------*/
>
> @@ -261,6 +268,23 @@
> #define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */
> #define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */
>
> +/* EMMC_TOP_CONTROL mask */
> +#define PAD_RXDLY_SEL (0x1 << 0) /* RW */
> +#define DELAY_EN (0x1 << 1) /* RW */
> +#define PAD_DAT_RD_RXDLY2 (0x1f << 2) /* RW */
> +#define PAD_DAT_RD_RXDLY (0x1f << 7) /* RW */
> +#define PAD_DAT_RD_RXDLY2_SEL (0x1 << 12) /* RW */
> +#define PAD_DAT_RD_RXDLY_SEL (0x1 << 13) /* RW */
> +#define DATA_K_VALUE_SEL (0x1 << 14) /* RW */
> +#define SDC_RX_ENH_EN (0x1 << 15) /* TW */
> +
> +/* EMMC_TOP_CMD mask */
> +#define PAD_CMD_RXDLY2 (0x1f << 0) /* RW */
> +#define PAD_CMD_RXDLY (0x1f << 5) /* RW */
> +#define PAD_CMD_RD_RXDLY2_SEL (0x1 << 10) /* RW */
> +#define PAD_CMD_RD_RXDLY_SEL (0x1 << 11) /* RW */
> +#define PAD_CMD_TX_DLY (0x1f << 12) /* RW */
> +
> #define REQ_CMD_EIO (0x1 << 0)
> #define REQ_CMD_TMO (0x1 << 1)
> #define REQ_DAT_ERR (0x1 << 2)
> @@ -333,6 +357,9 @@ struct msdc_save_para {
> u32 emmc50_cfg0;
> u32 emmc50_cfg3;
> u32 sdc_fifo_cfg;
> + u32 emmc_top_control;
> + u32 emmc_top_cmd;
> + u32 emmc50_pad_ds_tune;
> };
>
> struct mtk_mmc_compatible {
> @@ -351,6 +378,8 @@ struct msdc_tune_para {
> u32 iocon;
> u32 pad_tune;
> u32 pad_cmd_tune;
> + u32 emmc_top_control;
> + u32 emmc_top_cmd;
> };
>
> struct msdc_delay_phase {
> @@ -372,6 +401,7 @@ struct msdc_host {
> int error;
>
> void __iomem *base; /* host base address */
> + void __iomem *top_base; /* host top register base address */
Where do you assign a value to top_base?
I'm not familiar with the driver, but couldn't we reuse base and a flag for
example in mtk_mmc_compatible to check which tune register we need to use?
Regards,
Matthias
>
> struct msdc_dma dma; /* dma channel */
> u64 dma_mask;
> @@ -429,6 +459,18 @@ struct msdc_host {
> .support_64g = false,
> };
>
> +static const struct mtk_mmc_compatible mt8183_compat = {
> + .clk_div_bits = 12,
> + .hs400_tune = false,
> + .pad_tune_reg = MSDC_PAD_TUNE0,
> + .async_fifo = true,
> + .data_tune = true,
> + .busy_check = true,
> + .stop_clk_fix = true,
> + .enhance_rx = true,
> + .support_64g = true,
> +};
> +
> static const struct mtk_mmc_compatible mt2701_compat = {
> .clk_div_bits = 12,
> .hs400_tune = false,
> @@ -468,6 +510,7 @@ struct msdc_host {
> static const struct of_device_id msdc_of_ids[] = {
> { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
> { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
> + { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
> { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
> { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
> { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
> @@ -777,12 +820,28 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
> */
> if (host->mmc->actual_clock <= 52000000) {
> writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
> - writel(host->def_tune_para.pad_tune, host->base + tune_reg);
> + if (host->top_base) {
> + writel(host->def_tune_para.emmc_top_control,
> + host->top_base + EMMC_TOP_CONTROL);
> + writel(host->def_tune_para.emmc_top_cmd,
> + host->top_base + EMMC_TOP_CMD);
> + } else {
> + writel(host->def_tune_para.pad_tune,
> + host->base + tune_reg);
> + }
> } else {
> writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
> - writel(host->saved_tune_para.pad_tune, host->base + tune_reg);
> writel(host->saved_tune_para.pad_cmd_tune,
> host->base + PAD_CMD_TUNE);
> + if (host->top_base) {
> + writel(host->saved_tune_para.emmc_top_control,
> + host->top_base + EMMC_TOP_CONTROL);
> + writel(host->saved_tune_para.emmc_top_cmd,
> + host->top_base + EMMC_TOP_CMD);
> + } else {
> + writel(host->saved_tune_para.pad_tune,
> + host->base + tune_reg);
> + }
> }
>
> if (timing == MMC_TIMING_MMC_HS400 &&
> @@ -1355,7 +1414,12 @@ static void msdc_init_hw(struct msdc_host *host)
> val = readl(host->base + MSDC_INT);
> writel(val, host->base + MSDC_INT);
>
> - writel(0, host->base + tune_reg);
> + if (host->top_base) {
> + writel(0, host->top_base + EMMC_TOP_CONTROL);
> + writel(0, host->top_base + EMMC_TOP_CMD);
> + } else {
> + writel(0, host->base + tune_reg);
> + }
> writel(0, host->base + MSDC_IOCON);
> sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
> writel(0x403c0046, host->base + MSDC_PATCH_BIT);
> @@ -1379,8 +1443,12 @@ static void msdc_init_hw(struct msdc_host *host)
> sdr_set_field(host->base + MSDC_PATCH_BIT2,
> MSDC_PB2_RESPWAIT, 3);
> if (host->dev_comp->enhance_rx) {
> - sdr_set_bits(host->base + SDC_ADV_CFG0,
> - SDC_RX_ENHANCE_EN);
> + if (host->top_base)
> + sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
> + SDC_RX_ENH_EN);
> + else
> + sdr_set_bits(host->base + SDC_ADV_CFG0,
> + SDC_RX_ENHANCE_EN);
> } else {
> sdr_set_field(host->base + MSDC_PATCH_BIT2,
> MSDC_PB2_RESPSTSENSEL, 2);
> @@ -1398,11 +1466,26 @@ static void msdc_init_hw(struct msdc_host *host)
> sdr_set_bits(host->base + MSDC_PATCH_BIT2,
> MSDC_PB2_SUPPORT_64G);
> if (host->dev_comp->data_tune) {
> - sdr_set_bits(host->base + tune_reg,
> - MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL);
> + if (host->top_base) {
> + sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
> + PAD_DAT_RD_RXDLY_SEL);
> + sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL,
> + DATA_K_VALUE_SEL);
> + sdr_set_bits(host->top_base + EMMC_TOP_CMD,
> + PAD_CMD_RD_RXDLY_SEL);
> + } else {
> + sdr_set_bits(host->base + tune_reg,
> + MSDC_PAD_TUNE_RD_SEL |
> + MSDC_PAD_TUNE_CMD_SEL);
> + }
> } else {
> /* choose clock tune */
> - sdr_set_bits(host->base + tune_reg, MSDC_PAD_TUNE_RXDLYSEL);
> + if (host->top_base)
> + sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
> + PAD_RXDLY_SEL);
> + else
> + sdr_set_bits(host->base + tune_reg,
> + MSDC_PAD_TUNE_RXDLYSEL);
> }
>
> /* Configure to enable SDIO mode.
> @@ -1417,9 +1500,20 @@ static void msdc_init_hw(struct msdc_host *host)
> sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
>
> host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
> - host->def_tune_para.pad_tune = readl(host->base + tune_reg);
> host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
> - host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
> + if (host->top_base) {
> + host->def_tune_para.emmc_top_control =
> + readl(host->top_base + EMMC_TOP_CONTROL);
> + host->def_tune_para.emmc_top_cmd =
> + readl(host->top_base + EMMC_TOP_CMD);
> + host->saved_tune_para.emmc_top_control =
> + readl(host->top_base + EMMC_TOP_CONTROL);
> + host->saved_tune_para.emmc_top_cmd =
> + readl(host->top_base + EMMC_TOP_CMD);
> + } else {
> + host->def_tune_para.pad_tune = readl(host->base + tune_reg);
> + host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
> + }
> dev_dbg(host->dev, "init hardware done!");
> }
>
> @@ -1587,8 +1681,12 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
>
> sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
> for (i = 0 ; i < PAD_DELAY_MAX; i++) {
> - sdr_set_field(host->base + tune_reg,
> - MSDC_PAD_TUNE_CMDRDLY, i);
> + if (host->top_base)
> + sdr_set_field(host->top_base + EMMC_TOP_CMD,
> + PAD_CMD_RXDLY, i);
> + else
> + sdr_set_field(host->base + tune_reg,
> + MSDC_PAD_TUNE_CMDRDLY, i);
> /*
> * Using the same parameters, it may sometimes pass the test,
> * but sometimes it may fail. To make sure the parameters are
> @@ -1612,8 +1710,12 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
>
> sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
> for (i = 0; i < PAD_DELAY_MAX; i++) {
> - sdr_set_field(host->base + tune_reg,
> - MSDC_PAD_TUNE_CMDRDLY, i);
> + if (host->top_base)
> + sdr_set_field(host->top_base + EMMC_TOP_CMD,
> + PAD_CMD_RXDLY, i);
> + else
> + sdr_set_field(host->base + tune_reg,
> + MSDC_PAD_TUNE_CMDRDLY, i);
> /*
> * Using the same parameters, it may sometimes pass the test,
> * but sometimes it may fail. To make sure the parameters are
> @@ -1637,13 +1739,23 @@ static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
> final_maxlen = final_fall_delay.maxlen;
> if (final_maxlen == final_rise_delay.maxlen) {
> sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
> - sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
> - final_rise_delay.final_phase);
> + if (host->top_base)
> + sdr_set_field(host->base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
> + final_rise_delay.final_phase);
> + else
> + sdr_set_field(host->base + tune_reg,
> + MSDC_PAD_TUNE_CMDRDLY,
> + final_rise_delay.final_phase);
> final_delay = final_rise_delay.final_phase;
> } else {
> sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
> - sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
> - final_fall_delay.final_phase);
> + if (host->top_base)
> + sdr_set_field(host->base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
> + final_fall_delay.final_phase);
> + else
> + sdr_set_field(host->base + tune_reg,
> + MSDC_PAD_TUNE_CMDRDLY,
> + final_fall_delay.final_phase);
> final_delay = final_fall_delay.final_phase;
> }
> if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
> @@ -1728,8 +1840,12 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
> sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
> sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
> for (i = 0 ; i < PAD_DELAY_MAX; i++) {
> - sdr_set_field(host->base + tune_reg,
> - MSDC_PAD_TUNE_DATRRDLY, i);
> + if (host->top_base)
> + sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
> + PAD_DAT_RD_RXDLY, i);
> + else
> + sdr_set_field(host->base + tune_reg,
> + MSDC_PAD_TUNE_DATRRDLY, i);
> ret = mmc_send_tuning(mmc, opcode, NULL);
> if (!ret)
> rise_delay |= (1 << i);
> @@ -1743,8 +1859,12 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
> sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
> sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
> for (i = 0; i < PAD_DELAY_MAX; i++) {
> - sdr_set_field(host->base + tune_reg,
> - MSDC_PAD_TUNE_DATRRDLY, i);
> + if (host->top_base)
> + sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
> + PAD_DAT_RD_RXDLY, i);
> + else
> + sdr_set_field(host->base + tune_reg,
> + MSDC_PAD_TUNE_DATRRDLY, i);
> ret = mmc_send_tuning(mmc, opcode, NULL);
> if (!ret)
> fall_delay |= (1 << i);
> @@ -1756,16 +1876,26 @@ static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
> if (final_maxlen == final_rise_delay.maxlen) {
> sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
> sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
> - sdr_set_field(host->base + tune_reg,
> - MSDC_PAD_TUNE_DATRRDLY,
> - final_rise_delay.final_phase);
> + if (host->top_base)
> + sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
> + PAD_DAT_RD_RXDLY,
> + final_rise_delay.final_phase);
> + else
> + sdr_set_field(host->base + tune_reg,
> + MSDC_PAD_TUNE_DATRRDLY,
> + final_rise_delay.final_phase);
> final_delay = final_rise_delay.final_phase;
> } else {
> sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
> sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
> - sdr_set_field(host->base + tune_reg,
> - MSDC_PAD_TUNE_DATRRDLY,
> - final_fall_delay.final_phase);
> + if (host->top_base)
> + sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
> + PAD_DAT_RD_RXDLY,
> + final_fall_delay.final_phase);
> + else
> + sdr_set_field(host->base + tune_reg,
> + MSDC_PAD_TUNE_DATRRDLY,
> + final_fall_delay.final_phase);
> final_delay = final_fall_delay.final_phase;
> }
>
> @@ -1793,10 +1923,17 @@ static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
> sdr_clr_bits(host->base + MSDC_IOCON,
> MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
> for (i = 0 ; i < PAD_DELAY_MAX; i++) {
> - sdr_set_field(host->base + tune_reg,
> - MSDC_PAD_TUNE_CMDRDLY, i);
> - sdr_set_field(host->base + tune_reg,
> - MSDC_PAD_TUNE_DATRRDLY, i);
> + if (host->top_base) {
> + sdr_set_field(host->top_base + EMMC_TOP_CMD,
> + PAD_CMD_RXDLY, i);
> + sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
> + PAD_DAT_RD_RXDLY, i);
> + } else {
> + sdr_set_field(host->base + tune_reg,
> + MSDC_PAD_TUNE_CMDRDLY, i);
> + sdr_set_field(host->base + tune_reg,
> + MSDC_PAD_TUNE_DATRRDLY, i);
> + }
> ret = mmc_send_tuning(mmc, opcode, NULL);
> if (!ret)
> rise_delay |= (1 << i);
> @@ -1811,10 +1948,17 @@ static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
> sdr_set_bits(host->base + MSDC_IOCON,
> MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
> for (i = 0; i < PAD_DELAY_MAX; i++) {
> - sdr_set_field(host->base + tune_reg,
> - MSDC_PAD_TUNE_CMDRDLY, i);
> - sdr_set_field(host->base + tune_reg,
> - MSDC_PAD_TUNE_DATRRDLY, i);
> + if (host->top_base) {
> + sdr_set_field(host->top_base + EMMC_TOP_CMD,
> + PAD_CMD_RXDLY, i);
> + sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
> + PAD_DAT_RD_RXDLY, i);
> + } else {
> + sdr_set_field(host->base + tune_reg,
> + MSDC_PAD_TUNE_CMDRDLY, i);
> + sdr_set_field(host->base + tune_reg,
> + MSDC_PAD_TUNE_DATRRDLY, i);
> + }
> ret = mmc_send_tuning(mmc, opcode, NULL);
> if (!ret)
> fall_delay |= (1 << i);
> @@ -1827,22 +1971,24 @@ static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
> sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
> sdr_clr_bits(host->base + MSDC_IOCON,
> MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
> - sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
> - final_rise_delay.final_phase);
> - sdr_set_field(host->base + tune_reg,
> - MSDC_PAD_TUNE_DATRRDLY,
> - final_rise_delay.final_phase);
> final_delay = final_rise_delay.final_phase;
> } else {
> sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
> sdr_set_bits(host->base + MSDC_IOCON,
> MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
> + final_delay = final_fall_delay.final_phase;
> + }
> +
> + if (host->top_base) {
> + sdr_set_field(host->top_base + EMMC_TOP_CMD,
> + PAD_CMD_RXDLY, final_delay);
> + sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
> + PAD_DAT_RD_RXDLY, final_delay);
> + } else {
> sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
> - final_fall_delay.final_phase);
> + final_delay);
> sdr_set_field(host->base + tune_reg,
> - MSDC_PAD_TUNE_DATRRDLY,
> - final_fall_delay.final_phase);
> - final_delay = final_fall_delay.final_phase;
> + MSDC_PAD_TUNE_DATRRDLY, final_delay);
> }
>
> dev_dbg(host->dev, "Final pad delay: %x\n", final_delay);
> @@ -1860,8 +2006,12 @@ static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
> if (host->hs400_mode) {
> sdr_clr_bits(host->base + MSDC_IOCON,
> MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
> - sdr_set_field(host->base + tune_reg,
> - MSDC_PAD_TUNE_DATRRDLY, 0);
> + if (host->top_base)
> + sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
> + PAD_DAT_RD_RXDLY, 0);
> + else
> + sdr_set_field(host->base + tune_reg,
> + MSDC_PAD_TUNE_DATRRDLY, 0);
> }
> goto tune_done;
> }
> @@ -1884,6 +2034,12 @@ static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
> host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
> host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
> host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
> + if (host->top_base) {
> + host->saved_tune_para.emmc_top_control = readl(host->top_base +
> + EMMC_TOP_CONTROL);
> + host->saved_tune_para.emmc_top_cmd = readl(host->top_base +
> + EMMC_TOP_CMD);
> + }
> return ret;
> }
>
> @@ -1892,7 +2048,11 @@ static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
> struct msdc_host *host = mmc_priv(mmc);
> host->hs400_mode = true;
>
> - writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
> + if (host->top_base)
> + writel(host->hs400_ds_delay,
> + host->top_base + EMMC50_PAD_DS_TUNE);
> + else
> + writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
> /* hs400 mode must set it to 0 */
> sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
> /* to improve read performance, set outstanding to 2 */
> @@ -1975,6 +2135,11 @@ static int msdc_drv_probe(struct platform_device *pdev)
> goto host_free;
> }
>
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> + host->top_base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(host->top_base))
> + host->top_base = NULL;
> +
> ret = mmc_regulator_get_supply(mmc);
> if (ret)
> goto host_free;
> @@ -2143,7 +2308,6 @@ static void msdc_save_reg(struct msdc_host *host)
> host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
> host->save_para.iocon = readl(host->base + MSDC_IOCON);
> host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
> - host->save_para.pad_tune = readl(host->base + tune_reg);
> host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
> host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
> host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
> @@ -2152,6 +2316,16 @@ static void msdc_save_reg(struct msdc_host *host)
> host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
> host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
> host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
> + if (host->top_base) {
> + host->save_para.emmc_top_control =
> + readl(host->top_base + EMMC_TOP_CONTROL);
> + host->save_para.emmc_top_cmd =
> + readl(host->top_base + EMMC_TOP_CMD);
> + host->save_para.emmc50_pad_ds_tune =
> + readl(host->top_base + EMMC50_PAD_DS_TUNE);
> + } else {
> + host->save_para.pad_tune = readl(host->base + tune_reg);
> + }
> }
>
> static void msdc_restore_reg(struct msdc_host *host)
> @@ -2161,7 +2335,6 @@ static void msdc_restore_reg(struct msdc_host *host)
> writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
> writel(host->save_para.iocon, host->base + MSDC_IOCON);
> writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
> - writel(host->save_para.pad_tune, host->base + tune_reg);
> writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
> writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
> writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
> @@ -2170,6 +2343,16 @@ static void msdc_restore_reg(struct msdc_host *host)
> writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
> writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
> writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
> + if (host->top_base) {
> + writel(host->save_para.emmc_top_control,
> + host->top_base + EMMC_TOP_CONTROL);
> + writel(host->save_para.emmc_top_cmd,
> + host->top_base + EMMC_TOP_CMD);
> + writel(host->save_para.emmc50_pad_ds_tune,
> + host->top_base + EMMC50_PAD_DS_TUNE);
> + } else {
> + writel(host->save_para.pad_tune, host->base + tune_reg);
> + }
> }
>
> static int msdc_runtime_suspend(struct device *dev)
>