From: Matthias Brugger <[email protected]>
Jasper send this series some month ago. As there was no reaction from
his side, I'll do a friendly take-over.
I tested the patches on my Helios X20 boards and they fix the issue.
I didn't add a Tested-by tag as I added my Signed-off-by.
Changes since v1:
- add a fixes tag.
---
Currently, DRAM-related clocks and the axi_sel MUX are not marked with
CLK_IS_CRITICAL for MT6797. This causes memory corruption when the
system is booted without clk_ignore_unused.
This patchset
1. Makes it possible to mark outputs of MUXes as critical by introducing
a new macro, MUX_FLAGS,
2. Makes it possible to mark gates as critical by adding flags to
mtk_gate, and
3. Marks axi_sel, ddrphycfg_sel, infra_dramc_f26m and infra_dramc_b_f26m
as critical.
The addition of flags to mtk_gate also exists in the patch series "Add
basic and clock support for Mediatek MT8183 SoC" [1]. The type of
flags is unsigned int in that series, but the real type is unsigned
long, so my patch differs from that patch.
[1] https://patchwork.kernel.org/patch/10549953/
Jasper Mattsson (3):
clk: mediatek: Add MUX_FLAGS macro
clk: mediatek: Add flags to mtk_gate
clk: mediatek: Mark bus and DRAM related clocks as critical
drivers/clk/mediatek/clk-gate.c | 4 +-
drivers/clk/mediatek/clk-gate.h | 3 +-
drivers/clk/mediatek/clk-mt6797.c | 64 ++++++++++++++++++-------------
drivers/clk/mediatek/clk-mtk.c | 2 +-
drivers/clk/mediatek/clk-mtk.h | 9 ++++-
5 files changed, 50 insertions(+), 32 deletions(-)
--
2.19.1
From: Jasper Mattsson <[email protected]>
This is required to mark outputs of certain MUXes as CLK_IS_CRITICAL.
Fixes: 96596aa06628 ("clk: mediatek: add clk support for MT6797")
Signed-off-by: Jasper Mattsson <[email protected]>
Signed-off-by: Matthias Brugger <[email protected]>
---
drivers/clk/mediatek/clk-mtk.h | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index f83c2bbb677e..daab6ee94788 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -111,7 +111,11 @@ struct mtk_composite {
MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
_gate, CLK_SET_RATE_PARENT)
-#define MUX(_id, _name, _parents, _reg, _shift, _width) { \
+#define MUX(_id, _name, _parents, _reg, _shift, _width) \
+ MUX_FLAGS(_id, _name, _parents, _reg, \
+ _shift, _width, CLK_SET_RATE_PARENT)
+
+#define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \
.id = _id, \
.name = _name, \
.mux_reg = _reg, \
@@ -121,7 +125,7 @@ struct mtk_composite {
.divider_shift = -1, \
.parent_names = _parents, \
.num_parents = ARRAY_SIZE(_parents), \
- .flags = CLK_SET_RATE_PARENT, \
+ .flags = _flags, \
}
#define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \
--
2.19.1
From: Jasper Mattsson <[email protected]>
This is required to mark gates as CLK_IS_CRITICAL.
Fixes: 96596aa06628 ("clk: mediatek: add clk support for MT6797")
Signed-off-by: Jasper Mattsson <[email protected]>
Signed-off-by: Matthias Brugger <[email protected]>
---
drivers/clk/mediatek/clk-gate.c | 4 +++-
drivers/clk/mediatek/clk-gate.h | 3 ++-
drivers/clk/mediatek/clk-mtk.c | 2 +-
drivers/clk/mediatek/clk-mtk.h | 1 +
4 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
index 934bf0e45e26..9628d4e7690b 100644
--- a/drivers/clk/mediatek/clk-gate.c
+++ b/drivers/clk/mediatek/clk-gate.c
@@ -157,7 +157,8 @@ struct clk *mtk_clk_register_gate(
int clr_ofs,
int sta_ofs,
u8 bit,
- const struct clk_ops *ops)
+ const struct clk_ops *ops,
+ unsigned long flags)
{
struct mtk_clk_gate *cg;
struct clk *clk;
@@ -172,6 +173,7 @@ struct clk *mtk_clk_register_gate(
init.parent_names = parent_name ? &parent_name : NULL;
init.num_parents = parent_name ? 1 : 0;
init.ops = ops;
+ init.flags = flags;
cg->regmap = regmap;
cg->set_ofs = set_ofs;
diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h
index 72ef89b3ad7b..9f766dfe1d57 100644
--- a/drivers/clk/mediatek/clk-gate.h
+++ b/drivers/clk/mediatek/clk-gate.h
@@ -47,6 +47,7 @@ struct clk *mtk_clk_register_gate(
int clr_ofs,
int sta_ofs,
u8 bit,
- const struct clk_ops *ops);
+ const struct clk_ops *ops,
+ unsigned long flags);
#endif /* __DRV_CLK_GATE_H */
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 9c0ae4278a94..ef410413bb0b 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -130,7 +130,7 @@ int mtk_clk_register_gates(struct device_node *node,
gate->regs->set_ofs,
gate->regs->clr_ofs,
gate->regs->sta_ofs,
- gate->shift, gate->ops);
+ gate->shift, gate->ops, gate->flags);
if (IS_ERR(clk)) {
pr_err("Failed to register clk %s: %ld\n",
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index daab6ee94788..987ff2855249 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -162,6 +162,7 @@ struct mtk_gate {
const struct mtk_gate_regs *regs;
int shift;
const struct clk_ops *ops;
+ unsigned long flags;
};
int mtk_clk_register_gates(struct device_node *node,
--
2.19.1
From: Jasper Mattsson <[email protected]>
This marks MUXes axi_sel and ddrphycfg_sel as well as gates
infra_dramc_f26m and infra_dramc_b_f26m as with CLK_IS_CRITICAL.
Fixes: 96596aa06628 ("clk: mediatek: add clk support for MT6797")
Signed-off-by: Jasper Mattsson <[email protected]>
Signed-off-by: Matthias Brugger <[email protected]>
---
drivers/clk/mediatek/clk-mt6797.c | 64 ++++++++++++++++++-------------
1 file changed, 37 insertions(+), 27 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-mt6797.c
index 5702bc974ed9..20b106764423 100644
--- a/drivers/clk/mediatek/clk-mt6797.c
+++ b/drivers/clk/mediatek/clk-mt6797.c
@@ -329,10 +329,10 @@ static const struct mtk_composite top_muxes[] = {
ulposc_axi_ck_mux_pre_parents, 0x0040, 3, 1),
MUX(CLK_TOP_MUX_ULPOSC_AXI_CK_MUX, "ulposc_axi_ck_mux",
ulposc_axi_ck_mux_parents, 0x0040, 2, 1),
- MUX(CLK_TOP_MUX_AXI, "axi_sel", axi_parents,
- 0x0040, 0, 2),
- MUX(CLK_TOP_MUX_DDRPHYCFG, "ddrphycfg_sel", ddrphycfg_parents,
- 0x0040, 16, 2),
+ MUX_FLAGS(CLK_TOP_MUX_AXI, "axi_sel", axi_parents,
+ 0x0040, 0, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
+ MUX_FLAGS(CLK_TOP_MUX_DDRPHYCFG, "ddrphycfg_sel", ddrphycfg_parents,
+ 0x0040, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
MUX(CLK_TOP_MUX_MM, "mm_sel", mm_parents,
0x0040, 24, 2),
MUX_GATE(CLK_TOP_MUX_PWM, "pwm_sel", pwm_parents, 0x0050, 0, 3, 7),
@@ -424,31 +424,39 @@ static const struct mtk_gate_regs infra2_cg_regs = {
.sta_ofs = 0x00b0,
};
-#define GATE_ICG0(_id, _name, _parent, _shift) { \
- .id = _id, \
- .name = _name, \
- .parent_name = _parent, \
- .regs = &infra0_cg_regs, \
- .shift = _shift, \
- .ops = &mtk_clk_gate_ops_setclr, \
+#define GATE_ICG0(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &infra0_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
}
-#define GATE_ICG1(_id, _name, _parent, _shift) { \
- .id = _id, \
- .name = _name, \
- .parent_name = _parent, \
- .regs = &infra1_cg_regs, \
- .shift = _shift, \
- .ops = &mtk_clk_gate_ops_setclr, \
+#define GATE_ICG1(_id, _name, _parent, _shift) \
+ GATE_ICG1_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_ICG1_FLAGS(_id, _name, _parent, _shift, _flags) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &infra1_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ .flags = _flags, \
}
-#define GATE_ICG2(_id, _name, _parent, _shift) { \
- .id = _id, \
- .name = _name, \
- .parent_name = _parent, \
- .regs = &infra2_cg_regs, \
- .shift = _shift, \
- .ops = &mtk_clk_gate_ops_setclr, \
+#define GATE_ICG2(_id, _name, _parent, _shift) \
+ GATE_ICG2_FLAGS(_id, _name, _parent, _shift, 0)
+
+#define GATE_ICG2_FLAGS(_id, _name, _parent, _shift, _flags) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &infra2_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_setclr, \
+ .flags = _flags, \
}
static const struct mtk_gate infra_clks[] = {
@@ -505,7 +513,8 @@ static const struct mtk_gate infra_clks[] = {
GATE_ICG1(CLK_INFRA_CCIF_AP, "infra_ccif_ap", "axi_sel", 23),
GATE_ICG1(CLK_INFRA_AUDIO, "infra_audio", "axi_sel", 25),
GATE_ICG1(CLK_INFRA_CCIF_MD, "infra_ccif_md", "axi_sel", 26),
- GATE_ICG1(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m", "clk26m", 31),
+ GATE_ICG1_FLAGS(CLK_INFRA_DRAMC_F26M, "infra_dramc_f26m",
+ "clk26m", 31, CLK_IS_CRITICAL),
GATE_ICG2(CLK_INFRA_I2C4, "infra_i2c4", "axi_sel", 0),
GATE_ICG2(CLK_INFRA_I2C_APPM, "infra_i2c_appm", "axi_sel", 1),
GATE_ICG2(CLK_INFRA_I2C_GPUPM, "infra_i2c_gpupm", "axi_sel", 2),
@@ -516,7 +525,8 @@ static const struct mtk_gate infra_clks[] = {
GATE_ICG2(CLK_INFRA_I2C5, "infra_i2c5", "axi_sel", 7),
GATE_ICG2(CLK_INFRA_SYS_CIRQ, "infra_sys_cirq", "axi_sel", 8),
GATE_ICG2(CLK_INFRA_SPI1, "infra_spi1", "spi_sel", 10),
- GATE_ICG2(CLK_INFRA_DRAMC_B_F26M, "infra_dramc_b_f26m", "clk26m", 11),
+ GATE_ICG2_FLAGS(CLK_INFRA_DRAMC_B_F26M, "infra_dramc_b_f26m",
+ "clk26m", 11, CLK_IS_CRITICAL),
GATE_ICG2(CLK_INFRA_ANC_MD32, "infra_anc_md32", "anc_md32_sel", 12),
GATE_ICG2(CLK_INFRA_ANC_MD32_32K, "infra_anc_md32_32k", "clk26m", 13),
GATE_ICG2(CLK_INFRA_DVFS_SPM1, "infra_dvfs_spm1", "axi_sel", 15),
--
2.19.1
Quoting [email protected] (2018-11-16 10:08:58)
> From: Matthias Brugger <[email protected]>
>
> Jasper send this series some month ago. As there was no reaction from
> his side, I'll do a friendly take-over.
> I tested the patches on my Helios X20 boards and they fix the issue.
> I didn't add a Tested-by tag as I added my Signed-off-by.
>
> Changes since v1:
> - add a fixes tag.
>
> ---
>
> Currently, DRAM-related clocks and the axi_sel MUX are not marked with
> CLK_IS_CRITICAL for MT6797. This causes memory corruption when the
> system is booted without clk_ignore_unused.
>
> This patchset
>
> 1. Makes it possible to mark outputs of MUXes as critical by introducing
> a new macro, MUX_FLAGS,
> 2. Makes it possible to mark gates as critical by adding flags to
> mtk_gate, and
> 3. Marks axi_sel, ddrphycfg_sel, infra_dramc_f26m and infra_dramc_b_f26m
> as critical.
>
> The addition of flags to mtk_gate also exists in the patch series "Add
> basic and clock support for Mediatek MT8183 SoC" [1]. The type of
> flags is unsigned int in that series, but the real type is unsigned
> long, so my patch differs from that patch.
Will anyone from Mediatek review this? Why aren't the people who signed
off on drivers/clk/mediatek/clk-mt6797.c included on this patch series?
They no longer work there?
Quoting [email protected] (2018-11-16 10:09:01)
> From: Jasper Mattsson <[email protected]>
>
> This marks MUXes axi_sel and ddrphycfg_sel as well as gates
> infra_dramc_f26m and infra_dramc_b_f26m as with CLK_IS_CRITICAL.
>
> Fixes: 96596aa06628 ("clk: mediatek: add clk support for MT6797")
> Signed-off-by: Jasper Mattsson <[email protected]>
> Signed-off-by: Matthias Brugger <[email protected]>
> ---
Can you add comments in the commit text and in the code about why the
CLK_IS_CRITICAL flag is added to these clks? It makes it easier to
figure out why the flag is there months from now when we all forget
Quoting [email protected] (2018-11-16 10:09:00)
> From: Jasper Mattsson <[email protected]>
>
> This is required to mark gates as CLK_IS_CRITICAL.
>
> Fixes: 96596aa06628 ("clk: mediatek: add clk support for MT6797")
> Signed-off-by: Jasper Mattsson <[email protected]>
> Signed-off-by: Matthias Brugger <[email protected]>
> ---
These other two look ok to me. I'll apply them to the clk tree and wait
to merge to clk-next in case someone from Mediatek wants to review these
changes.
On 30/11/2018 07:47, Stephen Boyd wrote:
> Quoting [email protected] (2018-11-16 10:08:58)
>> From: Matthias Brugger <[email protected]>
>>
>> Jasper send this series some month ago. As there was no reaction from
>> his side, I'll do a friendly take-over.
>> I tested the patches on my Helios X20 boards and they fix the issue.
>> I didn't add a Tested-by tag as I added my Signed-off-by.
>>
>> Changes since v1:
>> - add a fixes tag.
>>
>> ---
>>
>> Currently, DRAM-related clocks and the axi_sel MUX are not marked with
>> CLK_IS_CRITICAL for MT6797. This causes memory corruption when the
>> system is booted without clk_ignore_unused.
>>
>> This patchset
>>
>> 1. Makes it possible to mark outputs of MUXes as critical by introducing
>> a new macro, MUX_FLAGS,
>> 2. Makes it possible to mark gates as critical by adding flags to
>> mtk_gate, and
>> 3. Marks axi_sel, ddrphycfg_sel, infra_dramc_f26m and infra_dramc_b_f26m
>> as critical.
>>
>> The addition of flags to mtk_gate also exists in the patch series "Add
>> basic and clock support for Mediatek MT8183 SoC" [1]. The type of
>> flags is unsigned int in that series, but the real type is unsigned
>> long, so my patch differs from that patch.
>
> Will anyone from Mediatek review this? Why aren't the people who signed
> off on drivers/clk/mediatek/clk-mt6797.c included on this patch series?
> They no longer work there?
>
My fault, I'll resend 3/3 with the comments you made. Added Kevin-CW now...
Quoting Matthias Brugger (2018-11-30 01:04:02)
>
>
> On 30/11/2018 07:47, Stephen Boyd wrote:
> > Quoting [email protected] (2018-11-16 10:08:58)
> >> From: Matthias Brugger <[email protected]>
> >>
> >> Jasper send this series some month ago. As there was no reaction from
> >> his side, I'll do a friendly take-over.
> >> I tested the patches on my Helios X20 boards and they fix the issue.
> >> I didn't add a Tested-by tag as I added my Signed-off-by.
> >>
> >> Changes since v1:
> >> - add a fixes tag.
> >>
> >> ---
> >>
> >> Currently, DRAM-related clocks and the axi_sel MUX are not marked with
> >> CLK_IS_CRITICAL for MT6797. This causes memory corruption when the
> >> system is booted without clk_ignore_unused.
> >>
> >> This patchset
> >>
> >> 1. Makes it possible to mark outputs of MUXes as critical by introducing
> >> a new macro, MUX_FLAGS,
> >> 2. Makes it possible to mark gates as critical by adding flags to
> >> mtk_gate, and
> >> 3. Marks axi_sel, ddrphycfg_sel, infra_dramc_f26m and infra_dramc_b_f26m
> >> as critical.
> >>
> >> The addition of flags to mtk_gate also exists in the patch series "Add
> >> basic and clock support for Mediatek MT8183 SoC" [1]. The type of
> >> flags is unsigned int in that series, but the real type is unsigned
> >> long, so my patch differs from that patch.
> >
> > Will anyone from Mediatek review this? Why aren't the people who signed
> > off on drivers/clk/mediatek/clk-mt6797.c included on this patch series?
> > They no longer work there?
> >
>
> My fault, I'll resend 3/3 with the comments you made. Added Kevin-CW now...
I never saw anything on the list. Did I miss anything? I have the first
two patches in my local queue still but I never merged it to clk-next
because nobody replied or resent anything. Please resend the whole
series because I've lost track of what's going on now. Sorry.
Hi Stephen/Matthias
On Mon, 2019-01-07 at 12:56 -0800, Stephen Boyd wrote:
> Quoting Matthias Brugger (2018-11-30 01:04:02)
> >
> >
> > On 30/11/2018 07:47, Stephen Boyd wrote:
> > > Quoting [email protected] (2018-11-16 10:08:58)
> > >> From: Matthias Brugger <[email protected]>
> > >>
> > >> Jasper send this series some month ago. As there was no reaction from
> > >> his side, I'll do a friendly take-over.
> > >> I tested the patches on my Helios X20 boards and they fix the issue.
> > >> I didn't add a Tested-by tag as I added my Signed-off-by.
> > >>
> > >> Changes since v1:
> > >> - add a fixes tag.
> > >>
> > >> ---
> > >>
> > >> Currently, DRAM-related clocks and the axi_sel MUX are not marked with
> > >> CLK_IS_CRITICAL for MT6797. This causes memory corruption when the
> > >> system is booted without clk_ignore_unused.
> > >>
> > >> This patchset
> > >>
> > >> 1. Makes it possible to mark outputs of MUXes as critical by introducing
> > >> a new macro, MUX_FLAGS,
> > >> 2. Makes it possible to mark gates as critical by adding flags to
> > >> mtk_gate, and
> > >> 3. Marks axi_sel, ddrphycfg_sel, infra_dramc_f26m and infra_dramc_b_f26m
> > >> as critical.
> > >>
> > >> The addition of flags to mtk_gate also exists in the patch series "Add
> > >> basic and clock support for Mediatek MT8183 SoC" [1]. The type of
> > >> flags is unsigned int in that series, but the real type is unsigned
> > >> long, so my patch differs from that patch.
> > >
> > > Will anyone from Mediatek review this? Why aren't the people who signed
> > > off on drivers/clk/mediatek/clk-mt6797.c included on this patch series?
> > > They no longer work there?
> > >
> >
> > My fault, I'll resend 3/3 with the comments you made. Added Kevin-CW now...
>
> I never saw anything on the list. Did I miss anything? I have the first
> two patches in my local queue still but I never merged it to clk-next
> because nobody replied or resent anything. Please resend the whole
> series because I've lost track of what's going on now. Sorry.
>
>
sorry for late response. Kelvin-CW and I are responsible for 6797
clk.You have my Ack:
Acked-by: Mars Cheng <[email protected]>
Thanks.
> _______________________________________________
> Linux-mediatek mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
On 07/01/2019 21:56, Stephen Boyd wrote:
> Quoting Matthias Brugger (2018-11-30 01:04:02)
>>
>>
>> On 30/11/2018 07:47, Stephen Boyd wrote:
>>> Quoting [email protected] (2018-11-16 10:08:58)
>>>> From: Matthias Brugger <[email protected]>
>>>>
>>>> Jasper send this series some month ago. As there was no reaction from
>>>> his side, I'll do a friendly take-over.
>>>> I tested the patches on my Helios X20 boards and they fix the issue.
>>>> I didn't add a Tested-by tag as I added my Signed-off-by.
>>>>
>>>> Changes since v1:
>>>> - add a fixes tag.
>>>>
>>>> ---
>>>>
>>>> Currently, DRAM-related clocks and the axi_sel MUX are not marked with
>>>> CLK_IS_CRITICAL for MT6797. This causes memory corruption when the
>>>> system is booted without clk_ignore_unused.
>>>>
>>>> This patchset
>>>>
>>>> 1. Makes it possible to mark outputs of MUXes as critical by introducing
>>>> a new macro, MUX_FLAGS,
>>>> 2. Makes it possible to mark gates as critical by adding flags to
>>>> mtk_gate, and
>>>> 3. Marks axi_sel, ddrphycfg_sel, infra_dramc_f26m and infra_dramc_b_f26m
>>>> as critical.
>>>>
>>>> The addition of flags to mtk_gate also exists in the patch series "Add
>>>> basic and clock support for Mediatek MT8183 SoC" [1]. The type of
>>>> flags is unsigned int in that series, but the real type is unsigned
>>>> long, so my patch differs from that patch.
>>>
>>> Will anyone from Mediatek review this? Why aren't the people who signed
>>> off on drivers/clk/mediatek/clk-mt6797.c included on this patch series?
>>> They no longer work there?
>>>
>>
>> My fault, I'll resend 3/3 with the comments you made. Added Kevin-CW now...
>
> I never saw anything on the list. Did I miss anything? I have the first
> two patches in my local queue still but I never merged it to clk-next
> because nobody replied or resent anything. Please resend the whole
> series because I've lost track of what's going on now. Sorry.
>
I resend just 3/3 as due to your comment I thought you applied the first two
already:
https://patchwork.kernel.org/patch/10737933/
Anyway I'll resend.
Regards,
Matthias