The current behavior is that clk_round_rate would return the same clock
rate passed to it for valid PLL configurations. This change will return
the exact rate the PLL will provide in accordance with clk API.
Signed-off-by: Robert Yang <[email protected]>
---
Changes in V2:
- Move input divider (m == 0) check into the cfg constraints check
condition. Forgo adding WARN_ON and avoid using 0 input divider
all together.
drivers/clk/tegra/clk-pll.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 17a058c3bbc1..2a800a9c56e6 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -589,12 +589,13 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
cfg->n = cfg->output_rate / cfreq;
cfg->cpcon = OUT_OF_TABLE_CPCON;
- if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
- (1 << p_div) > divp_max(pll)
- || cfg->output_rate > pll->params->vco_max) {
+ if (cfg->m == 0 || cfg->m > divm_max(pll) ||
+ cfg->n > divn_max(pll) || (1 << p_div) > divp_max(pll) ||
+ cfg->output_rate > pll->params->vco_max) {
return -EINVAL;
}
+ cfg->output_rate = cfg->n * DIV_ROUND_UP(parent_rate, cfg->m);
cfg->output_rate >>= p_div;
if (pll->params->pdiv_tohw) {
--
2.17.1
Quoting Robert Yang (2018-09-25 14:49:40)
> The current behavior is that clk_round_rate would return the same clock
> rate passed to it for valid PLL configurations. This change will return
> the exact rate the PLL will provide in accordance with clk API.
>
> Signed-off-by: Robert Yang <[email protected]>
> ---
I'm waiting for someone from Nvidia/Tegra background to review this
change.
On 17.10.2018 1:47, Stephen Boyd wrote:
> Quoting Robert Yang (2018-09-25 14:49:40)
>> The current behavior is that clk_round_rate would return the same clock
>> rate passed to it for valid PLL configurations. This change will return
>> the exact rate the PLL will provide in accordance with clk API.
>>
>> Signed-off-by: Robert Yang <[email protected]>
>> ---
>
> I'm waiting for someone from Nvidia/Tegra background to review this
> change.
>
Apparently Peter is taking a pause. I think Thierry's ACK to V1 should be still valid here.
Also, if this helps:
Reviewed-by: Dmitry Osipenko <[email protected]>
Tested-by: Dmitry Osipenko <[email protected]>
On Tue, Sep 25, 2018 at 05:49:40PM -0400, Robert Yang wrote:
> The current behavior is that clk_round_rate would return the same clock
> rate passed to it for valid PLL configurations. This change will return
> the exact rate the PLL will provide in accordance with clk API.
>
> Signed-off-by: Robert Yang <[email protected]>
> ---
> Changes in V2:
> - Move input divider (m == 0) check into the cfg constraints check
> condition. Forgo adding WARN_ON and avoid using 0 input divider
> all together.
>
> drivers/clk/tegra/clk-pll.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
Acked-by: Thierry Reding <[email protected]>
Quoting Robert Yang (2018-09-25 14:49:40)
> The current behavior is that clk_round_rate would return the same clock
> rate passed to it for valid PLL configurations. This change will return
> the exact rate the PLL will provide in accordance with clk API.
>
> Signed-off-by: Robert Yang <[email protected]>
> ---
Applied to clk-next