Add support for octal mode IO data transfer.
Micron flash, mt35xu512aba, supports octal mode data transfer and
NXP FlexSPI controller supports 8 data lines for data transfer (Rx/Tx).
Patch series
* Add support for octal mode flags and parsing of same in spi driver.
* Add parsing logic for spi-mem framework and m25p80.c device file.
* Add opcodes for octal I/O commands in spi-nor framework, Read and Write proto for (1-1-8/1-8-8) mode.
Opcodes are added as per octal data IO commands required for mt35xu512aba [1] flash.
* Add mode bit required for octal mode in nxp-fspi driver [2].
* Define binding property 'spi-rx/tx-bus-width' for LX2160ARDB target [2].
Tested on LX2160ARDB target with nxp-fspi driver, below are
Read performance number of 1-1-1 and 1-1-8 read protocol.
root@lxxx:~# cat /proc/mtd
dev: size erasesize name
mtd0: 04000000 00001000 "spi0.0"
mtd1: 04000000 00001000 "spi0.1"
root@lxxx:~# time mtd_debug read /dev/mtd0 0x0 0x1000000 0read
Copied 16777216 bytes from address 0x00000000 in flash to 0read
real 0m2.792s
user 0m0.000s
sys 0m2.790s
root@lxxx:~# time mtd_debug read /dev/mtd1 0x0 0x1000000 0read
Copied 16777216 bytes from address 0x00000000 in flash to 0read
real 0m0.441s
user 0m0.000s
sys 0m0.440s
root@ls1012ardb:~#
Flash device MTD0 configured in 1-1-1 protocol.
Flash device MTD1 configured in 1-1-8 protocol.
[1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=70384&state=*
[2] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=76402
Yogesh Gaur (7):
spi: add support for octal mode I/O data transfer
spi: spi-mem: add support for octal mode I/O data transfer
mtd: spi-nor: add opcodes for octal Read/Write commands
mtd: spi-nor: add octal read flag for flash mt35xu512aba
mtd: m25p80: add support of octal mode I/O transfer
spi: nxp-fspi: add octal mode flag bit for octal support
arm64: dts: lx2160a: update fspi node
Changes for v6:
- Correct S-o-b tag with full author name as 'Yogesh Narayan Gaur'.
- Rebase on top of v4.20-rc5.
Changes for v5:
- Modified string 'octo' as 'octal' in all patches.
Changes for v4:
- Rebase on top of v4.20-rc2.
- Modify octo entries enum value in spi.h.
Changes for v3:
- Add octo mode support in spi_setup().
- Rename all patches with 'octal' string modified as 'octo'.
Changes for v2:
- Incorporated review comments of Boris and Vignesh.
Yogesh Gaur (7):
spi: add support for octal mode I/O data transfer
spi: spi-mem: add support for octal mode I/O data transfer
mtd: spi-nor: add opcodes for octal Read/Write commands
mtd: spi-nor: add octal read flag for flash mt35xu512aba
mtd: m25p80: add support of octal mode I/O transfer
spi: nxp-fspi: add octal mode flag bit for octal support
arm64: dts: lx2160a: update fspi node
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 ++++
drivers/mtd/devices/m25p80.c | 9 ++++++++-
drivers/mtd/spi-nor/spi-nor.c | 19 ++++++++++++++++---
drivers/spi/spi-mem.c | 9 ++++++++-
drivers/spi/spi-nxp-fspi.c | 4 ++--
drivers/spi/spi.c | 12 ++++++++++--
include/linux/mtd/spi-nor.h | 16 ++++++++++++----
include/linux/spi/spi.h | 4 +++-
8 files changed, 63 insertions(+), 14 deletions(-)
--
2.7.4
Add flags for Octal mode I/O data transfer
Required for the SPI controller which can do the data transfer (TX/RX)
on 8 data lines e.g. NXP FlexSPI controller.
SPI_TX_OCTAL: transmit with 8 wires
SPI_RX_OCTAL: receive with 8 wires
Signed-off-by: Yogesh Narayan Gaur <[email protected]>
Reviewed-by: Boris Brezillon <[email protected]>
---
Changes for v6:
- Correct S-o-b tag with full author name as 'Yogesh Narayan Gaur'.
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- Rebase on top of v4.20-rc2
Changes for v3:
- Modified string 'octal' with 'octo'.
- Add octo mode support in spi_setup().
Changes for v2:
- Incorporated review comments of Boris.
drivers/spi/spi.c | 12 ++++++++++--
include/linux/spi/spi.h | 4 +++-
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 6ca5940..95249b8 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -1617,6 +1617,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
case 4:
spi->mode |= SPI_TX_QUAD;
break;
+ case 8:
+ spi->mode |= SPI_TX_OCTAL;
+ break;
default:
dev_warn(&ctlr->dev,
"spi-tx-bus-width %d not supported\n",
@@ -1635,6 +1638,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
case 4:
spi->mode |= SPI_RX_QUAD;
break;
+ case 8:
+ spi->mode |= SPI_RX_OCTAL;
+ break;
default:
dev_warn(&ctlr->dev,
"spi-rx-bus-width %d not supported\n",
@@ -2823,7 +2829,8 @@ int spi_setup(struct spi_device *spi)
/* if it is SPI_3WIRE mode, DUAL and QUAD should be forbidden
*/
if ((spi->mode & SPI_3WIRE) && (spi->mode &
- (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)))
+ (SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL |
+ SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL)))
return -EINVAL;
/* help drivers fail *cleanly* when they need options
* that aren't supported with their current controller
@@ -2832,7 +2839,8 @@ int spi_setup(struct spi_device *spi)
*/
bad_bits = spi->mode & ~(spi->controller->mode_bits | SPI_CS_WORD);
ugly_bits = bad_bits &
- (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD);
+ (SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL |
+ SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL);
if (ugly_bits) {
dev_warn(&spi->dev,
"setup: ignoring unsupported mode bits %x\n",
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 6be77fa..0c1ca5d 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -154,7 +154,9 @@ struct spi_device {
#define SPI_TX_QUAD 0x200 /* transmit with 4 wires */
#define SPI_RX_DUAL 0x400 /* receive with 2 wires */
#define SPI_RX_QUAD 0x800 /* receive with 4 wires */
-#define SPI_CS_WORD 0x1000 /* toggle cs after each word */
+#define SPI_CS_WORD 0x1000 /* toggle cs after each word */
+#define SPI_TX_OCTAL 0x2000 /* transmit with 8 wires */
+#define SPI_RX_OCTAL 0x4000 /* receive with 8 wires */
int irq;
void *controller_state;
void *controller_data;
--
2.7.4
Add support for octal mode I/O data transfer in spi-mem framework.
Signed-off-by: Yogesh Narayan Gaur <[email protected]>
Reviewed-by: Boris Brezillon <[email protected]>
---
Changes for v6:
- Correct S-o-b tag with full author name as 'Yogesh Narayan Gaur'.
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2:
- Patch added in v2 version.
drivers/spi/spi-mem.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index 62a7b80..5e15d62 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -12,7 +12,7 @@
#include "internals.h"
-#define SPI_MEM_MAX_BUSWIDTH 4
+#define SPI_MEM_MAX_BUSWIDTH 8
/**
* spi_controller_dma_map_mem_op_data() - DMA-map the buffer attached to a
@@ -121,6 +121,13 @@ static int spi_check_buswidth_req(struct spi_mem *mem, u8 buswidth, bool tx)
break;
+ case 8:
+ if ((tx && (mode & SPI_TX_OCTAL)) ||
+ (!tx && (mode & SPI_RX_OCTAL)))
+ return 0;
+
+ break;
+
default:
break;
}
--
2.7.4
Add octal mode flags for octal I/O data transfer support.
NXP FlexSPI controller supports 8 lines Rx/Tx data transfer.
Signed-off-by: Yogesh Narayan Gaur <[email protected]>
---
Changes for v6:
- Correct S-o-b tag with full author name as 'Yogesh Narayan Gaur'.
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2:
- None
drivers/spi/spi-nxp-fspi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
index 6d497f4..cfd3126 100644
--- a/drivers/spi/spi-nxp-fspi.c
+++ b/drivers/spi/spi-nxp-fspi.c
@@ -995,8 +995,8 @@ static int nxp_fspi_probe(struct platform_device *pdev)
if (!ctlr)
return -ENOMEM;
- ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD |
- SPI_TX_DUAL | SPI_TX_QUAD;
+ ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL |
+ SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL;
f = spi_controller_get_devdata(ctlr);
f->dev = dev;
--
2.7.4
Add support for octal mode I/O data transfer based on the controller (spi)
mode.
Assign hw-capability mask bits for octal transfer.
Signed-off-by: Yogesh Narayan Gaur <[email protected]>
---
Changes for v6:
- Correct S-o-b tag with full author name as 'Yogesh Narayan Gaur'.
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2:
- Incorporated review comments of Boris.
drivers/mtd/devices/m25p80.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index c4a1d04..651bab6 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -195,7 +195,14 @@ static int m25p_probe(struct spi_mem *spimem)
spi_mem_set_drvdata(spimem, flash);
flash->spimem = spimem;
- if (spi->mode & SPI_RX_QUAD) {
+ if (spi->mode & SPI_RX_OCTAL) {
+ hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+
+ if (spi->mode & SPI_TX_OCTAL)
+ hwcaps.mask |= (SNOR_HWCAPS_READ_1_8_8 |
+ SNOR_HWCAPS_PP_1_1_8 |
+ SNOR_HWCAPS_PP_1_8_8);
+ } else if (spi->mode & SPI_RX_QUAD) {
hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
if (spi->mode & SPI_TX_QUAD)
--
2.7.4
Flash mt35xu512aba connected to FlexSPI controller supports
1-1-8/1-8-8 protocol.
Added flag spi-rx-bus-width and spi-tx-bus-width with values as
8 and 8 respectively for both flashes connected at CS0 and CS1.
Signed-off-by: Yogesh Narayan Gaur <[email protected]>
---
Changes for v6:
- Correct S-o-b tag with full author name as 'Yogesh Narayan Gaur'.
Changes for v5:
- None
Changes for v4:
- None
Changes for v3:
- None
Changes for v2:
- None
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 3b20c97..24cc41c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -45,6 +45,8 @@
m25p,fast-read;
spi-max-frequency = <20000000>;
reg = <0>;
+ spi-rx-bus-width = <8>;
+ spi-tx-bus-width = <8>;
};
mt35xu512aba1: flash@1 {
@@ -54,6 +56,8 @@
m25p,fast-read;
spi-max-frequency = <20000000>;
reg = <1>;
+ spi-rx-bus-width = <8>;
+ spi-tx-bus-width = <8>;
};
};
--
2.7.4
- Add opcodes for octal I/O commands
* Read : 1-1-8 and 1-8-8 protocol
* Write : 1-1-8 and 1-8-8 protocol
* opcodes for 4-byte address mode command
- Entry of macros in _convert_3to4_xxx function
- Add flag specifying flash support octal read commands.
Signed-off-by: Vignesh R <[email protected]>
Signed-off-by: Yogesh Narayan Gaur <[email protected]>
---
Changes for v6:
- Correct S-o-b tag with full author name as 'Yogesh Narayan Gaur'.
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2:
- Incorporated review comments of Boris and Vignesh
drivers/mtd/spi-nor/spi-nor.c | 16 ++++++++++++++--
include/linux/mtd/spi-nor.h | 16 ++++++++++++----
2 files changed, 26 insertions(+), 6 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 6e13bbd..872d707 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -68,7 +68,7 @@ enum spi_nor_read_command_index {
SNOR_CMD_READ_4_4_4,
SNOR_CMD_READ_1_4_4_DTR,
- /* Octo SPI */
+ /* Octal SPI */
SNOR_CMD_READ_1_1_8,
SNOR_CMD_READ_1_8_8,
SNOR_CMD_READ_8_8_8,
@@ -85,7 +85,7 @@ enum spi_nor_pp_command_index {
SNOR_CMD_PP_1_4_4,
SNOR_CMD_PP_4_4_4,
- /* Octo SPI */
+ /* Octal SPI */
SNOR_CMD_PP_1_1_8,
SNOR_CMD_PP_1_8_8,
SNOR_CMD_PP_8_8_8,
@@ -278,6 +278,7 @@ struct flash_info {
#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
#define USE_CLSR BIT(14) /* use CLSR command */
+#define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */
/* Part specific fixup hooks. */
const struct spi_nor_fixups *fixups;
@@ -398,6 +399,8 @@ static u8 spi_nor_convert_3to4_read(u8 opcode)
{ SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
{ SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
{ SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
+ { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
+ { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
{ SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
{ SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
@@ -414,6 +417,8 @@ static u8 spi_nor_convert_3to4_program(u8 opcode)
{ SPINOR_OP_PP, SPINOR_OP_PP_4B },
{ SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
{ SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
+ { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
+ { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
};
return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
@@ -3591,6 +3596,13 @@ static int spi_nor_init_params(struct spi_nor *nor,
SNOR_PROTO_1_1_4);
}
+ if (info->flags & SPI_NOR_OCTAL_READ) {
+ params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+ spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_8],
+ 0, 8, SPINOR_OP_READ_1_1_8,
+ SNOR_PROTO_1_1_8);
+ }
+
/* Page Program settings. */
params->hwcaps.mask |= SNOR_HWCAPS_PP;
spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index fa2d89e..2353af8 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -46,9 +46,13 @@
#define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
#define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
+#define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
+#define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
#define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
#define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
+#define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */
+#define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */
#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
#define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
@@ -69,9 +73,13 @@
#define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
#define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
#define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
+#define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */
+#define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */
#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
#define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
#define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
+#define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */
+#define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */
#define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
#define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
@@ -458,7 +466,7 @@ struct spi_nor_hwcaps {
/*
*(Fast) Read capabilities.
* MUST be ordered by priority: the higher bit position, the higher priority.
- * As a matter of performances, it is relevant to use Octo SPI protocols first,
+ * As a matter of performances, it is relevant to use Octal SPI protocols first,
* then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
* (Slow) Read.
*/
@@ -479,7 +487,7 @@ struct spi_nor_hwcaps {
#define SNOR_HWCAPS_READ_4_4_4 BIT(9)
#define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
-#define SNOR_HWCPAS_READ_OCTO GENMASK(14, 11)
+#define SNOR_HWCPAS_READ_OCTAL GENMASK(14, 11)
#define SNOR_HWCAPS_READ_1_1_8 BIT(11)
#define SNOR_HWCAPS_READ_1_8_8 BIT(12)
#define SNOR_HWCAPS_READ_8_8_8 BIT(13)
@@ -488,7 +496,7 @@ struct spi_nor_hwcaps {
/*
* Page Program capabilities.
* MUST be ordered by priority: the higher bit position, the higher priority.
- * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
+ * Like (Fast) Read capabilities, Octal/Quad SPI protocols are preferred to the
* legacy SPI 1-1-1 protocol.
* Note that Dual Page Programs are not supported because there is no existing
* JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
@@ -502,7 +510,7 @@ struct spi_nor_hwcaps {
#define SNOR_HWCAPS_PP_1_4_4 BIT(18)
#define SNOR_HWCAPS_PP_4_4_4 BIT(19)
-#define SNOR_HWCAPS_PP_OCTO GENMASK(22, 20)
+#define SNOR_HWCAPS_PP_OCTAL GENMASK(22, 20)
#define SNOR_HWCAPS_PP_1_1_8 BIT(20)
#define SNOR_HWCAPS_PP_1_8_8 BIT(21)
#define SNOR_HWCAPS_PP_8_8_8 BIT(22)
--
2.7.4
Add octal read flag for flash mt35xu512aba.
This flash, mt35xu512aba, is only complaint to SFDP JESD216B and does
not seem to support newer JESD216C standard that provides auto
detection of Octal mode capabilities and opcodes. Therefore, this
capability is manually added using new SPI_NOR_OCTAL_READ flag.
Signed-off-by: Vignesh R <[email protected]>
Signed-off-by: Yogesh Narayan Gaur <[email protected]>
---
Changes for v6:
- Correct S-o-b tag with full author name as 'Yogesh Narayan Gaur'.
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2:
- Incorporated review comments of Boris and Vignesh
drivers/mtd/spi-nor/spi-nor.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 872d707..53a3bcc 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1877,7 +1877,8 @@ static const struct flash_info spi_nor_ids[] = {
/* Micron */
{
"mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
- SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES)
+ SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
+ SPI_NOR_4B_OPCODES)
},
/* PMC */
--
2.7.4
Hi,
On 19/12/18 3:41 PM, Yogesh Narayan Gaur wrote:
> Add support for octal mode IO data transfer.
> Micron flash, mt35xu512aba, supports octal mode data transfer and
> NXP FlexSPI controller supports 8 data lines for data transfer (Rx/Tx).
>
> Patch series
> * Add support for octal mode flags and parsing of same in spi driver.
> * Add parsing logic for spi-mem framework and m25p80.c device file.
> * Add opcodes for octal I/O commands in spi-nor framework, Read and Write proto for (1-1-8/1-8-8) mode.
> Opcodes are added as per octal data IO commands required for mt35xu512aba [1] flash.
> * Add mode bit required for octal mode in nxp-fspi driver [2].
> * Define binding property 'spi-rx/tx-bus-width' for LX2160ARDB target [2].
>
> Tested on LX2160ARDB target with nxp-fspi driver, below are
> Read performance number of 1-1-1 and 1-1-8 read protocol.
>
> root@lxxx:~# cat /proc/mtd
> dev: size erasesize name
> mtd0: 04000000 00001000 "spi0.0"
> mtd1: 04000000 00001000 "spi0.1"
> root@lxxx:~# time mtd_debug read /dev/mtd0 0x0 0x1000000 0read
> Copied 16777216 bytes from address 0x00000000 in flash to 0read
>
> real 0m2.792s
> user 0m0.000s
> sys 0m2.790s
> root@lxxx:~# time mtd_debug read /dev/mtd1 0x0 0x1000000 0read
> Copied 16777216 bytes from address 0x00000000 in flash to 0read
>
> real 0m0.441s
> user 0m0.000s
> sys 0m0.440s
> root@ls1012ardb:~#
>
>
> Flash device MTD0 configured in 1-1-1 protocol.
> Flash device MTD1 configured in 1-1-8 protocol.
>
> [1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=70384&state=*
> [2] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=76402
>
> Yogesh Gaur (7):
> spi: add support for octal mode I/O data transfer
> spi: spi-mem: add support for octal mode I/O data transfer
These two patches are already merged and is now part of linux-next[1].
Its preferred to send patches based on top of latest linux-next so as to
avoid resending patches that have already been picked up by the maintainer.
[1]
commit 6b03061f882de49b83ccf44beb3a12c920a2da1b
Author: Yogesh Narayan Gaur <[email protected]>
Date: Mon Dec 3 08:39:06 2018 +0000
spi: add support for octal mode I/O data transfer
commit b12a084c8729ef423089bb9a5a143eed39cd94e7
Author: Yogesh Narayan Gaur <[email protected]>
Date: Mon Dec 3 08:39:12 2018 +0000
spi: spi-mem: add support for octal mode I/O data transfer
Regards
Vignesh
> mtd: spi-nor: add opcodes for octal Read/Write commands
> mtd: spi-nor: add octal read flag for flash mt35xu512aba
> mtd: m25p80: add support of octal mode I/O transfer
> spi: nxp-fspi: add octal mode flag bit for octal support
> arm64: dts: lx2160a: update fspi node
>
> Changes for v6:
> - Correct S-o-b tag with full author name as 'Yogesh Narayan Gaur'.
> - Rebase on top of v4.20-rc5.
> Changes for v5:
> - Modified string 'octo' as 'octal' in all patches.
> Changes for v4:
> - Rebase on top of v4.20-rc2.
> - Modify octo entries enum value in spi.h.
> Changes for v3:
> - Add octo mode support in spi_setup().
> - Rename all patches with 'octal' string modified as 'octo'.
> Changes for v2:
> - Incorporated review comments of Boris and Vignesh.
>
> Yogesh Gaur (7):
> spi: add support for octal mode I/O data transfer
> spi: spi-mem: add support for octal mode I/O data transfer
> mtd: spi-nor: add opcodes for octal Read/Write commands
> mtd: spi-nor: add octal read flag for flash mt35xu512aba
> mtd: m25p80: add support of octal mode I/O transfer
> spi: nxp-fspi: add octal mode flag bit for octal support
> arm64: dts: lx2160a: update fspi node
>
> arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 ++++
> drivers/mtd/devices/m25p80.c | 9 ++++++++-
> drivers/mtd/spi-nor/spi-nor.c | 19 ++++++++++++++++---
> drivers/spi/spi-mem.c | 9 ++++++++-
> drivers/spi/spi-nxp-fspi.c | 4 ++--
> drivers/spi/spi.c | 12 ++++++++++--
> include/linux/mtd/spi-nor.h | 16 ++++++++++++----
> include/linux/spi/spi.h | 4 +++-
> 8 files changed, 63 insertions(+), 14 deletions(-)
>
--
Regards
Vignesh
Hi Vignesh,
> -----Original Message-----
> From: Vignesh R [mailto:[email protected]]
> Sent: Wednesday, December 19, 2018 6:14 PM
> To: Yogesh Narayan Gaur <[email protected]>; linux-
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]
> Cc: [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; linux-
> [email protected]
> Subject: Re: [PATCH v6 0/7] spi: add support for octal mode
>
> Hi,
>
> On 19/12/18 3:41 PM, Yogesh Narayan Gaur wrote:
> > Add support for octal mode IO data transfer.
> > Micron flash, mt35xu512aba, supports octal mode data transfer and NXP
> > FlexSPI controller supports 8 data lines for data transfer (Rx/Tx).
> >
> > Patch series
> > * Add support for octal mode flags and parsing of same in spi driver.
> > * Add parsing logic for spi-mem framework and m25p80.c device file.
> > * Add opcodes for octal I/O commands in spi-nor framework, Read and Write
> proto for (1-1-8/1-8-8) mode.
> > Opcodes are added as per octal data IO commands required for
> mt35xu512aba [1] flash.
> > * Add mode bit required for octal mode in nxp-fspi driver [2].
> > * Define binding property 'spi-rx/tx-bus-width' for LX2160ARDB target [2].
> >
> > Tested on LX2160ARDB target with nxp-fspi driver, below are Read
> > performance number of 1-1-1 and 1-1-8 read protocol.
> >
> > root@lxxx:~# cat /proc/mtd
> > dev: size erasesize name
> > mtd0: 04000000 00001000 "spi0.0"
> > mtd1: 04000000 00001000 "spi0.1"
> > root@lxxx:~# time mtd_debug read /dev/mtd0 0x0 0x1000000 0read
> > Copied 16777216 bytes from address 0x00000000 in flash to 0read
> >
> > real 0m2.792s
> > user 0m0.000s
> > sys 0m2.790s
> > root@lxxx:~# time mtd_debug read /dev/mtd1 0x0 0x1000000 0read
> > Copied 16777216 bytes from address 0x00000000 in flash to 0read
> >
> > real 0m0.441s
> > user 0m0.000s
> > sys 0m0.440s
> > root@ls1012ardb:~#
> >
> >
> > Flash device MTD0 configured in 1-1-1 protocol.
> > Flash device MTD1 configured in 1-1-8 protocol.
> >
> > [1]
> > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpat
> > chwork.ozlabs.org%2Fproject%2Flinux-
> mtd%2Flist%2F%3Fseries%3D70384%26s
> >
> tate%3D*&data=02%7C01%7Cyogeshnarayan.gaur%40nxp.com%7Cac5c9
> ca4ad0
> >
> 84f10762208d665af9130%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0
> %7C636
> >
> 808202064181032&sdata=LCjo%2B%2FhIpEYygsLHMFzb65ZtXjsDdhEAVV4
> %2BjQ
> > iyUtI%3D&reserved=0 [2]
> > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpat
> > chwork.ozlabs.org%2Fproject%2Flinux-
> mtd%2Flist%2F%3Fseries%3D76402&
> > ;data=02%7C01%7Cyogeshnarayan.gaur%40nxp.com%7Cac5c9ca4ad084f107
> 62208d
> >
> 665af9130%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636808202
> 064181
> >
> 032&sdata=A9hAX4oTyJPzc4J3y3PqwNagWEqvpGolf8RE9RyYV28%3D&am
> p;reser
> > ved=0
> >
> > Yogesh Gaur (7):
> > spi: add support for octal mode I/O data transfer
> > spi: spi-mem: add support for octal mode I/O data transfer
>
>
> These two patches are already merged and is now part of linux-next[1].
> Its preferred to send patches based on top of latest linux-next so as to avoid
> resending patches that have already been picked up by the maintainer.
>
> [1]
> commit 6b03061f882de49b83ccf44beb3a12c920a2da1b
> Author: Yogesh Narayan Gaur <[email protected]>
> Date: Mon Dec 3 08:39:06 2018 +0000
>
> spi: add support for octal mode I/O data transfer
>
> commit b12a084c8729ef423089bb9a5a143eed39cd94e7
> Author: Yogesh Narayan Gaur <[email protected]>
> Date: Mon Dec 3 08:39:12 2018 +0000
>
> spi: spi-mem: add support for octal mode I/O data transfer
>
>
I have checked on repo "git://git.infradead.org/linux-mtd.git" on branch "spi-nor/next" and in that kernel version is 4.20.-rc5.
In this repo above 2 patches are not present and hence has send the patches by moving to top of this repo.
Can you please let me know the repo of linux-next and branch to use.
--
Regards
Yogesh Gaur
> Regards
> Vignesh
>
> > mtd: spi-nor: add opcodes for octal Read/Write commands
> > mtd: spi-nor: add octal read flag for flash mt35xu512aba
> > mtd: m25p80: add support of octal mode I/O transfer
> > spi: nxp-fspi: add octal mode flag bit for octal support
> > arm64: dts: lx2160a: update fspi node
> >
> > Changes for v6:
> > - Correct S-o-b tag with full author name as 'Yogesh Narayan Gaur'.
> > - Rebase on top of v4.20-rc5.
> > Changes for v5:
> > - Modified string 'octo' as 'octal' in all patches.
> > Changes for v4:
> > - Rebase on top of v4.20-rc2.
> > - Modify octo entries enum value in spi.h.
> > Changes for v3:
> > - Add octo mode support in spi_setup().
> > - Rename all patches with 'octal' string modified as 'octo'.
> > Changes for v2:
> > - Incorporated review comments of Boris and Vignesh.
> >
> > Yogesh Gaur (7):
> > spi: add support for octal mode I/O data transfer
> > spi: spi-mem: add support for octal mode I/O data transfer
> > mtd: spi-nor: add opcodes for octal Read/Write commands
> > mtd: spi-nor: add octal read flag for flash mt35xu512aba
> > mtd: m25p80: add support of octal mode I/O transfer
> > spi: nxp-fspi: add octal mode flag bit for octal support
> > arm64: dts: lx2160a: update fspi node
> >
> > arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 ++++
> > drivers/mtd/devices/m25p80.c | 9 ++++++++-
> > drivers/mtd/spi-nor/spi-nor.c | 19 ++++++++++++++++---
> > drivers/spi/spi-mem.c | 9 ++++++++-
> > drivers/spi/spi-nxp-fspi.c | 4 ++--
> > drivers/spi/spi.c | 12 ++++++++++--
> > include/linux/mtd/spi-nor.h | 16 ++++++++++++----
> > include/linux/spi/spi.h | 4 +++-
> > 8 files changed, 63 insertions(+), 14 deletions(-)
> >
>
> --
> Regards
> Vignesh
Hi All,
> -----Original Message-----
> From: Vignesh R [mailto:[email protected]]
> Sent: Thursday, December 20, 2018 12:03 PM
> To: Yogesh Narayan Gaur <[email protected]>; linux-
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]
> Cc: [email protected]; [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; linux-
> [email protected]
> Subject: Re: [PATCH v6 0/7] spi: add support for octal mode
>
> Hi,
>
> On 20/12/18 11:02 AM, Yogesh Narayan Gaur wrote:
> [...]
> >>> Yogesh Gaur (7):
> >>> spi: add support for octal mode I/O data transfer
> >>> spi: spi-mem: add support for octal mode I/O data transfer
> >>
> >>
> >> These two patches are already merged and is now part of linux-next[1].
> >> Its preferred to send patches based on top of latest linux-next so as
> >> to avoid resending patches that have already been picked up by the
> maintainer.
> >>
> >> [1]
> >> commit 6b03061f882de49b83ccf44beb3a12c920a2da1b
> >> Author: Yogesh Narayan Gaur <[email protected]>
> >> Date: Mon Dec 3 08:39:06 2018 +0000
> >>
> >> spi: add support for octal mode I/O data transfer
> >>
> >> commit b12a084c8729ef423089bb9a5a143eed39cd94e7
> >> Author: Yogesh Narayan Gaur <[email protected]>
> >> Date: Mon Dec 3 08:39:12 2018 +0000
> >>
> >> spi: spi-mem: add support for octal mode I/O data transfer
> >>
> >>
> > I have checked on repo "git://git.infradead.org/linux-mtd.git" on branch "spi-
> nor/next" and in that kernel version is 4.20.-rc5.
> > In this repo above 2 patches are not present and hence has send the patches
> by moving to top of this repo.
> >
>
> Those patches are applied to spi tree:
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.ker
> nel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fbroonie%2Fspi.git%2Flog%
> 2F%3Fh%3Dfor-
> next&data=02%7C01%7Cyogeshnarayan.gaur%40nxp.com%7Cc24a66e695
> 7f4940e83708d66644f5bf%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0
> %7C636808843700180940&sdata=4IPwuRmJKv4qISAjD0W07OIA%2BWQpT
> 3E97T%2BSbSOrSN8%3D&reserved=0
>
> > Can you please let me know the repo of linux-next and branch to use.
> >
>
> The linux-next tree is the holding area for patches aimed at the next kernel
> merge window. This tree includes spi-nor/next as part of mtd/next as well as
> many other subsystem specific -next trees:
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.ker
> nel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fnext%2Flinux-
> next.git&data=02%7C01%7Cyogeshnarayan.gaur%40nxp.com%7Cc24a66e
> 6957f4940e83708d66644f5bf%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%
> 7C0%7C636808843700180940&sdata=VGMHZCjAgZfnSJeUHhkpgI0ygt9pvP
> y9KJs5Pzn64D0%3D&reserved=0 branch: master
>
>
Above repo "kernel/git/broonie/spi.git" and branch (for-next) are missing below 2 patches[1], which have been applied by Boris and present in repo "git://git.infradead.org/linux-mtd.git" on branch "spi-nor/next".
commit a98086e00420ad92cfa961bcbb457fbe52ec28c9
Author: Yogesh Narayan Gaur <[email protected]>
Date: Fri Oct 12 02:23:13 2018 +0000
mtd: spi-nor: add entry for mt35xu512aba flash
Add entry for mt35xu512aba Micron NOR flash.
This flash is having uniform sector erase size of 128KB, have
support of FSR(flag status register), flash size is 64MB and
supports 4-byte commands.
Signed-off-by: Yogesh Gaur <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
Signed-off-by: Boris Brezillon <[email protected]>
commit 0005aad094538e1c290b1cdb5b940e4a16f405b0
Author: Yogesh Narayan Gaur <[email protected]>
Date: Fri Oct 12 02:23:08 2018 +0000
mtd: spi-nor: add macros related to MICRON flash
Some MICRON related macros in spi-nor domain were ST.
Rename entries related to STMicroelectronics under macro SNOR_MFR_ST.
Added entry of MFR Id for Micron flashes, 0x002C.
Signed-off-by: Yogesh Gaur <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
Signed-off-by: Boris Brezillon <[email protected]>
Octal mode support patch series has dependency over these patches.
Should I send these two patches again or specifies them as dependency patches in the cover letter.
--
Regards
Yogesh Gaur
[1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=70384&state=*
> Regards
> Vignesh
>
> > --
> > Regards
> > Yogesh Gaur
> >
> >> Regards
> >> Vignesh
> >>
> >>> mtd: spi-nor: add opcodes for octal Read/Write commands
> >>> mtd: spi-nor: add octal read flag for flash mt35xu512aba
> >>> mtd: m25p80: add support of octal mode I/O transfer
> >>> spi: nxp-fspi: add octal mode flag bit for octal support
> >>> arm64: dts: lx2160a: update fspi node
> >>>
> >>> Changes for v6:
> >>> - Correct S-o-b tag with full author name as 'Yogesh Narayan Gaur'.
> >>> - Rebase on top of v4.20-rc5.
> >>> Changes for v5:
> >>> - Modified string 'octo' as 'octal' in all patches.
> >>> Changes for v4:
> >>> - Rebase on top of v4.20-rc2.
> >>> - Modify octo entries enum value in spi.h.
> >>> Changes for v3:
> >>> - Add octo mode support in spi_setup().
> >>> - Rename all patches with 'octal' string modified as 'octo'.
> >>> Changes for v2:
> >>> - Incorporated review comments of Boris and Vignesh.
> >>>
> >>> Yogesh Gaur (7):
> >>> spi: add support for octal mode I/O data transfer
> >>> spi: spi-mem: add support for octal mode I/O data transfer
> >>> mtd: spi-nor: add opcodes for octal Read/Write commands
> >>> mtd: spi-nor: add octal read flag for flash mt35xu512aba
> >>> mtd: m25p80: add support of octal mode I/O transfer
> >>> spi: nxp-fspi: add octal mode flag bit for octal support
> >>> arm64: dts: lx2160a: update fspi node
> >>>
> >>> arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 ++++
> >>> drivers/mtd/devices/m25p80.c | 9 ++++++++-
> >>> drivers/mtd/spi-nor/spi-nor.c | 19 ++++++++++++++++---
> >>> drivers/spi/spi-mem.c | 9 ++++++++-
> >>> drivers/spi/spi-nxp-fspi.c | 4 ++--
> >>> drivers/spi/spi.c | 12 ++++++++++--
> >>> include/linux/mtd/spi-nor.h | 16 ++++++++++++----
> >>> include/linux/spi/spi.h | 4 +++-
> >>> 8 files changed, 63 insertions(+), 14 deletions(-)
> >>>
> >>
> >> --
> >> Regards
> >> Vignesh
On Thu, 20 Dec 2018 08:23:07 +0000
Yogesh Narayan Gaur <[email protected]> wrote:
> Octal mode support patch series has dependency over these patches.
> Should I send these two patches again or specifies them as dependency patches in the cover letter.
No, you should either base your work on the master branch of the
linux-next repo [1] (as suggested by Vignesh) or wait
for 4.21-rc1/5.0-rc1 before sending a new version.
[1]https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/log/
Hi,
On 20/12/18 11:02 AM, Yogesh Narayan Gaur wrote:
[...]
>>> Yogesh Gaur (7):
>>> spi: add support for octal mode I/O data transfer
>>> spi: spi-mem: add support for octal mode I/O data transfer
>>
>>
>> These two patches are already merged and is now part of linux-next[1].
>> Its preferred to send patches based on top of latest linux-next so as to avoid
>> resending patches that have already been picked up by the maintainer.
>>
>> [1]
>> commit 6b03061f882de49b83ccf44beb3a12c920a2da1b
>> Author: Yogesh Narayan Gaur <[email protected]>
>> Date: Mon Dec 3 08:39:06 2018 +0000
>>
>> spi: add support for octal mode I/O data transfer
>>
>> commit b12a084c8729ef423089bb9a5a143eed39cd94e7
>> Author: Yogesh Narayan Gaur <[email protected]>
>> Date: Mon Dec 3 08:39:12 2018 +0000
>>
>> spi: spi-mem: add support for octal mode I/O data transfer
>>
>>
> I have checked on repo "git://git.infradead.org/linux-mtd.git" on branch "spi-nor/next" and in that kernel version is 4.20.-rc5.
> In this repo above 2 patches are not present and hence has send the patches by moving to top of this repo.
>
Those patches are applied to spi tree:
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git/log/?h=for-next
> Can you please let me know the repo of linux-next and branch to use.
>
The linux-next tree is the holding area for patches aimed at
the next kernel merge window. This tree includes spi-nor/next as part of mtd/next
as well as many other subsystem specific -next trees:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git branch: master
Regards
Vignesh
> --
> Regards
> Yogesh Gaur
>
>> Regards
>> Vignesh
>>
>>> mtd: spi-nor: add opcodes for octal Read/Write commands
>>> mtd: spi-nor: add octal read flag for flash mt35xu512aba
>>> mtd: m25p80: add support of octal mode I/O transfer
>>> spi: nxp-fspi: add octal mode flag bit for octal support
>>> arm64: dts: lx2160a: update fspi node
>>>
>>> Changes for v6:
>>> - Correct S-o-b tag with full author name as 'Yogesh Narayan Gaur'.
>>> - Rebase on top of v4.20-rc5.
>>> Changes for v5:
>>> - Modified string 'octo' as 'octal' in all patches.
>>> Changes for v4:
>>> - Rebase on top of v4.20-rc2.
>>> - Modify octo entries enum value in spi.h.
>>> Changes for v3:
>>> - Add octo mode support in spi_setup().
>>> - Rename all patches with 'octal' string modified as 'octo'.
>>> Changes for v2:
>>> - Incorporated review comments of Boris and Vignesh.
>>>
>>> Yogesh Gaur (7):
>>> spi: add support for octal mode I/O data transfer
>>> spi: spi-mem: add support for octal mode I/O data transfer
>>> mtd: spi-nor: add opcodes for octal Read/Write commands
>>> mtd: spi-nor: add octal read flag for flash mt35xu512aba
>>> mtd: m25p80: add support of octal mode I/O transfer
>>> spi: nxp-fspi: add octal mode flag bit for octal support
>>> arm64: dts: lx2160a: update fspi node
>>>
>>> arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 ++++
>>> drivers/mtd/devices/m25p80.c | 9 ++++++++-
>>> drivers/mtd/spi-nor/spi-nor.c | 19 ++++++++++++++++---
>>> drivers/spi/spi-mem.c | 9 ++++++++-
>>> drivers/spi/spi-nxp-fspi.c | 4 ++--
>>> drivers/spi/spi.c | 12 ++++++++++--
>>> include/linux/mtd/spi-nor.h | 16 ++++++++++++----
>>> include/linux/spi/spi.h | 4 +++-
>>> 8 files changed, 63 insertions(+), 14 deletions(-)
>>>
>>
>> --
>> Regards
>> Vignesh
On 12/19/2018 12:12 PM, Yogesh Narayan Gaur wrote:
> Add octal read flag for flash mt35xu512aba.
> This flash, mt35xu512aba, is only complaint to SFDP JESD216B and does
> not seem to support newer JESD216C standard that provides auto
> detection of Octal mode capabilities and opcodes. Therefore, this
> capability is manually added using new SPI_NOR_OCTAL_READ flag.
>
> Signed-off-by: Vignesh R <[email protected]>
> Signed-off-by: Yogesh Narayan Gaur <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
> ---
> Changes for v6:
> - Correct S-o-b tag with full author name as 'Yogesh Narayan Gaur'.
> Changes for v5:
> - Modified string 'octo' with 'octal'.
> Changes for v4:
> - None
> Changes for v3:
> - Modified string 'octal' with 'octo'.
> Changes for v2:
> - Incorporated review comments of Boris and Vignesh
>
> drivers/mtd/spi-nor/spi-nor.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index 872d707..53a3bcc 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -1877,7 +1877,8 @@ static const struct flash_info spi_nor_ids[] = {
> /* Micron */
> {
> "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
> - SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES)
> + SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
> + SPI_NOR_4B_OPCODES)
> },
>
> /* PMC */
>
On 12/19/2018 12:12 PM, Yogesh Narayan Gaur wrote:
> - Add opcodes for octal I/O commands
> * Read : 1-1-8 and 1-8-8 protocol
> * Write : 1-1-8 and 1-8-8 protocol
I verified that the above opcodes are compliant with the MT35X Public datasheet.
> * opcodes for 4-byte address mode command
opcodes compliant with jesd216c.
>
> - Entry of macros in _convert_3to4_xxx function
>
> - Add flag specifying flash support octal read commands.
It would be nicer to explain the need of this flag, similar to what you did in
patch's 4/7 commit message.
>
> Signed-off-by: Vignesh R <[email protected]>
> Signed-off-by: Yogesh Narayan Gaur <[email protected]>
Looks good:
Reviewed-by: Tudor Ambarus <[email protected]>
> ---
> Changes for v6:
> - Correct S-o-b tag with full author name as 'Yogesh Narayan Gaur'.
> Changes for v5:
> - Modified string 'octo' with 'octal'.
> Changes for v4:
> - None
> Changes for v3:
> - Modified string 'octal' with 'octo'.
> Changes for v2:
> - Incorporated review comments of Boris and Vignesh
>
> drivers/mtd/spi-nor/spi-nor.c | 16 ++++++++++++++--
> include/linux/mtd/spi-nor.h | 16 ++++++++++++----
> 2 files changed, 26 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index 6e13bbd..872d707 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -68,7 +68,7 @@ enum spi_nor_read_command_index {
> SNOR_CMD_READ_4_4_4,
> SNOR_CMD_READ_1_4_4_DTR,
>
> - /* Octo SPI */
> + /* Octal SPI */
> SNOR_CMD_READ_1_1_8,
> SNOR_CMD_READ_1_8_8,
> SNOR_CMD_READ_8_8_8,
> @@ -85,7 +85,7 @@ enum spi_nor_pp_command_index {
> SNOR_CMD_PP_1_4_4,
> SNOR_CMD_PP_4_4_4,
>
> - /* Octo SPI */
> + /* Octal SPI */
> SNOR_CMD_PP_1_1_8,
> SNOR_CMD_PP_1_8_8,
> SNOR_CMD_PP_8_8_8,
> @@ -278,6 +278,7 @@ struct flash_info {
> #define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
> #define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
> #define USE_CLSR BIT(14) /* use CLSR command */
> +#define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */
>
> /* Part specific fixup hooks. */
> const struct spi_nor_fixups *fixups;
> @@ -398,6 +399,8 @@ static u8 spi_nor_convert_3to4_read(u8 opcode)
> { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
> { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
> { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
> + { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
> + { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
>
> { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
> { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
> @@ -414,6 +417,8 @@ static u8 spi_nor_convert_3to4_program(u8 opcode)
> { SPINOR_OP_PP, SPINOR_OP_PP_4B },
> { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
> { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
> + { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
> + { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
> };
>
> return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
> @@ -3591,6 +3596,13 @@ static int spi_nor_init_params(struct spi_nor *nor,
> SNOR_PROTO_1_1_4);
> }
>
> + if (info->flags & SPI_NOR_OCTAL_READ) {
> + params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
> + spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_8],
> + 0, 8, SPINOR_OP_READ_1_1_8,
> + SNOR_PROTO_1_1_8);
> + }
> +
> /* Page Program settings. */
> params->hwcaps.mask |= SNOR_HWCAPS_PP;
> spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
> diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
> index fa2d89e..2353af8 100644
> --- a/include/linux/mtd/spi-nor.h
> +++ b/include/linux/mtd/spi-nor.h
> @@ -46,9 +46,13 @@
> #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
> #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
> #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
> +#define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
> +#define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
> #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
> #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
> #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
> +#define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */
> +#define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */
> #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
> #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
> #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
> @@ -69,9 +73,13 @@
> #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
> #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
> #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
> +#define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */
> +#define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */
> #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
> #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
> #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
> +#define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */
> +#define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */
> #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
> #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
> #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
> @@ -458,7 +466,7 @@ struct spi_nor_hwcaps {
> /*
> *(Fast) Read capabilities.
> * MUST be ordered by priority: the higher bit position, the higher priority.
> - * As a matter of performances, it is relevant to use Octo SPI protocols first,
> + * As a matter of performances, it is relevant to use Octal SPI protocols first,
> * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
> * (Slow) Read.
> */
> @@ -479,7 +487,7 @@ struct spi_nor_hwcaps {
> #define SNOR_HWCAPS_READ_4_4_4 BIT(9)
> #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
>
> -#define SNOR_HWCPAS_READ_OCTO GENMASK(14, 11)
> +#define SNOR_HWCPAS_READ_OCTAL GENMASK(14, 11)
> #define SNOR_HWCAPS_READ_1_1_8 BIT(11)
> #define SNOR_HWCAPS_READ_1_8_8 BIT(12)
> #define SNOR_HWCAPS_READ_8_8_8 BIT(13)
> @@ -488,7 +496,7 @@ struct spi_nor_hwcaps {
> /*
> * Page Program capabilities.
> * MUST be ordered by priority: the higher bit position, the higher priority.
> - * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
> + * Like (Fast) Read capabilities, Octal/Quad SPI protocols are preferred to the
> * legacy SPI 1-1-1 protocol.
> * Note that Dual Page Programs are not supported because there is no existing
> * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
> @@ -502,7 +510,7 @@ struct spi_nor_hwcaps {
> #define SNOR_HWCAPS_PP_1_4_4 BIT(18)
> #define SNOR_HWCAPS_PP_4_4_4 BIT(19)
>
> -#define SNOR_HWCAPS_PP_OCTO GENMASK(22, 20)
> +#define SNOR_HWCAPS_PP_OCTAL GENMASK(22, 20)
> #define SNOR_HWCAPS_PP_1_1_8 BIT(20)
> #define SNOR_HWCAPS_PP_1_8_8 BIT(21)
> #define SNOR_HWCAPS_PP_8_8_8 BIT(22)
>