Everyone:
This series contains changes I made in order to enable support of PCIE
IP block on i.MX8MQ SoCs.
Changes since [v2], [fixes]:
- Incorporated [patch] introducing drvdata
- i.MX6 PHY operation gating converted to a single patch and to use a
dedicated flag instead of doing explicit variant check
- Kconfig entry changed to use ARM64 && ARCH_MXC
- Dropped FALLTHROUGH annotations
Changes since [v1]:
- Driver changed to use single "fsl,controller-id" property to
distinguish between two intances of PCIE IP block
- All code pertaining to L1SS was dropped to simplify the patch
- Documented additions to DT bindings
Feedback is welcome!
Thanks,
Andrey Smirnov
[patch] https://patchwork.kernel.org/patch/10712261/
[fixes] https://lore.kernel.org/linux-arm-kernel/[email protected]
[v2] https://lore.kernel.org/linux-arm-kernel/[email protected]
[v1] https://lore.kernel.org/linux-arm-kernel/[email protected]/
Andrey Smirnov (3):
PCI: imx6: introduce drvdata
PCI: imx6: Mark PHY functions as i.MX6 specific
PCI: imx6: Add support for i.MX8MQ
.../bindings/pci/fsl,imx6q-pcie.txt | 6 +-
drivers/pci/controller/dwc/Kconfig | 4 +-
drivers/pci/controller/dwc/pci-imx6.c | 150 +++++++++++++++---
3 files changed, 136 insertions(+), 24 deletions(-)
--
2.19.1
PCIE PHY IP block on i.MX7D differs from the one used on i.MX6 family,
so none of the code in current implementation of imx6_setup_phy_mpll() and
imx6_pcie_reset_phy() is applicable.
Tested-by: Trent Piepho <[email protected]>
Signed-off-by: Andrey Smirnov <[email protected]>
Reviewed-by: Lucas Stach <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Chris Healy <[email protected]>
Cc: Lucas Stach <[email protected]>
Cc: Leonard Crestez <[email protected]>
Cc: "A.s. Dong" <[email protected]>
Cc: Richard Zhu <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
drivers/pci/controller/dwc/pci-imx6.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index d50ed69e7a57..caa05104b90b 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -41,8 +41,11 @@ enum imx6_pcie_variants {
IMX7D,
};
+#define IMX6_PCIE_FLAG_IMX6_PHY BIT(0)
+
struct imx6_pcie_drvdata {
enum imx6_pcie_variants variant;
+ u32 flags;
};
struct imx6_pcie {
@@ -256,6 +259,9 @@ static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
{
u32 tmp;
+ if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
+ return;
+
pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
PHY_RX_OVRD_IN_LO_RX_PLL_EN);
@@ -573,6 +579,9 @@ static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie)
int mult, div;
u32 val;
+ if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
+ return 0;
+
switch (phy_rate) {
case 125000000:
/*
@@ -1088,12 +1097,15 @@ static void imx6_pcie_shutdown(struct platform_device *pdev)
static const struct imx6_pcie_drvdata drvdata[] = {
[IMX6Q] = {
.variant = IMX6Q,
+ .flags = IMX6_PCIE_FLAG_IMX6_PHY,
},
[IMX6SX] = {
.variant = IMX6SX,
+ .flags = IMX6_PCIE_FLAG_IMX6_PHY,
},
[IMX6QP] = {
.variant = IMX6QP,
+ .flags = IMX6_PCIE_FLAG_IMX6_PHY,
},
[IMX7D] = {
.variant = IMX7D,
--
2.19.1
Add code needed to support i.MX8MQ variant.
Signed-off-by: Andrey Smirnov <[email protected]>
Reviewed-by: Lucas Stach <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Chris Healy <[email protected]>
Cc: Lucas Stach <[email protected]>
Cc: Leonard Crestez <[email protected]>
Cc: "A.s. Dong" <[email protected]>
Cc: Richard Zhu <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
---
.../bindings/pci/fsl,imx6q-pcie.txt | 6 +-
drivers/pci/controller/dwc/Kconfig | 4 +-
drivers/pci/controller/dwc/pci-imx6.c | 82 ++++++++++++++++++-
3 files changed, 87 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
index d514c1f2365f..1a10c313e8d7 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
@@ -9,6 +9,7 @@ Required properties:
- "fsl,imx6sx-pcie",
- "fsl,imx6qp-pcie"
- "fsl,imx7d-pcie"
+ - "fsl,imx8mq-pcie"
- reg: base address and length of the PCIe controller
- interrupts: A list of interrupt outputs of the controller. Must contain an
entry for each entry in the interrupt-names property.
@@ -45,7 +46,7 @@ Additional required properties for imx6sx-pcie:
PCIE_PHY power domains
- power-domain-names: Must be "pcie", "pcie_phy"
-Additional required properties for imx7d-pcie:
+Additional required properties for imx7d-pcie and imx8mq-pcie:
- power-domains: Must be set to a phandle pointing to PCIE_PHY power domain
- resets: Must contain phandles to PCIe-related reset lines exposed by SRC
IP block
@@ -54,6 +55,9 @@ Additional required properties for imx7d-pcie:
- "apps"
- "turnoff"
+Additional required properties for imx8mq-pcie:
+- fsl,controller-id: Logical ID of a given PCIE controller. PCIE1 is 0, PCIE2 is 1;
+
Example:
pcie@01000000 {
diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
index 6aafec3fad00..83ea318ad989 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -89,8 +89,8 @@ config PCI_EXYNOS
select PCIE_DW_HOST
config PCI_IMX6
- bool "Freescale i.MX6/7 PCIe controller"
- depends on SOC_IMX6Q || SOC_IMX7D || (ARM && COMPILE_TEST)
+ bool "Freescale i.MX6/7/8 PCIe controller"
+ depends on SOC_IMX6Q || SOC_IMX7D || (ARM64 && ARCH_MXC) || ((ARM || ARM64) && COMPILE_TEST)
depends on PCI_MSI_IRQ_DOMAIN
select PCIE_DW_HOST
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index caa05104b90b..d71680920155 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -8,6 +8,7 @@
* Author: Sean Cross <[email protected]>
*/
+#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio.h>
@@ -32,6 +33,11 @@
#include "pcie-designware.h"
+#define IMX8MQ_GPR_PCIE_REF_USE_PAD BIT(9)
+#define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN BIT(10)
+#define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE BIT(11)
+#define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8)
+
#define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
enum imx6_pcie_variants {
@@ -39,6 +45,7 @@ enum imx6_pcie_variants {
IMX6SX,
IMX6QP,
IMX7D,
+ IMX8MQ,
};
#define IMX6_PCIE_FLAG_IMX6_PHY BIT(0)
@@ -57,6 +64,7 @@ struct imx6_pcie {
struct clk *pcie_inbound_axi;
struct clk *pcie;
struct regmap *iomuxc_gpr;
+ u32 controller_id;
struct reset_control *pciephy_reset;
struct reset_control *apps_reset;
struct reset_control *turnoff_reset;
@@ -275,6 +283,7 @@ static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
}
+#ifdef CONFIG_ARM
/* Added for PCI abort handling */
static int imx6q_pcie_abort_handler(unsigned long addr,
unsigned int fsr, struct pt_regs *regs)
@@ -308,6 +317,7 @@ static int imx6q_pcie_abort_handler(unsigned long addr,
return 1;
}
+#endif
static int imx6_pcie_attach_pd(struct device *dev)
{
@@ -352,6 +362,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
switch (imx6_pcie->drvdata->variant) {
case IMX7D:
+ case IMX8MQ:
reset_control_assert(imx6_pcie->pciephy_reset);
reset_control_assert(imx6_pcie->apps_reset);
break;
@@ -390,6 +401,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
{
struct dw_pcie *pci = imx6_pcie->pci;
struct device *dev = pci->dev;
+ unsigned int offset;
int ret = 0;
switch (imx6_pcie->drvdata->variant) {
@@ -420,6 +432,29 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
break;
case IMX7D:
break;
+ case IMX8MQ:
+ switch (imx6_pcie->controller_id) {
+ case 0:
+ offset = IOMUXC_GPR14;
+ break;
+ case 1:
+ offset = IOMUXC_GPR16;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /*
+ * Set the over ride low and enabled
+ * make sure that REF_CLK is turned on.
+ */
+ regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+ IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE,
+ 0);
+ regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+ IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
+ IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
+ break;
}
return ret;
@@ -496,6 +531,9 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
}
switch (imx6_pcie->drvdata->variant) {
+ case IMX8MQ:
+ reset_control_deassert(imx6_pcie->pciephy_reset);
+ break;
case IMX7D:
reset_control_deassert(imx6_pcie->pciephy_reset);
imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie);
@@ -533,7 +571,36 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
{
+
+
+ unsigned int mask, val, offset;
+
+ mask = IMX6Q_GPR12_DEVICE_TYPE;
+ val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT);
+
switch (imx6_pcie->drvdata->variant) {
+ case IMX8MQ:
+ switch (imx6_pcie->controller_id) {
+ case 0:
+ offset = IOMUXC_GPR14;
+ break;
+ case 1:
+ offset = IOMUXC_GPR16;
+ mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE;
+ val = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
+ PCI_EXP_TYPE_ROOT_PORT);
+ break;
+ default:
+ return;
+ }
+ /*
+ * TODO: Currently this code assumes external
+ * oscillator is being used
+ */
+ regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
+ IMX8MQ_GPR_PCIE_REF_USE_PAD,
+ IMX8MQ_GPR_PCIE_REF_USE_PAD);
+ break;
case IMX7D:
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
@@ -569,8 +636,7 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
break;
}
- regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
- IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
+ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val);
}
static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie)
@@ -667,6 +733,7 @@ static void imx6_pcie_ltssm_enable(struct device *dev)
IMX6Q_GPR12_PCIE_CTL_2);
break;
case IMX7D:
+ case IMX8MQ:
reset_control_deassert(imx6_pcie->apps_reset);
break;
}
@@ -954,6 +1021,10 @@ static int imx6_pcie_probe(struct platform_device *pdev)
imx6_pcie->pci = pci;
imx6_pcie->drvdata = of_device_get_match_data(dev);
+ if (of_property_read_u32(node, "fsl,controller-id",
+ &imx6_pcie->controller_id))
+ imx6_pcie->controller_id = 0;
+
dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
if (IS_ERR(pci->dbi_base))
@@ -1006,6 +1077,7 @@ static int imx6_pcie_probe(struct platform_device *pdev)
}
break;
case IMX7D:
+ case IMX8MQ:
imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev,
"pciephy");
if (IS_ERR(imx6_pcie->pciephy_reset)) {
@@ -1110,6 +1182,9 @@ static const struct imx6_pcie_drvdata drvdata[] = {
[IMX7D] = {
.variant = IMX7D,
},
+ [IMX8MQ] = {
+ .variant = IMX8MQ,
+ },
};
static const struct of_device_id imx6_pcie_of_match[] = {
@@ -1117,6 +1192,7 @@ static const struct of_device_id imx6_pcie_of_match[] = {
{ .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], },
{ .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
{ .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], },
+ { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },
{},
};
@@ -1133,6 +1209,7 @@ static struct platform_driver imx6_pcie_driver = {
static int __init imx6_pcie_init(void)
{
+#ifdef CONFIG_ARM
/*
* Since probe() can be deferred we need to make sure that
* hook_fault_code is not called after __init memory is freed
@@ -1142,6 +1219,7 @@ static int __init imx6_pcie_init(void)
*/
hook_fault_code(8, imx6q_pcie_abort_handler, SIGBUS, 0,
"external abort on non-linefetch");
+#endif
return platform_driver_register(&imx6_pcie_driver);
}
--
2.19.1
Introduce driver data struct. This will simplify handling of device
specific differences.
Cc: Bjorn Helgaas <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Chris Healy <[email protected]>
Cc: Lucas Stach <[email protected]>
Cc: Leonard Crestez <[email protected]>
Cc: "A.s. Dong" <[email protected]>
Cc: Richard Zhu <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Stefan Agner <[email protected]>
Reviewed-by: Lucas Stach <[email protected]>
[[email protected] reformatted drvdata, to simplify future diffs]
Signed-off-by: Andrey Smirnov <[email protected]>
---
drivers/pci/controller/dwc/pci-imx6.c | 56 ++++++++++++++++++---------
1 file changed, 37 insertions(+), 19 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 26087b3da590..d50ed69e7a57 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -41,6 +41,10 @@ enum imx6_pcie_variants {
IMX7D,
};
+struct imx6_pcie_drvdata {
+ enum imx6_pcie_variants variant;
+};
+
struct imx6_pcie {
struct dw_pcie *pci;
int reset_gpio;
@@ -53,7 +57,6 @@ struct imx6_pcie {
struct reset_control *pciephy_reset;
struct reset_control *apps_reset;
struct reset_control *turnoff_reset;
- enum imx6_pcie_variants variant;
u32 tx_deemph_gen1;
u32 tx_deemph_gen2_3p5db;
u32 tx_deemph_gen2_6db;
@@ -66,6 +69,7 @@ struct imx6_pcie {
struct device *pd_pcie;
/* power domain for pcie phy */
struct device *pd_pcie_phy;
+ const struct imx6_pcie_drvdata *drvdata;
};
/* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */
@@ -340,7 +344,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
{
struct device *dev = imx6_pcie->pci->dev;
- switch (imx6_pcie->variant) {
+ switch (imx6_pcie->drvdata->variant) {
case IMX7D:
reset_control_assert(imx6_pcie->pciephy_reset);
reset_control_assert(imx6_pcie->apps_reset);
@@ -382,7 +386,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
struct device *dev = pci->dev;
int ret = 0;
- switch (imx6_pcie->variant) {
+ switch (imx6_pcie->drvdata->variant) {
case IMX6SX:
ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
if (ret) {
@@ -485,7 +489,7 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
!imx6_pcie->gpio_active_high);
}
- switch (imx6_pcie->variant) {
+ switch (imx6_pcie->drvdata->variant) {
case IMX7D:
reset_control_deassert(imx6_pcie->pciephy_reset);
imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie);
@@ -523,7 +527,7 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
{
- switch (imx6_pcie->variant) {
+ switch (imx6_pcie->drvdata->variant) {
case IMX7D:
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
@@ -645,7 +649,7 @@ static void imx6_pcie_ltssm_enable(struct device *dev)
{
struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
- switch (imx6_pcie->variant) {
+ switch (imx6_pcie->drvdata->variant) {
case IMX6Q:
case IMX6SX:
case IMX6QP:
@@ -698,7 +702,7 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
tmp |= PORT_LOGIC_SPEED_CHANGE;
dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
- if (imx6_pcie->variant != IMX7D) {
+ if (imx6_pcie->drvdata->variant != IMX7D) {
/*
* On i.MX7, DIRECT_SPEED_CHANGE behaves differently
* from i.MX6 family when no link speed transition
@@ -801,7 +805,7 @@ static void imx6_pcie_ltssm_disable(struct device *dev)
{
struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
- switch (imx6_pcie->variant) {
+ switch (imx6_pcie->drvdata->variant) {
case IMX6SX:
case IMX6QP:
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
@@ -827,7 +831,7 @@ static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie)
}
/* Others poke directly at IOMUXC registers */
- switch (imx6_pcie->variant) {
+ switch (imx6_pcie->drvdata->variant) {
case IMX6SX:
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6SX_GPR12_PCIE_PM_TURN_OFF,
@@ -857,7 +861,7 @@ static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie)
clk_disable_unprepare(imx6_pcie->pcie_phy);
clk_disable_unprepare(imx6_pcie->pcie_bus);
- switch (imx6_pcie->variant) {
+ switch (imx6_pcie->drvdata->variant) {
case IMX6SX:
clk_disable_unprepare(imx6_pcie->pcie_inbound_axi);
break;
@@ -873,8 +877,8 @@ static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie)
static inline bool imx6_pcie_supports_suspend(struct imx6_pcie *imx6_pcie)
{
- return (imx6_pcie->variant == IMX7D ||
- imx6_pcie->variant == IMX6SX);
+ return (imx6_pcie->drvdata->variant == IMX7D ||
+ imx6_pcie->drvdata->variant == IMX6SX);
}
static int imx6_pcie_suspend_noirq(struct device *dev)
@@ -939,8 +943,7 @@ static int imx6_pcie_probe(struct platform_device *pdev)
pci->ops = &dw_pcie_ops;
imx6_pcie->pci = pci;
- imx6_pcie->variant =
- (enum imx6_pcie_variants)of_device_get_match_data(dev);
+ imx6_pcie->drvdata = of_device_get_match_data(dev);
dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
@@ -984,7 +987,7 @@ static int imx6_pcie_probe(struct platform_device *pdev)
return PTR_ERR(imx6_pcie->pcie);
}
- switch (imx6_pcie->variant) {
+ switch (imx6_pcie->drvdata->variant) {
case IMX6SX:
imx6_pcie->pcie_inbound_axi = devm_clk_get(dev,
"pcie_inbound_axi");
@@ -1082,11 +1085,26 @@ static void imx6_pcie_shutdown(struct platform_device *pdev)
imx6_pcie_assert_core_reset(imx6_pcie);
}
+static const struct imx6_pcie_drvdata drvdata[] = {
+ [IMX6Q] = {
+ .variant = IMX6Q,
+ },
+ [IMX6SX] = {
+ .variant = IMX6SX,
+ },
+ [IMX6QP] = {
+ .variant = IMX6QP,
+ },
+ [IMX7D] = {
+ .variant = IMX7D,
+ },
+};
+
static const struct of_device_id imx6_pcie_of_match[] = {
- { .compatible = "fsl,imx6q-pcie", .data = (void *)IMX6Q, },
- { .compatible = "fsl,imx6sx-pcie", .data = (void *)IMX6SX, },
- { .compatible = "fsl,imx6qp-pcie", .data = (void *)IMX6QP, },
- { .compatible = "fsl,imx7d-pcie", .data = (void *)IMX7D, },
+ { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], },
+ { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], },
+ { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
+ { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], },
{},
};
--
2.19.1
On Mon, 2018-12-17 at 20:07 -0800, Andrey Smirnov wrote:
> Add code needed to support i.MX8MQ variant.
> static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
> {
> +
> +
Remove empty lines?
> + unsigned int mask, val, offset;
> +
> + mask = IMX6Q_GPR12_DEVICE_TYPE;
> + val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT);
... snip ...
> - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
> - IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
> + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val);
Maybe setting port type should be a separate function from init_phy?
On Mon, Dec 17, 2018 at 08:07:02PM -0800, Andrey Smirnov wrote:
> Add code needed to support i.MX8MQ variant.
>
> Signed-off-by: Andrey Smirnov <[email protected]>
> Reviewed-by: Lucas Stach <[email protected]>
> Cc: Bjorn Helgaas <[email protected]>
> Cc: Fabio Estevam <[email protected]>
> Cc: Chris Healy <[email protected]>
> Cc: Lucas Stach <[email protected]>
> Cc: Leonard Crestez <[email protected]>
> Cc: "A.s. Dong" <[email protected]>
> Cc: Richard Zhu <[email protected]>
> Cc: Rob Herring <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> ---
> .../bindings/pci/fsl,imx6q-pcie.txt | 6 +-
> drivers/pci/controller/dwc/Kconfig | 4 +-
> drivers/pci/controller/dwc/pci-imx6.c | 82 ++++++++++++++++++-
> 3 files changed, 87 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> index d514c1f2365f..1a10c313e8d7 100644
> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> @@ -9,6 +9,7 @@ Required properties:
> - "fsl,imx6sx-pcie",
> - "fsl,imx6qp-pcie"
> - "fsl,imx7d-pcie"
> + - "fsl,imx8mq-pcie"
> - reg: base address and length of the PCIe controller
> - interrupts: A list of interrupt outputs of the controller. Must contain an
> entry for each entry in the interrupt-names property.
> @@ -45,7 +46,7 @@ Additional required properties for imx6sx-pcie:
> PCIE_PHY power domains
> - power-domain-names: Must be "pcie", "pcie_phy"
>
> -Additional required properties for imx7d-pcie:
> +Additional required properties for imx7d-pcie and imx8mq-pcie:
> - power-domains: Must be set to a phandle pointing to PCIE_PHY power domain
> - resets: Must contain phandles to PCIe-related reset lines exposed by SRC
> IP block
> @@ -54,6 +55,9 @@ Additional required properties for imx7d-pcie:
> - "apps"
> - "turnoff"
>
> +Additional required properties for imx8mq-pcie:
> +- fsl,controller-id: Logical ID of a given PCIE controller. PCIE1 is 0, PCIE2 is 1;
> +
Remove this.
If GPR register offset is what you need, then put that into DT.
Typically, we'd have a property with iomuxc phandle and offset.
Rob
On Tue, Dec 18, 2018 at 1:34 AM Leonard Crestez <[email protected]> wrote:
>
> On Mon, 2018-12-17 at 20:07 -0800, Andrey Smirnov wrote:
> > Add code needed to support i.MX8MQ variant.
>
> > static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
> > {
> > +
> > +
> Remove empty lines?
>
Sure, will do.
> > + unsigned int mask, val, offset;
> > +
> > + mask = IMX6Q_GPR12_DEVICE_TYPE;
> > + val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT);
>
> ... snip ...
>
> > - regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
> > - IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
> > + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val);
>
> Maybe setting port type should be a separate function from init_phy?
Sure, will change in v4.
Thanks,
Andrey Smirnov
On 12/18/2018 5:15 PM, Rob Herring wrote:
> On Mon, Dec 17, 2018 at 08:07:02PM -0800, Andrey Smirnov wrote:
>> Add code needed to support i.MX8MQ variant.
>>
>> Signed-off-by: Andrey Smirnov <[email protected]>
>> Reviewed-by: Lucas Stach <[email protected]>
>> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
>> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
>>
>> +Additional required properties for imx8mq-pcie:
>> +- fsl,controller-id: Logical ID of a given PCIE controller. PCIE1 is 0, PCIE2 is 1;
>> +
>
> Remove this.
>
> If GPR register offset is what you need, then put that into DT.
> Typically, we'd have a property with iomuxc phandle and offset.
This series initially added explicit offsets but I suggested a single
"controller-id" because:
* There are multiple bit and byte offsets
* Other imx8 SOCs also have 2x pcie with other bit/byte offsets
Hiding this behind a compatible string and single "controller-id" seem
preferable to elaborating register maps in dt bindings. It also makes
upgrades simpler: if features are added which use other bits there is no
need to describe them in DT and deal with compatibility headaches.
Link to older thread: https://lkml.org/lkml/2018/11/29/888
It's possible my suggestion was misguided.
On Tue, Dec 18, 2018 at 12:09 PM Leonard Crestez
<[email protected]> wrote:
>
> On 12/18/2018 5:15 PM, Rob Herring wrote:
> > On Mon, Dec 17, 2018 at 08:07:02PM -0800, Andrey Smirnov wrote:
> >> Add code needed to support i.MX8MQ variant.
> >>
> >> Signed-off-by: Andrey Smirnov <[email protected]>
> >> Reviewed-by: Lucas Stach <[email protected]>
>
> >> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> >> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> >>
> >> +Additional required properties for imx8mq-pcie:
> >> +- fsl,controller-id: Logical ID of a given PCIE controller. PCIE1 is 0, PCIE2 is 1;
> >> +
> >
> > Remove this.
> >
> > If GPR register offset is what you need, then put that into DT.
> > Typically, we'd have a property with iomuxc phandle and offset.
>
> This series initially added explicit offsets but I suggested a single
> "controller-id" because:
> * There are multiple bit and byte offsets
> * Other imx8 SOCs also have 2x pcie with other bit/byte offsets
>
> Hiding this behind a compatible string and single "controller-id" seem
> preferable to elaborating register maps in dt bindings. It also makes
> upgrades simpler: if features are added which use other bits there is no
> need to describe them in DT and deal with compatibility headaches.
You already have an id for the controllers: the address. Use that if
you don't want to put the register offsets in DT.
Rob
On Tue, Dec 18, 2018 at 1:10 PM Rob Herring <[email protected]> wrote:
>
> On Tue, Dec 18, 2018 at 12:09 PM Leonard Crestez
> <[email protected]> wrote:
> >
> > On 12/18/2018 5:15 PM, Rob Herring wrote:
> > > On Mon, Dec 17, 2018 at 08:07:02PM -0800, Andrey Smirnov wrote:
> > >> Add code needed to support i.MX8MQ variant.
> > >>
> > >> Signed-off-by: Andrey Smirnov <[email protected]>
> > >> Reviewed-by: Lucas Stach <[email protected]>
> >
> > >> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> > >> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> > >>
> > >> +Additional required properties for imx8mq-pcie:
> > >> +- fsl,controller-id: Logical ID of a given PCIE controller. PCIE1 is 0, PCIE2 is 1;
> > >> +
> > >
> > > Remove this.
> > >
> > > If GPR register offset is what you need, then put that into DT.
> > > Typically, we'd have a property with iomuxc phandle and offset.
> >
> > This series initially added explicit offsets but I suggested a single
> > "controller-id" because:
> > * There are multiple bit and byte offsets
> > * Other imx8 SOCs also have 2x pcie with other bit/byte offsets
> >
> > Hiding this behind a compatible string and single "controller-id" seem
> > preferable to elaborating register maps in dt bindings. It also makes
> > upgrades simpler: if features are added which use other bits there is no
> > need to describe them in DT and deal with compatibility headaches.
>
> You already have an id for the controllers: the address. Use that if
> you don't want to put the register offsets in DT.
>
Lucas, are you on board with this?
Thanks,
Andrey Smirnov
On Wed, 2018-12-19 at 16:47 -0800, Andrey Smirnov wrote:
>
> > > This series initially added explicit offsets but I suggested a single
> > > "controller-id" because:
> > > * There are multiple bit and byte offsets
> > > * Other imx8 SOCs also have 2x pcie with other bit/byte offsets
> > >
> > > Hiding this behind a compatible string and single "controller-id" seem
> > > preferable to elaborating register maps in dt bindings. It also makes
> > > upgrades simpler: if features are added which use other bits there is no
> > > need to describe them in DT and deal with compatibility headaches.
> >
> > You already have an id for the controllers: the address. Use that if
> > you don't want to put the register offsets in DT.
> >
>
> Lucas, are you on board with this?
Does address here mean the address from the controller's reg property?
How do you map that address to the controller's index? A giant table
of every soc so the soc type plus controller register address pair than
can be looked up in the driver?
I.e., on iMX8MQ the controller at 0x33800000 is controller 0 and so on
for every possible SoC address combination?
Not really a fan of that.
The situation here is that some registers for these controllers are
interleaved, right? I.e., there's one register somewhere where bit 0
means enable controller 0 and bit 1 means enable controller 1 and so
on.
Isn't cell-index already the standard device tree property for this
kind of setup?
I know cell-index was historically also (ab)used in an attempt to
provide a fixed kernel device enumeration order, something now handled
better by chosen node aliases.
On 12/20/2018 3:22 AM, Trent Piepho wrote:
> On Wed, 2018-12-19 at 16:47 -0800, Andrey Smirnov wrote:
>>>> This series initially added explicit offsets but I suggested a single
>>>> "controller-id" because:
>>>> * There are multiple bit and byte offsets
>>>> * Other imx8 SOCs also have 2x pcie with other bit/byte offsets
>>>>
>>>> Hiding this behind a compatible string and single "controller-id" seem
>>>> preferable to elaborating register maps in dt bindings. It also makes
>>>> upgrades simpler: if features are added which use other bits there is no
>>>> need to describe them in DT and deal with compatibility headaches.
>>>
>>> You already have an id for the controllers: the address. Use that if
>>> you don't want to put the register offsets in DT.
>>
>> Lucas, are you on board with this?
>
> Does address here mean the address from the controller's reg property?
>
> How do you map that address to the controller's index?
I guess you could have a constant for the address of the first
controller and then substract. But hardcoding any sort of physical
address feels wrong with DT.
> The situation here is that some registers for these controllers are
> interleaved, right? I.e., there's one register somewhere where bit 0
> means enable controller 0 and bit 1 means enable controller 1 and so
> on.
>
> Isn't cell-index already the standard device tree property for this
> kind of setup?
Look at how this cell-index property is documented in other bindings it
seems to be an excellent fit: just rename controller-id to cell-index.
On Wed, Dec 19, 2018 at 7:22 PM Trent Piepho <[email protected]> wrote:
>
> On Wed, 2018-12-19 at 16:47 -0800, Andrey Smirnov wrote:
> >
> > > > This series initially added explicit offsets but I suggested a single
> > > > "controller-id" because:
> > > > * There are multiple bit and byte offsets
> > > > * Other imx8 SOCs also have 2x pcie with other bit/byte offsets
> > > >
> > > > Hiding this behind a compatible string and single "controller-id" seem
> > > > preferable to elaborating register maps in dt bindings. It also makes
> > > > upgrades simpler: if features are added which use other bits there is no
> > > > need to describe them in DT and deal with compatibility headaches.
> > >
> > > You already have an id for the controllers: the address. Use that if
> > > you don't want to put the register offsets in DT.
> > >
> >
> > Lucas, are you on board with this?
>
> Does address here mean the address from the controller's reg property?
Yes.
> How do you map that address to the controller's index? A giant table
> of every soc so the soc type plus controller register address pair than
> can be looked up in the driver?
You only need the 2-Nth instance addresses. A non-matching address can
be instance 0.
> I.e., on iMX8MQ the controller at 0x33800000 is controller 0 and so on
> for every possible SoC address combination?
>
> Not really a fan of that.
Well, this was not my first suggestion.
> The situation here is that some registers for these controllers are
> interleaved, right? I.e., there's one register somewhere where bit 0
> means enable controller 0 and bit 1 means enable controller 1 and so
> on.
So? The only difference here is an additional mapping step.
> Isn't cell-index already the standard device tree property for this
> kind of setup?
>
> I know cell-index was historically also (ab)used in an attempt to
> provide a fixed kernel device enumeration order, something now handled
> better by chosen node aliases.
Don't use cell-index. Consider it a deprecated relic from OF that is
not used on FDT (though there probably are some cases it did get
used).
Rob
On Tue, Dec 18, 2018 at 12:09 PM Leonard Crestez
<[email protected]> wrote:
>
> On 12/18/2018 5:15 PM, Rob Herring wrote:
> > On Mon, Dec 17, 2018 at 08:07:02PM -0800, Andrey Smirnov wrote:
> >> Add code needed to support i.MX8MQ variant.
> >>
> >> Signed-off-by: Andrey Smirnov <[email protected]>
> >> Reviewed-by: Lucas Stach <[email protected]>
>
> >> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> >> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
> >>
> >> +Additional required properties for imx8mq-pcie:
> >> +- fsl,controller-id: Logical ID of a given PCIE controller. PCIE1 is 0, PCIE2 is 1;
> >> +
> >
> > Remove this.
> >
> > If GPR register offset is what you need, then put that into DT.
> > Typically, we'd have a property with iomuxc phandle and offset.
>
> This series initially added explicit offsets but I suggested a single
> "controller-id" because:
> * There are multiple bit and byte offsets
> * Other imx8 SOCs also have 2x pcie with other bit/byte offsets
>
> Hiding this behind a compatible string and single "controller-id" seem
> preferable to elaborating register maps in dt bindings. It also makes
> upgrades simpler: if features are added which use other bits there is no
> need to describe them in DT and deal with compatibility headaches.
You don't have to describe all bit and byte offsets. Once you know 1,
you can derive all the others. In fact, it doesn't have to be a
register field at all, just provide whatever identifier you need:
<$syscon 0>
and
<&syscon 1>
Rob