2019-01-24 06:19:28

by CK Hu (胡俊光)

Subject: Re: [PATCH V2,4/8] drm/mediatek: fix the rate and divder of hdmi phy for MT2701

On Fri, 2019-01-18 at 20:59 +0800, Wangyan Wang wrote:
> From: chunhui dai <[email protected]>

Describe something here.

>
> Fixes: 0fc721b2968e ("drm/mediatek: add hdmi driver for MT2701 and MT7623")
> Signed-off-by: chunhui dai <[email protected]>

Any one who pass a patch should sign off it.

Regards,
CK

> ---
> drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> index 43bc058d5528..88dd9e812ca0 100644
> --- a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> +++ b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> @@ -114,8 +114,8 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
>
> if (rate <= 64000000)
> pos_div = 3;
> - else if (rate <= 12800000)
> - pos_div = 1;
> + else if (rate <= 128000000)
> + pos_div = 2;
> else
> pos_div = 1;
>

2019-01-25 02:29:20

by wangyan wang

Subject: Re: [PATCH V2,4/8] drm/mediatek: fix the rate and divder of hdmi phy for MT2701

Dear CK,

OK,I will modify according your comments in V3.

Best Regards
Wangyan Wang


On Thu, 2019-01-24 at 14:17 +0800, CK Hu wrote:
> On Fri, 2019-01-18 at 20:59 +0800, Wangyan Wang wrote:
> > From: chunhui dai <[email protected]>
>
> Describe something here.
>
> >
> > Fixes: 0fc721b2968e ("drm/mediatek: add hdmi driver for MT2701 and MT7623")
> > Signed-off-by: chunhui dai <[email protected]>
>
> Any one who pass a patch should sign off it.
>
> Regards,
> CK
>
> > ---
> > drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> > index 43bc058d5528..88dd9e812ca0 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> > @@ -114,8 +114,8 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> >
> > if (rate <= 64000000)
> > pos_div = 3;
> > - else if (rate <= 12800000)
> > - pos_div = 1;
> > + else if (rate <= 128000000)
> > + pos_div = 2;
> > else
> > pos_div = 1;
> >
>
>