Hi folks,
This series adds support for the Mali450 MP4 GPU found on the
hi6220 SoC from HiSilicon. It has been tested with the out
of tree lima drm/mesa driver hosted on freedesktop.org gitlab,
and validated using Weston and kmscube.
regards,
Peter.
Peter Griffin (6):
dt-bindings: gpu: mali-utgard: add hisilicon,hi6220-mali compatible
dt-bindings: reset: hisilicon: Update compatible documentation
arm64: dts: hisilicon: Add Mali-450 MP4 GPU DT entry
reset: hi6220: Add support for AO reset controller
dt-bindings: reset: hisilicon: Add ao reset controller
clk: hi6220: use CLK_OF_DECLARE_DRIVER
.../devicetree/bindings/gpu/arm,mali-utgard.txt | 5 +++
.../bindings/reset/hisilicon,hi6220-reset.txt | 1 +
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 38 ++++++++++++++++
drivers/clk/hisilicon/clk-hi6220.c | 2 +-
drivers/reset/hisilicon/hi6220_reset.c | 51 +++++++++++++++++++++-
include/dt-bindings/reset/hisi,hi6220-resets.h | 7 +++
6 files changed, 102 insertions(+), 2 deletions(-)
--
2.7.4
hi6220 has a Mali450 MP4 so lets add it into the DT.
Signed-off-by: Peter Griffin <[email protected]>
---
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 38 +++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 108e2a4..2072b63 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -260,6 +260,7 @@
compatible = "hisilicon,hi6220-aoctrl", "syscon";
reg = <0x0 0xf7800000 0x0 0x2000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
sys_ctrl: sys_ctrl@f7030000 {
@@ -1021,6 +1022,43 @@
clock-names = "apb_pclk";
cpu = <&cpu7>;
};
+
+ mali: gpu@f4080000 {
+ compatible = "hisilicon,hi6220-mali", "arm,mali-450";
+ reg = <0x0 0xf4080000 0x0 0x00040000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1",
+ "pp2",
+ "ppmmu2",
+ "pp3",
+ "ppmmu3";
+ clocks = <&media_ctrl HI6220_G3D_CLK>,
+ <&media_ctrl HI6220_G3D_PCLK>;
+ clock-names = "core", "bus";
+ assigned-clocks = <&media_ctrl HI6220_G3D_CLK>,
+ <&media_ctrl HI6220_G3D_PCLK>;
+ assigned-clock-rates = <500000000>, <144000000>;
+ reset-names = "ao_g3d", "media_g3d";
+ resets = <&ao_ctrl AO_G3D>, <&media_ctrl MEDIA_G3D>;
+ };
};
};
--
2.7.4
As now we also need to probe in the reset driver as well.
Signed-off-by: Peter Griffin <[email protected]>
---
drivers/clk/hisilicon/clk-hi6220.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c
index a87809d..952ffe2 100644
--- a/drivers/clk/hisilicon/clk-hi6220.c
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -89,7 +89,7 @@ static void __init hi6220_clk_ao_init(struct device_node *np)
hisi_clk_register_gate_sep(hi6220_separated_gate_clks_ao,
ARRAY_SIZE(hi6220_separated_gate_clks_ao), clk_data_ao);
}
-CLK_OF_DECLARE(hi6220_clk_ao, "hisilicon,hi6220-aoctrl", hi6220_clk_ao_init);
+CLK_OF_DECLARE_DRIVER(hi6220_clk_ao, "hisilicon,hi6220-aoctrl", hi6220_clk_ao_init);
/* clocks in sysctrl */
--
2.7.4
This is required to bring Mali450 gpu out of reset.
Signed-off-by: Peter Griffin <[email protected]>
---
include/dt-bindings/reset/hisi,hi6220-resets.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/include/dt-bindings/reset/hisi,hi6220-resets.h b/include/dt-bindings/reset/hisi,hi6220-resets.h
index e7c362a8..63aff7d 100644
--- a/include/dt-bindings/reset/hisi,hi6220-resets.h
+++ b/include/dt-bindings/reset/hisi,hi6220-resets.h
@@ -73,4 +73,11 @@
#define MEDIA_MMU 6
#define MEDIA_XG2RAM1 7
+#define AO_G3D 1
+#define AO_CODECISP 2
+#define AO_MCPU 4
+#define AO_BBPHARQMEM 5
+#define AO_HIFI 8
+#define AO_ACPUSCUL2C 12
+
#endif /*_DT_BINDINGS_RESET_CONTROLLER_HI6220*/
--
2.7.4
This is required to bring Mali450 gpu out of reset.
Signed-off-by: Peter Griffin <[email protected]>
---
drivers/reset/hisilicon/hi6220_reset.c | 51 +++++++++++++++++++++++++++++++++-
1 file changed, 50 insertions(+), 1 deletion(-)
diff --git a/drivers/reset/hisilicon/hi6220_reset.c b/drivers/reset/hisilicon/hi6220_reset.c
index d5e5229..0cd5f92 100644
--- a/drivers/reset/hisilicon/hi6220_reset.c
+++ b/drivers/reset/hisilicon/hi6220_reset.c
@@ -36,6 +36,7 @@
enum hi6220_reset_ctrl_type {
PERIPHERAL,
MEDIA,
+ AO,
};
struct hi6220_reset_data {
@@ -95,6 +96,47 @@ static const struct reset_control_ops hi6220_media_reset_ops = {
.deassert = hi6220_media_deassert,
};
+#define AO_SCTRL_SC_PW_CLKEN0 0x800
+#define AO_SCTRL_SC_PW_CLKDIS0 0x804
+
+#define AO_SCTRL_SC_PW_RSTEN0 0x810
+#define AO_SCTRL_SC_PW_RSTDIS0 0x814
+
+#define AO_SCTRL_SC_PW_ISOEN0 0x820
+#define AO_SCTRL_SC_PW_ISODIS0 0x824
+#define AO_MAX_INDEX 12
+
+static int hi6220_ao_assert(struct reset_controller_dev *rc_dev,
+ unsigned long idx)
+{
+ struct hi6220_reset_data *data = to_reset_data(rc_dev);
+ struct regmap *regmap = data->regmap;
+ int ret;
+
+ ret = regmap_write(regmap, AO_SCTRL_SC_PW_RSTEN0, BIT(idx));
+ ret |= regmap_write(regmap, AO_SCTRL_SC_PW_ISOEN0, BIT(idx));
+ ret |= regmap_write(regmap, AO_SCTRL_SC_PW_CLKDIS0, BIT(idx));
+ return ret;
+}
+
+static int hi6220_ao_deassert(struct reset_controller_dev *rc_dev,
+ unsigned long idx)
+{
+ struct hi6220_reset_data *data = to_reset_data(rc_dev);
+ struct regmap *regmap = data->regmap;
+ int ret;
+
+ ret = regmap_write(regmap, AO_SCTRL_SC_PW_RSTDIS0, BIT(idx));
+ ret |= regmap_write(regmap, AO_SCTRL_SC_PW_ISODIS0, BIT(idx));
+ ret |= regmap_write(regmap, AO_SCTRL_SC_PW_CLKEN0, BIT(idx));
+ return ret;
+}
+
+static const struct reset_control_ops hi6220_ao_reset_ops = {
+ .assert = hi6220_ao_assert,
+ .deassert = hi6220_ao_deassert,
+};
+
static int hi6220_reset_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
@@ -120,9 +162,12 @@ static int hi6220_reset_probe(struct platform_device *pdev)
if (type == MEDIA) {
data->rc_dev.ops = &hi6220_media_reset_ops;
data->rc_dev.nr_resets = MEDIA_MAX_INDEX;
- } else {
+ } else if (type == PERIPHERAL) {
data->rc_dev.ops = &hi6220_peripheral_reset_ops;
data->rc_dev.nr_resets = PERIPH_MAX_INDEX;
+ } else {
+ data->rc_dev.ops = &hi6220_ao_reset_ops;
+ data->rc_dev.nr_resets = AO_MAX_INDEX;
}
return reset_controller_register(&data->rc_dev);
@@ -137,6 +182,10 @@ static const struct of_device_id hi6220_reset_match[] = {
.compatible = "hisilicon,hi6220-mediactrl",
.data = (void *)MEDIA,
},
+ {
+ .compatible = "hisilicon,hi6220-aoctrl",
+ .data = (void *)AO,
+ },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, hi6220_reset_match);
--
2.7.4
The Hisilicon hi6220 uses a Mali-450MP4 with 4 PPs, so add
a compatible for it.
Signed-off-by: Peter Griffin <[email protected]>
---
Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
index ae63f09..936a20a 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt
@@ -23,6 +23,7 @@ Required properties:
+ rockchip,rk3228-mali
+ rockchip,rk3328-mali
+ stericsson,db8500-mali
+ + hisilicon,hi6220-mali
- reg: Physical base address and length of the GPU registers
@@ -97,6 +98,10 @@ to specify one more vendor-specific compatible, among:
* interrupt-names and interrupts:
+ combined: combined interrupt of all of the above lines
+ - hisilicon,hi6220-mali
+ Required properties:
+ * resets: phandles to the reset lines for the GPU
+
Example:
mali: gpu@1c40000 {
--
2.7.4
The reset driver now supports the ao reset controller, so update the
documentation to match.
Signed-off-by: Peter Griffin <[email protected]>
---
Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
index c25da39..ea0a6a9 100644
--- a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
+++ b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
@@ -11,6 +11,7 @@ Required properties:
- compatible: should be one of the following:
- "hisilicon,hi6220-sysctrl", "syscon" : For peripheral reset controller.
- "hisilicon,hi6220-mediactrl", "syscon" : For media reset controller.
+ - "hisilicon,hi6220-aoctrl", "syscon" : For ao reset controller.
- reg: should be register base and length as documented in the
datasheet
- #reset-cells: 1, see below
--
2.7.4
Quoting Peter Griffin (2019-03-18 12:38:51)
> As now we also need to probe in the reset driver as well.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---
> drivers/clk/hisilicon/clk-hi6220.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Doesn't this need to be squashed with the reset driver bits so we don't
have a bisection hole?
>
> diff --git a/drivers/clk/hisilicon/clk-hi6220.c b/drivers/clk/hisilicon/clk-hi6220.c
> index a87809d..952ffe2 100644
> --- a/drivers/clk/hisilicon/clk-hi6220.c
> +++ b/drivers/clk/hisilicon/clk-hi6220.c
> @@ -89,7 +89,7 @@ static void __init hi6220_clk_ao_init(struct device_node *np)
> hisi_clk_register_gate_sep(hi6220_separated_gate_clks_ao,
> ARRAY_SIZE(hi6220_separated_gate_clks_ao), clk_data_ao);
> }
> -CLK_OF_DECLARE(hi6220_clk_ao, "hisilicon,hi6220-aoctrl", hi6220_clk_ao_init);
> +CLK_OF_DECLARE_DRIVER(hi6220_clk_ao, "hisilicon,hi6220-aoctrl", hi6220_clk_ao_init);
Can you also add a comment indicating why/what is the other driver that
is probing the same device node?
Hi Peter,
On Mon, 2019-03-18 at 19:38 +0000, Peter Griffin wrote:
> This is required to bring Mali450 gpu out of reset.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---
> drivers/reset/hisilicon/hi6220_reset.c | 51 +++++++++++++++++++++++++++++++++-
> 1 file changed, 50 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/reset/hisilicon/hi6220_reset.c b/drivers/reset/hisilicon/hi6220_reset.c
> index d5e5229..0cd5f92 100644
> --- a/drivers/reset/hisilicon/hi6220_reset.c
> +++ b/drivers/reset/hisilicon/hi6220_reset.c
> @@ -36,6 +36,7 @@
> enum hi6220_reset_ctrl_type {
> PERIPHERAL,
> MEDIA,
> + AO,
> };
>
> struct hi6220_reset_data {
> @@ -95,6 +96,47 @@ static const struct reset_control_ops hi6220_media_reset_ops = {
> .deassert = hi6220_media_deassert,
> };
>
> +#define AO_SCTRL_SC_PW_CLKEN0 0x800
> +#define AO_SCTRL_SC_PW_CLKDIS0 0x804
> +
> +#define AO_SCTRL_SC_PW_RSTEN0 0x810
> +#define AO_SCTRL_SC_PW_RSTDIS0 0x814
> +
> +#define AO_SCTRL_SC_PW_ISOEN0 0x820
> +#define AO_SCTRL_SC_PW_ISODIS0 0x824
> +#define AO_MAX_INDEX 12
> +
> +static int hi6220_ao_assert(struct reset_controller_dev *rc_dev,
> + unsigned long idx)
> +{
> + struct hi6220_reset_data *data = to_reset_data(rc_dev);
> + struct regmap *regmap = data->regmap;
> + int ret;
> +
> + ret = regmap_write(regmap, AO_SCTRL_SC_PW_RSTEN0, BIT(idx));
> + ret |= regmap_write(regmap, AO_SCTRL_SC_PW_ISOEN0, BIT(idx));
> + ret |= regmap_write(regmap, AO_SCTRL_SC_PW_CLKDIS0, BIT(idx));
What if two regmap_writes return a different error code? Better check
for ret and return individually. Also, no need to issue two more writes
if the first one failed.
> + return ret;
> +}
> +
> +static int hi6220_ao_deassert(struct reset_controller_dev *rc_dev,
> + unsigned long idx)
> +{
> + struct hi6220_reset_data *data = to_reset_data(rc_dev);
> + struct regmap *regmap = data->regmap;
> + int ret;
> +
> + ret = regmap_write(regmap, AO_SCTRL_SC_PW_RSTDIS0, BIT(idx));
> + ret |= regmap_write(regmap, AO_SCTRL_SC_PW_ISODIS0, BIT(idx));
> + ret |= regmap_write(regmap, AO_SCTRL_SC_PW_CLKEN0, BIT(idx));
Same as above. Otherwise this looks fine. With this fixed, I could pick
up patches 2, 4, and 5.
regards
Philipp
On Mon, 18 Mar 2019 19:38:50 +0000, Peter Griffin wrote:
> This is required to bring Mali450 gpu out of reset.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---
> include/dt-bindings/reset/hisi,hi6220-resets.h | 7 +++++++
> 1 file changed, 7 insertions(+)
>
Reviewed-by: Rob Herring <[email protected]>
On Mon, 18 Mar 2019 19:38:46 +0000, Peter Griffin wrote:
> The Hisilicon hi6220 uses a Mali-450MP4 with 4 PPs, so add
> a compatible for it.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---
> Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 5 +++++
> 1 file changed, 5 insertions(+)
>
Reviewed-by: Rob Herring <[email protected]>
On Mon, 18 Mar 2019 19:38:47 +0000, Peter Griffin wrote:
> The reset driver now supports the ao reset controller, so update the
> documentation to match.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---
> Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Rob Herring <[email protected]>