From: Yogesh Gaur <[email protected]>
Increase size of cmux_to_group array, to accomdate entry of
-1 termination.
Added -1, terminated, entry for 4080_cmux_grpX.
Signed-off-by: Yogesh Gaur <[email protected]>
Signed-off-by: Vabhav Sharma <[email protected]>
Acked-by: Scott Wood <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
---
drivers/clk/clk-qoriq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 1212a9b..f6606cf 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -79,7 +79,7 @@ struct clockgen_chipinfo {
const struct clockgen_muxinfo *cmux_groups[2];
const struct clockgen_muxinfo *hwaccel[NUM_HWACCEL];
void (*init_periph)(struct clockgen *cg);
- int cmux_to_group[NUM_CMUX]; /* -1 terminates if fewer than NUM_CMUX */
+ int cmux_to_group[NUM_CMUX+1]; /* array should be -1 terminated */
u32 pll_mask; /* 1 << n bit set if PLL n is valid */
u32 flags; /* CG_xxx */
};
@@ -601,7 +601,7 @@ static const struct clockgen_chipinfo chipinfo[] = {
&p4080_cmux_grp1, &p4080_cmux_grp2
},
.cmux_to_group = {
- 0, 0, 0, 0, 1, 1, 1, 1
+ 0, 0, 0, 0, 1, 1, 1, 1, -1
},
.pll_mask = 0x1f,
},
--
2.7.4
Your subject should be "clk: qoriq: Increase array size of cmux_to_group"
Quoting Vabhav Sharma (2019-04-24 07:50:13)
> From: Yogesh Gaur <[email protected]>
>
> Increase size of cmux_to_group array, to accomdate entry of
> -1 termination.
>
> Added -1, terminated, entry for 4080_cmux_grpX.
>
> Signed-off-by: Yogesh Gaur <[email protected]>
> Signed-off-by: Vabhav Sharma <[email protected]>
> Acked-by: Scott Wood <[email protected]>
> Acked-by: Stephen Boyd <[email protected]>
> ---
> drivers/clk/clk-qoriq.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
> index 1212a9b..f6606cf 100644
> --- a/drivers/clk/clk-qoriq.c
> +++ b/drivers/clk/clk-qoriq.c
> @@ -79,7 +79,7 @@ struct clockgen_chipinfo {
> const struct clockgen_muxinfo *cmux_groups[2];
> const struct clockgen_muxinfo *hwaccel[NUM_HWACCEL];
> void (*init_periph)(struct clockgen *cg);
> - int cmux_to_group[NUM_CMUX]; /* -1 terminates if fewer than NUM_CMUX */
> + int cmux_to_group[NUM_CMUX+1]; /* array should be -1 terminated */
Please put space around that +.
> u32 pll_mask; /* 1 << n bit set if PLL n is valid */
> u32 flags; /* CG_xxx */
> };
> @@ -601,7 +601,7 @@ static const struct clockgen_chipinfo chipinfo[] = {
> &p4080_cmux_grp1, &p4080_cmux_grp2
> },
> .cmux_to_group = {
> - 0, 0, 0, 0, 1, 1, 1, 1
> + 0, 0, 0, 0, 1, 1, 1, 1, -1
> },
> .pll_mask = 0x1f,
> },
Did you want this patch to go through clk tree? I seem to have acked it,
which I don't remember. Usually when I ack something I assume it's going
through some other tree.
> -----Original Message-----
> From: Stephen Boyd <[email protected]>
> Sent: Thursday, April 25, 2019 4:51 AM
> To: [email protected]; [email protected]; Vabhav Sharma
> <[email protected]>
> Cc: [email protected]; Yogesh Narayan Gaur
> <[email protected]>; Vabhav Sharma
> <[email protected]>
> Subject: [EXT] Re: [PATCH] arm64: drivers: clk: qoriq: increase array size of
> cmux_to_group
>
> Caution: EXT Email
>
> Your subject should be "clk: qoriq: Increase array size of cmux_to_group"
Ok, I will update it
>
> Quoting Vabhav Sharma (2019-04-24 07:50:13)
> > From: Yogesh Gaur <[email protected]>
> >
> > Increase size of cmux_to_group array, to accomdate entry of
> > -1 termination.
> >
> > Added -1, terminated, entry for 4080_cmux_grpX.
> >
> > Signed-off-by: Yogesh Gaur <[email protected]>
> > Signed-off-by: Vabhav Sharma <[email protected]>
> > Acked-by: Scott Wood <[email protected]>
> > Acked-by: Stephen Boyd <[email protected]>
> > ---
> > drivers/clk/clk-qoriq.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index
> > 1212a9b..f6606cf 100644
> > --- a/drivers/clk/clk-qoriq.c
> > +++ b/drivers/clk/clk-qoriq.c
> > @@ -79,7 +79,7 @@ struct clockgen_chipinfo {
> > const struct clockgen_muxinfo *cmux_groups[2];
> > const struct clockgen_muxinfo *hwaccel[NUM_HWACCEL];
> > void (*init_periph)(struct clockgen *cg);
> > - int cmux_to_group[NUM_CMUX]; /* -1 terminates if fewer than
> NUM_CMUX */
> > + int cmux_to_group[NUM_CMUX+1]; /* array should be -1
> > + terminated */
>
> Please put space around that +.
Ok, I will update it
>
> > u32 pll_mask; /* 1 << n bit set if PLL n is valid */
> > u32 flags; /* CG_xxx */
> > };
> > @@ -601,7 +601,7 @@ static const struct clockgen_chipinfo chipinfo[] = {
> > &p4080_cmux_grp1, &p4080_cmux_grp2
> > },
> > .cmux_to_group = {
> > - 0, 0, 0, 0, 1, 1, 1, 1
> > + 0, 0, 0, 0, 1, 1, 1, 1, -1
> > },
> > .pll_mask = 0x1f,
> > },
>
> Did you want this patch to go through clk tree? I seem to have acked it,
> which I don't remember. Usually when I ack something I assume it's going
> through some other tree.
Yes , please help to merge it
This Patch was sent earlier as a part of adding NXP LX2160A SoC support, reviewed and acked but dropped during merge window. So I break the clock patches into two patch to let clk maintainers merge it.