The system counter block guide states that the base clock is
internally divided by 3 before use, that means the clock input of
system counter defined in DT should be base clock which is normally
from OSC, and then internally divided by 3 before use.
Signed-off-by: Anson Huang <[email protected]>
---
No changes.
---
drivers/clocksource/timer-imx-sysctr.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/clocksource/timer-imx-sysctr.c b/drivers/clocksource/timer-imx-sysctr.c
index fd7d680..b7c80a3 100644
--- a/drivers/clocksource/timer-imx-sysctr.c
+++ b/drivers/clocksource/timer-imx-sysctr.c
@@ -20,6 +20,8 @@
#define SYS_CTR_EN 0x1
#define SYS_CTR_IRQ_MASK 0x2
+#define SYS_CTR_CLK_DIV 0x3
+
static void __iomem *sys_ctr_base;
static u32 cmpcr;
@@ -134,6 +136,9 @@ static int __init sysctr_timer_init(struct device_node *np)
if (ret)
return ret;
+ /* system counter clock is divided by 3 internally */
+ to_sysctr.of_clk.rate /= SYS_CTR_CLK_DIV;
+
sys_ctr_base = timer_of_base(&to_sysctr);
cmpcr = readl(sys_ctr_base + CMPCR);
cmpcr &= ~SYS_CTR_EN;
--
2.7.4
Add i.MX8MQ system counter node to enable timer-imx-sysctr
broadcast timer driver.
Signed-off-by: Anson Huang <[email protected]>
---
No changes.
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 7c68df6..4fdd60f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -644,6 +644,14 @@
#pwm-cells = <2>;
status = "disabled";
};
+
+ system_counter: timer@306a0000 {
+ compatible = "nxp,sysctr-timer";
+ reg = <0x306a0000 0x20000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc_25m>;
+ clock-names = "per";
+ };
};
bus@30800000 { /* AIPS3 */
--
2.7.4
Enable i.MX8MM cpu-idle using generic ARM cpu-idle driver, 2 states
are supported, details as below:
root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state0/name
WFI
root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state0/usage
3973
root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state1/name
cpu-pd-wait
root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state1/usage
6647
Signed-off-by: Anson Huang <[email protected]>
---
Changes since V5:
- improve state1 idle name to better match PSCI doc;
- remove wakeup-latency-us property as it is NOT necessary when entry-latency-us/exit-latency-us
exist.
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 94433c53..9b2dc12 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -44,6 +44,19 @@
#address-cells = <1>;
#size-cells = <0>;
+ idle-states {
+ entry-method = "psci";
+
+ cpu_pd_wait: cpu-pd-wait {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010033>;
+ local-timer-stop;
+ entry-latency-us = <1000>;
+ exit-latency-us = <700>;
+ min-residency-us = <2700>;
+ };
+ };
+
A53_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
@@ -56,6 +69,7 @@
nvmem-cells = <&cpu_speed_grade>;
nvmem-cell-names = "speed_grade";
#cooling-cells = <2>;
+ cpu-idle-states = <&cpu_pd_wait>;
};
A53_1: cpu@1 {
@@ -68,6 +82,7 @@
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
+ cpu-idle-states = <&cpu_pd_wait>;
};
A53_2: cpu@2 {
@@ -80,6 +95,7 @@
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
+ cpu-idle-states = <&cpu_pd_wait>;
};
A53_3: cpu@3 {
@@ -92,6 +108,7 @@
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
+ cpu-idle-states = <&cpu_pd_wait>;
};
A53_L2: l2-cache0 {
--
2.7.4
Add i.MX8MM system counter node to enable timer-imx-sysctr
broadcast timer driver.
Signed-off-by: Anson Huang <[email protected]>
---
No changes.
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index ef66bb5..94433c53 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -572,6 +572,14 @@
#pwm-cells = <2>;
status = "disabled";
};
+
+ system_counter: timer@306a0000 {
+ compatible = "nxp,sysctr-timer";
+ reg = <0x306a0000 0x20000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc_24m>;
+ clock-names = "per";
+ };
};
aips3: bus@30800000 {
--
2.7.4
On 16/08/2019 02:38, Anson Huang wrote:
> Enable i.MX8MM cpu-idle using generic ARM cpu-idle driver, 2 states
> are supported, details as below:
>
> root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state0/name
> WFI
> root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state0/usage
> 3973
> root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state1/name
> cpu-pd-wait
> root@imx8mmevk:~# cat /sys/devices/system/cpu/cpu0/cpuidle/state1/usage
> 6647
>
> Signed-off-by: Anson Huang <[email protected]>
Hi Anson,
I've applied the patches 1-3 but this one does not apply.
You can either respin it against tip/timers/core and take it through
Shawn's tree. If the later, you can add my Acked-by.
-- Daniel
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
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Hi, Daniel/Shawn
> On 16/08/2019 02:38, Anson Huang wrote:
> > Enable i.MX8MM cpu-idle using generic ARM cpu-idle driver, 2 states
> > are supported, details as below:
> >
> > root@imx8mmevk:~# cat
> /sys/devices/system/cpu/cpu0/cpuidle/state0/name
> > WFI
> > root@imx8mmevk:~# cat
> > /sys/devices/system/cpu/cpu0/cpuidle/state0/usage
> > 3973
> > root@imx8mmevk:~# cat
> /sys/devices/system/cpu/cpu0/cpuidle/state1/name
> > cpu-pd-wait
> > root@imx8mmevk:~# cat
> > /sys/devices/system/cpu/cpu0/cpuidle/state1/usage
> > 6647
> >
> > Signed-off-by: Anson Huang <[email protected]>
>
> Hi Anson,
>
> I've applied the patches 1-3 but this one does not apply.
Thanks.
>
> You can either respin it against tip/timers/core and take it through Shawn's
> tree. If the later, you can add my Acked-by.
Hi, Shawn
Can you take this patch and add below Acked-by? It should can be applied to your tree directly.
Acked-by: Daniel Lezcano <[email protected]>
Thanks,
Anson
Hi, Shawn
> > On 16/08/2019 02:38, Anson Huang wrote:
> > > Enable i.MX8MM cpu-idle using generic ARM cpu-idle driver, 2 states
> > > are supported, details as below:
> > >
> > > root@imx8mmevk:~# cat
> > /sys/devices/system/cpu/cpu0/cpuidle/state0/name
> > > WFI
> > > root@imx8mmevk:~# cat
> > > /sys/devices/system/cpu/cpu0/cpuidle/state0/usage
> > > 3973
> > > root@imx8mmevk:~# cat
> > /sys/devices/system/cpu/cpu0/cpuidle/state1/name
> > > cpu-pd-wait
> > > root@imx8mmevk:~# cat
> > > /sys/devices/system/cpu/cpu0/cpuidle/state1/usage
> > > 6647
> > >
> > > Signed-off-by: Anson Huang <[email protected]>
> >
> > Hi Anson,
> >
> > I've applied the patches 1-3 but this one does not apply.
>
> Thanks.
>
> >
> > You can either respin it against tip/timers/core and take it through
> > Shawn's tree. If the later, you can add my Acked-by.
>
> Hi, Shawn
> Can you take this patch and add below Acked-by? It should can be
> applied to your tree directly.
>
> Acked-by: Daniel Lezcano <[email protected]>
Sorry that I just found this patch can NOT be applied to your for-next tree neither, so
I redo the patch against your for-next tree, so you can just skip this patch series now
(as Daniel already picked the rest 3 patches) and take that patch I just sent, link as below:
https://patchwork.kernel.org/patch/11097471/
Thanks,
Anson