Enable i2c1 on i.MX8MN DDR4 EVK board.
Signed-off-by: Anson Huang <[email protected]>
---
No changes.
---
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
index 9b2c172..5fce5b1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
@@ -50,6 +50,13 @@
>;
};
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
+ MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ >;
+ };
+
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
fsl,pins = <
MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
@@ -182,6 +189,13 @@
};
};
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
&snvs_pwrkey {
status = "okay";
};
--
2.7.4
Add A53 OPP table, cpu regulator and speed grading node to
support cpu-freq driver.
Signed-off-by: Anson Huang <[email protected]>
---
No changes.
---
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 4 +++
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 41 +++++++++++++++++++++++
2 files changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
index 10ebf77..11c705d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
@@ -27,6 +27,10 @@
};
};
+&A53_0 {
+ cpu-supply = <&buck2_reg>;
+};
+
&iomuxc {
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 1d8899b..785f4c4 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -51,6 +51,9 @@
clocks = <&clk IMX8MN_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ operating-points-v2 = <&a53_opp_table>;
+ nvmem-cells = <&cpu_speed_grade>;
+ nvmem-cell-names = "speed_grade";
};
A53_1: cpu@1 {
@@ -61,6 +64,7 @@
clocks = <&clk IMX8MN_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ operating-points-v2 = <&a53_opp_table>;
};
A53_2: cpu@2 {
@@ -71,6 +75,7 @@
clocks = <&clk IMX8MN_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ operating-points-v2 = <&a53_opp_table>;
};
A53_3: cpu@3 {
@@ -81,6 +86,7 @@
clocks = <&clk IMX8MN_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ operating-points-v2 = <&a53_opp_table>;
};
A53_L2: l2-cache0 {
@@ -88,6 +94,35 @@
};
};
+ a53_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <850000>;
+ opp-supported-hw = <0xb00>, <0x7>;
+ clock-latency-ns = <150000>;
+ opp-suspend;
+ };
+
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-microvolt = <950000>;
+ opp-supported-hw = <0x300>, <0x7>;
+ clock-latency-ns = <150000>;
+ opp-suspend;
+ };
+
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <1000000>;
+ opp-supported-hw = <0x100>, <0x3>;
+ clock-latency-ns = <150000>;
+ opp-suspend;
+ };
+ };
+
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
@@ -288,6 +323,12 @@
compatible = "fsl,imx8mn-ocotp", "fsl,imx7d-ocotp", "syscon";
reg = <0x30350000 0x10000>;
clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpu_speed_grade: speed-grade@10 {
+ reg = <0x10 4>;
+ };
};
anatop: anatop@30360000 {
--
2.7.4
i.MX8MN supports CPU running at 1.5GHz/1.4GHz/1.2GHz, add missing
frequency for ARM PLL table.
Signed-off-by: Anson Huang <[email protected]>
---
Changes since V1:
- split the patch into 2 patches, #1 fixed those missing .rate_count assignment,
#2 add missing frequency points.
---
drivers/clk/imx/clk-imx8mn.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index b5a027c..48884f9 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -42,6 +42,8 @@ enum {
static const struct imx_pll14xx_rate_table imx8mn_pll1416x_tbl[] = {
PLL_1416X_RATE(1800000000U, 225, 3, 0),
PLL_1416X_RATE(1600000000U, 200, 3, 0),
+ PLL_1416X_RATE(1500000000U, 375, 3, 1),
+ PLL_1416X_RATE(1400000000U, 350, 3, 1),
PLL_1416X_RATE(1200000000U, 300, 3, 1),
PLL_1416X_RATE(1000000000U, 250, 3, 1),
PLL_1416X_RATE(800000000U, 200, 3, 1),
--
2.7.4
i.MX8MN has different speed grading definition as below, it has 4 bits
to define speed grading, add support for it.
SPEED_GRADE[3:0] MHz
0000 2300
0001 2200
0010 2100
0011 2000
0100 1900
0101 1800
0110 1700
0111 1600
1000 1500
1001 1400
1010 1300
1011 1200
1100 1100
1101 1000
1110 900
1111 800
Signed-off-by: Anson Huang <[email protected]>
---
No changes.
---
drivers/cpufreq/imx-cpufreq-dt.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/cpufreq/imx-cpufreq-dt.c b/drivers/cpufreq/imx-cpufreq-dt.c
index 4f85f31..35db14c 100644
--- a/drivers/cpufreq/imx-cpufreq-dt.c
+++ b/drivers/cpufreq/imx-cpufreq-dt.c
@@ -16,6 +16,7 @@
#define OCOTP_CFG3_SPEED_GRADE_SHIFT 8
#define OCOTP_CFG3_SPEED_GRADE_MASK (0x3 << 8)
+#define IMX8MN_OCOTP_CFG3_SPEED_GRADE_MASK (0xf << 8)
#define OCOTP_CFG3_MKT_SEGMENT_SHIFT 6
#define OCOTP_CFG3_MKT_SEGMENT_MASK (0x3 << 6)
@@ -34,7 +35,12 @@ static int imx_cpufreq_dt_probe(struct platform_device *pdev)
if (ret)
return ret;
- speed_grade = (cell_value & OCOTP_CFG3_SPEED_GRADE_MASK) >> OCOTP_CFG3_SPEED_GRADE_SHIFT;
+ if (of_machine_is_compatible("fsl,imx8mn"))
+ speed_grade = (cell_value & IMX8MN_OCOTP_CFG3_SPEED_GRADE_MASK)
+ >> OCOTP_CFG3_SPEED_GRADE_SHIFT;
+ else
+ speed_grade = (cell_value & OCOTP_CFG3_SPEED_GRADE_MASK)
+ >> OCOTP_CFG3_SPEED_GRADE_SHIFT;
mkt_segment = (cell_value & OCOTP_CFG3_MKT_SEGMENT_MASK) >> OCOTP_CFG3_MKT_SEGMENT_SHIFT;
/*
--
2.7.4
Add i.MX8MN to blacklist, so that imx-cpufreq-dt driver can handle
speed grading bits just like other i.MX8M SoCs.
Signed-off-by: Anson Huang <[email protected]>
---
No changes.
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index ec2057d..febcec8 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -109,6 +109,7 @@ static const struct of_device_id blacklist[] __initconst = {
{ .compatible = "fsl,imx7d", },
{ .compatible = "fsl,imx8mq", },
{ .compatible = "fsl,imx8mm", },
+ { .compatible = "fsl,imx8mn", },
{ .compatible = "marvell,armadaxp", },
--
2.7.4
On i.MX8MN DDR4 EVK board, there is a rohm,bd71847 PMIC
on i2c1 bus, enable it.
Signed-off-by: Anson Huang <[email protected]>
---
No changes.
---
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 109 ++++++++++++++++++++++
1 file changed, 109 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
index 5fce5b1..10ebf77 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
@@ -57,6 +57,12 @@
>;
};
+ pinctrl_pmic: pmicirq {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
+ >;
+ };
+
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
fsl,pins = <
MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
@@ -194,6 +200,109 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
+
+ pmic@4b {
+ compatible = "rohm,bd71847";
+ reg = <0x4b>;
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 GPIO_ACTIVE_LOW>;
+ rohm,reset-snvs-powered;
+
+ regulators {
+ buck1_reg: BUCK1 {
+ regulator-name = "BUCK1";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-name = "BUCK2";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+
+ buck3_reg: BUCK3 {
+ // BUCK5 in datasheet
+ regulator-name = "BUCK3";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ };
+
+ buck4_reg: BUCK4 {
+ // BUCK6 in datasheet
+ regulator-name = "BUCK4";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5_reg: BUCK5 {
+ // BUCK7 in datasheet
+ regulator-name = "BUCK5";
+ regulator-min-microvolt = <1605000>;
+ regulator-max-microvolt = <1995000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6_reg: BUCK6 {
+ // BUCK8 in datasheet
+ regulator-name = "BUCK6";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2_reg: LDO2 {
+ regulator-name = "LDO2";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-name = "LDO3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "LDO4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-name = "LDO6";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
};
&snvs_pwrkey {
--
2.7.4
Add .rate_count assignment which is necessary for searching required
PLL rate from the each PLL table.
Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver")
Signed-off-by: Anson Huang <[email protected]>
---
Changes since V1:
- split the patch into 2 patches, #1 fixed those missing .rate_count assignment,
#2 add missing frequency points.
---
drivers/clk/imx/clk-imx8mn.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index ecd1062..b5a027c 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -67,36 +67,43 @@ static const struct imx_pll14xx_rate_table imx8mn_drampll_tbl[] = {
static struct imx_pll14xx_clk imx8mn_audio_pll = {
.type = PLL_1443X,
.rate_table = imx8mn_audiopll_tbl,
+ .rate_count = ARRAY_SIZE(imx8mn_audiopll_tbl),
};
static struct imx_pll14xx_clk imx8mn_video_pll = {
.type = PLL_1443X,
.rate_table = imx8mn_videopll_tbl,
+ .rate_count = ARRAY_SIZE(imx8mn_videopll_tbl),
};
static struct imx_pll14xx_clk imx8mn_dram_pll = {
.type = PLL_1443X,
.rate_table = imx8mn_drampll_tbl,
+ .rate_count = ARRAY_SIZE(imx8mn_drampll_tbl),
};
static struct imx_pll14xx_clk imx8mn_arm_pll = {
.type = PLL_1416X,
.rate_table = imx8mn_pll1416x_tbl,
+ .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
};
static struct imx_pll14xx_clk imx8mn_gpu_pll = {
.type = PLL_1416X,
.rate_table = imx8mn_pll1416x_tbl,
+ .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
};
static struct imx_pll14xx_clk imx8mn_vpu_pll = {
.type = PLL_1416X,
.rate_table = imx8mn_pll1416x_tbl,
+ .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
};
static struct imx_pll14xx_clk imx8mn_sys_pll = {
.type = PLL_1416X,
.rate_table = imx8mn_pll1416x_tbl,
+ .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
};
static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
--
2.7.4
On 18-08-19, 02:32, Anson Huang wrote:
> Add i.MX8MN to blacklist, so that imx-cpufreq-dt driver can handle
> speed grading bits just like other i.MX8M SoCs.
>
> Signed-off-by: Anson Huang <[email protected]>
> Reviewed-by: Leonard Crestez <[email protected]>
> ---
> No changes.
> ---
> drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
> index ec2057d..febcec8 100644
> --- a/drivers/cpufreq/cpufreq-dt-platdev.c
> +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
> @@ -109,6 +109,7 @@ static const struct of_device_id blacklist[] __initconst = {
> { .compatible = "fsl,imx7d", },
> { .compatible = "fsl,imx8mq", },
> { .compatible = "fsl,imx8mm", },
> + { .compatible = "fsl,imx8mn", },
>
> { .compatible = "marvell,armadaxp", },
>
Applied. Thanks.
--
viresh
On 18-08-19, 02:32, Anson Huang wrote:
> i.MX8MN has different speed grading definition as below, it has 4 bits
> to define speed grading, add support for it.
>
> SPEED_GRADE[3:0] MHz
> 0000 2300
> 0001 2200
> 0010 2100
> 0011 2000
> 0100 1900
> 0101 1800
> 0110 1700
> 0111 1600
> 1000 1500
> 1001 1400
> 1010 1300
> 1011 1200
> 1100 1100
> 1101 1000
> 1110 900
> 1111 800
>
> Signed-off-by: Anson Huang <[email protected]>
> Reviewed-by: Leonard Crestez <[email protected]>
> ---
> No changes.
> ---
> drivers/cpufreq/imx-cpufreq-dt.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
Applied. Thanks.
--
viresh
On Sun, Aug 18, 2019 at 02:32:19AM -0400, Anson Huang wrote:
> Enable i2c1 on i.MX8MN DDR4 EVK board.
>
> Signed-off-by: Anson Huang <[email protected]>
Applied, thanks.
On Sun, Aug 18, 2019 at 02:32:20AM -0400, Anson Huang wrote:
> On i.MX8MN DDR4 EVK board, there is a rohm,bd71847 PMIC
> on i2c1 bus, enable it.
>
> Signed-off-by: Anson Huang <[email protected]>
Applied, thanks.
On Sun, Aug 18, 2019 at 02:32:23AM -0400, Anson Huang wrote:
> Add .rate_count assignment which is necessary for searching required
> PLL rate from the each PLL table.
>
> Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver")
The commit ID is not stable before the commit lands on mainline, so I
dropped it and applied the patch.
Shawn
> Signed-off-by: Anson Huang <[email protected]>
> ---
> Changes since V1:
> - split the patch into 2 patches, #1 fixed those missing .rate_count assignment,
> #2 add missing frequency points.
> ---
> drivers/clk/imx/clk-imx8mn.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
> index ecd1062..b5a027c 100644
> --- a/drivers/clk/imx/clk-imx8mn.c
> +++ b/drivers/clk/imx/clk-imx8mn.c
> @@ -67,36 +67,43 @@ static const struct imx_pll14xx_rate_table imx8mn_drampll_tbl[] = {
> static struct imx_pll14xx_clk imx8mn_audio_pll = {
> .type = PLL_1443X,
> .rate_table = imx8mn_audiopll_tbl,
> + .rate_count = ARRAY_SIZE(imx8mn_audiopll_tbl),
> };
>
> static struct imx_pll14xx_clk imx8mn_video_pll = {
> .type = PLL_1443X,
> .rate_table = imx8mn_videopll_tbl,
> + .rate_count = ARRAY_SIZE(imx8mn_videopll_tbl),
> };
>
> static struct imx_pll14xx_clk imx8mn_dram_pll = {
> .type = PLL_1443X,
> .rate_table = imx8mn_drampll_tbl,
> + .rate_count = ARRAY_SIZE(imx8mn_drampll_tbl),
> };
>
> static struct imx_pll14xx_clk imx8mn_arm_pll = {
> .type = PLL_1416X,
> .rate_table = imx8mn_pll1416x_tbl,
> + .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
> };
>
> static struct imx_pll14xx_clk imx8mn_gpu_pll = {
> .type = PLL_1416X,
> .rate_table = imx8mn_pll1416x_tbl,
> + .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
> };
>
> static struct imx_pll14xx_clk imx8mn_vpu_pll = {
> .type = PLL_1416X,
> .rate_table = imx8mn_pll1416x_tbl,
> + .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
> };
>
> static struct imx_pll14xx_clk imx8mn_sys_pll = {
> .type = PLL_1416X,
> .rate_table = imx8mn_pll1416x_tbl,
> + .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
> };
>
> static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
> --
> 2.7.4
>
On Sun, Aug 18, 2019 at 02:32:24AM -0400, Anson Huang wrote:
> i.MX8MN supports CPU running at 1.5GHz/1.4GHz/1.2GHz, add missing
> frequency for ARM PLL table.
>
> Signed-off-by: Anson Huang <[email protected]>
Applied, thanks.
On Sun, Aug 18, 2019 at 02:32:25AM -0400, Anson Huang wrote:
> Add A53 OPP table, cpu regulator and speed grading node to
> support cpu-freq driver.
>
> Signed-off-by: Anson Huang <[email protected]>
Applied, thanks.