Add fspi node property for LS1028A SoC for FlexSPI driver.
Property added for FlexSPI controller and for the connected
slave device for the LS1028ARDB and LS1028AQDS target.
RDB and QDS is having one SPI-NOR flash device, mt35xu02g
connected at CS0.
This flash device "mt35xu02g" is tested for octal read
Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Ashish Kumar <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 15 +++++++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 15 +++++++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 13 +++++++++++++
3 files changed, 43 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index 5e14e5a..5d46993 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -103,6 +103,21 @@
status = "okay";
};
+&fspi {
+ status = "okay";
+ flash0: mt35xu02g@0 {
+ compatible = "micron,mt35xu02g", "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ m25p,fast-read;
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
+ spi-rx-bus-width = <8>; /* 8 SPI Rx lines */
+ spi-tx-bus-width = <1>; /* 1 SPI Tx line */
+ };
+};
+
&i2c0 {
status = "okay";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index 1a69221..f33cb2e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -96,6 +96,21 @@
status = "okay";
};
+&fspi {
+ status = "okay";
+ flash0: mt35xu02g@0 {
+ compatible = "micron,mt35xu02g", "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ m25p,fast-read;
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
+ spi-rx-bus-width = <8>; /* 8 SPI Rx lines */
+ spi-tx-bus-width = <1>; /* 1 SPI Tx line */
+ };
+};
+
&i2c0 {
status = "okay";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index b139b29..4aa1825 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -174,6 +174,19 @@
clocks = <&sysclk>;
};
+ fspi: spi@20c0000 {
+ compatible = "nxp,lx2160a-fspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20c0000 0x0 0x10000>,
+ <0x0 0x20000000 0x0 0x10000000>;
+ reg-names = "fspi_base", "fspi_mmap";
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "fspi_en", "fspi";
+ status = "disabled";
+ };
+
i2c0: i2c@2000000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
--
2.7.4
Add QSPI node in dtsi(ls1088si), and dts(ls1088ardb, ls1088aqds) boards.
Both ls1088ardb and ls1088aqds has two 64MB flash from SPANSION(s25fs512s).
QUAD I/O is tested in case of read and single I/O is tested in case of
write.
Signed-off-by: Kuldeep Singh <[email protected]>
Signed-off-by: Ashish Kumar <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts | 26 +++++++++++++++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 26 +++++++++++++++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 13 ++++++++++++
3 files changed, 65 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
index 120e62d..3347e6a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
@@ -143,6 +143,32 @@
status = "okay";
};
+&qspi {
+ status = "okay";
+
+ qflash0: s25fs512s@0 {
+ compatible = "spansion,s25fs512a", "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ m25p,fast-read;
+ spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ reg = <0>;
+ };
+
+ qflash1: s25fs512s@1 {
+ compatible = "spansion,s25fs512a", "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ m25p,fast-read;
+ spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ reg = <1>;
+ };
+};
+
&sata {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
index 8e925df..09d3203 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
@@ -86,6 +86,32 @@
status = "okay";
};
+&qspi {
+ status = "okay";
+
+ qflash0: s25fs512s@0 {
+ compatible = "spansion,s25fs512a", "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ m25p,fast-read;
+ spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ reg = <0>;
+ };
+
+ qflash1: s25fs512s@1 {
+ compatible = "spansion,s25fs512a", "jedec,spi-nor";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ m25p,fast-read;
+ spi-max-frequency = <50000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ reg = <1>;
+ };
+};
+
&sata {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index d1469b0..5a81a7e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -408,6 +408,19 @@
status = "disabled";
};
+ qspi: spi@20c0000 {
+ compatible = "fsl,ls2080a-qspi", "fsl,ls1088a-qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20c0000 0x0 0x10000>,
+ <0x0 0x20000000 0x0 0x10000000>;
+ reg-names = "QuadSPI", "QuadSPI-memory";
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "qspi_en", "qspi";
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ status = "disabled";
+ };
+
sata: sata@3200000 {
compatible = "fsl,ls1088a-ahci";
reg = <0x0 0x3200000 0x0 0x10000>,
--
2.7.4
Since device properties are different, so remove fsl, ls1021a-qspi.
ls1021a-qspi is to be used only for Big-endian verion of QSPI controller
Signed-off-by: Kuldeep Singh <[email protected]>
Signed-off-by: Ashish Kumar <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 64101c9..8e42ac9 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -619,7 +619,7 @@
qspi: spi@20c0000 {
status = "disabled";
- compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
+ compatible = "fsl,ls2080a-qspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20c0000 0x0 0x10000>,
--
2.7.4
On Tue, Sep 10, 2019 at 05:50:51PM +0530, Ashish Kumar wrote:
> Add fspi node property for LS1028A SoC for FlexSPI driver.
> Property added for FlexSPI controller and for the connected
> slave device for the LS1028ARDB and LS1028AQDS target.
> RDB and QDS is having one SPI-NOR flash device, mt35xu02g
> connected at CS0.
> This flash device "mt35xu02g" is tested for octal read
>
> Signed-off-by: Xiaowei Bao <[email protected]>
> Signed-off-by: Ashish Kumar <[email protected]>
When you send a patch series, the patches should be numbered properly
and preferably with a cover-letter.
> ---
> arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 15 +++++++++++++++
> arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 15 +++++++++++++++
> arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 13 +++++++++++++
> 3 files changed, 43 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> index 5e14e5a..5d46993 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> @@ -103,6 +103,21 @@
> status = "okay";
> };
>
> +&fspi {
> + status = "okay";
Have a newline between properties and child node..
> + flash0: mt35xu02g@0 {
Use a generic node name and specific label name.
> + compatible = "micron,mt35xu02g", "jedec,spi-nor";
"micron,mt35xu02g" is undocumented.
Shawn
> + #address-cells = <1>;
> + #size-cells = <1>;
> + m25p,fast-read;
> + spi-max-frequency = <50000000>;
> + reg = <0>;
> + /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
> + spi-rx-bus-width = <8>; /* 8 SPI Rx lines */
> + spi-tx-bus-width = <1>; /* 1 SPI Tx line */
> + };
> +};
> +
> &i2c0 {
> status = "okay";
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> index 1a69221..f33cb2e 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> @@ -96,6 +96,21 @@
> status = "okay";
> };
>
> +&fspi {
> + status = "okay";
> + flash0: mt35xu02g@0 {
> + compatible = "micron,mt35xu02g", "jedec,spi-nor";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + m25p,fast-read;
> + spi-max-frequency = <50000000>;
> + reg = <0>;
> + /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
> + spi-rx-bus-width = <8>; /* 8 SPI Rx lines */
> + spi-tx-bus-width = <1>; /* 1 SPI Tx line */
> + };
> +};
> +
> &i2c0 {
> status = "okay";
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> index b139b29..4aa1825 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> @@ -174,6 +174,19 @@
> clocks = <&sysclk>;
> };
>
> + fspi: spi@20c0000 {
> + compatible = "nxp,lx2160a-fspi";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x0 0x20c0000 0x0 0x10000>,
> + <0x0 0x20000000 0x0 0x10000000>;
> + reg-names = "fspi_base", "fspi_mmap";
> + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
> + clock-names = "fspi_en", "fspi";
> + status = "disabled";
> + };
> +
> i2c0: i2c@2000000 {
> compatible = "fsl,vf610-i2c";
> #address-cells = <1>;
> --
> 2.7.4
>
> -----Original Message-----
> From: Shawn Guo <[email protected]>
> Sent: 2019??10??6?? 11:20
> To: Ashish Kumar <[email protected]>
> Cc: [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; Xiaowei
> Bao <[email protected]>
> Subject: Re: [PATCH] arm64: dts: ls1028a: Add FlexSPI support for NXP LS1028
>
> On Tue, Sep 10, 2019 at 05:50:51PM +0530, Ashish Kumar wrote:
> > Add fspi node property for LS1028A SoC for FlexSPI driver.
> > Property added for FlexSPI controller and for the connected slave
> > device for the LS1028ARDB and LS1028AQDS target.
> > RDB and QDS is having one SPI-NOR flash device, mt35xu02g connected at
> > CS0.
> > This flash device "mt35xu02g" is tested for octal read
> >
> > Signed-off-by: Xiaowei Bao <[email protected]>
> > Signed-off-by: Ashish Kumar <[email protected]>
>
> When you send a patch series, the patches should be numbered properly and
> preferably with a cover-letter.
Got it, thanks.
Thanks
Xiaowei
>
> > ---
> > arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 15
> > +++++++++++++++ arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts |
> 15 +++++++++++++++
> > arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 13 +++++++++++++
> > 3 files changed, 43 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > index 5e14e5a..5d46993 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > @@ -103,6 +103,21 @@
> > status = "okay";
> > };
> >
> > +&fspi {
> > + status = "okay";
>
> Have a newline between properties and child node..
>
> > + flash0: mt35xu02g@0 {
>
> Use a generic node name and specific label name.
>
> > + compatible = "micron,mt35xu02g", "jedec,spi-nor";
>
> "micron,mt35xu02g" is undocumented.
>
> Shawn
>
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + m25p,fast-read;
> > + spi-max-frequency = <50000000>;
> > + reg = <0>;
> > + /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
> > + spi-rx-bus-width = <8>; /* 8 SPI Rx lines */
> > + spi-tx-bus-width = <1>; /* 1 SPI Tx line */
> > + };
> > +};
> > +
> > &i2c0 {
> > status = "okay";
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> > b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> > index 1a69221..f33cb2e 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> > @@ -96,6 +96,21 @@
> > status = "okay";
> > };
> >
> > +&fspi {
> > + status = "okay";
> > + flash0: mt35xu02g@0 {
> > + compatible = "micron,mt35xu02g", "jedec,spi-nor";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + m25p,fast-read;
> > + spi-max-frequency = <50000000>;
> > + reg = <0>;
> > + /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
> > + spi-rx-bus-width = <8>; /* 8 SPI Rx lines */
> > + spi-tx-bus-width = <1>; /* 1 SPI Tx line */
> > + };
> > +};
> > +
> > &i2c0 {
> > status = "okay";
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > index b139b29..4aa1825 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > @@ -174,6 +174,19 @@
> > clocks = <&sysclk>;
> > };
> >
> > + fspi: spi@20c0000 {
> > + compatible = "nxp,lx2160a-fspi";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x0 0x20c0000 0x0 0x10000>,
> > + <0x0 0x20000000 0x0 0x10000000>;
> > + reg-names = "fspi_base", "fspi_mmap";
> > + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
> > + clock-names = "fspi_en", "fspi";
> > + status = "disabled";
> > + };
> > +
> > i2c0: i2c@2000000 {
> > compatible = "fsl,vf610-i2c";
> > #address-cells = <1>;
> > --
> > 2.7.4
> >