cpp[BytePerPlane] can't describe the 10bit data format correctly,
So we use bpp[BitPerPlane] to instead cpp.
Signed-off-by: Sandy Huang <[email protected]>
---
drivers/gpu/drm/armada/armada_fbdev.c | 2 +-
drivers/gpu/drm/armada/armada_plane.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/armada/armada_fbdev.c b/drivers/gpu/drm/armada/armada_fbdev.c
index 090cc0d..a2e4344 100644
--- a/drivers/gpu/drm/armada/armada_fbdev.c
+++ b/drivers/gpu/drm/armada/armada_fbdev.c
@@ -88,7 +88,7 @@ static int armada_fbdev_create(struct drm_fb_helper *fbh,
drm_fb_helper_fill_info(info, fbh, sizes);
DRM_DEBUG_KMS("allocated %dx%d %dbpp fb: 0x%08llx\n",
- dfb->fb.width, dfb->fb.height, dfb->fb.format->cpp[0] * 8,
+ dfb->fb.width, dfb->fb.height, dfb->fb.format->bpp[0],
(unsigned long long)obj->phys_addr);
return 0;
diff --git a/drivers/gpu/drm/armada/armada_plane.c b/drivers/gpu/drm/armada/armada_plane.c
index e7cc2b3..fa400ac 100644
--- a/drivers/gpu/drm/armada/armada_plane.c
+++ b/drivers/gpu/drm/armada/armada_plane.c
@@ -46,13 +46,13 @@ void armada_drm_plane_calc(struct drm_plane_state *state, u32 addrs[2][3],
int i;
DRM_DEBUG_KMS("pitch %u x %d y %d bpp %d\n",
- fb->pitches[0], x, y, format->cpp[0] * 8);
+ fb->pitches[0], x, y, format->bpp[0]);
if (num_planes > 3)
num_planes = 3;
addrs[0][0] = addr + fb->offsets[0] + y * fb->pitches[0] +
- x * format->cpp[0];
+ x * format->bpp[0] / 8;
pitches[0] = fb->pitches[0];
y /= format->vsub;
@@ -60,7 +60,7 @@ void armada_drm_plane_calc(struct drm_plane_state *state, u32 addrs[2][3],
for (i = 1; i < num_planes; i++) {
addrs[0][i] = addr + fb->offsets[i] + y * fb->pitches[i] +
- x * format->cpp[i];
+ x * format->bpp[i] / 8;
pitches[i] = fb->pitches[i];
}
for (; i < 3; i++) {
--
2.7.4
cpp[BytePerPlane] can't describe the 10bit data format correctly,
So we use bpp[BitPerPlane] to instead cpp.
Signed-off-by: Sandy Huang <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_drm_fb.c | 2 +-
drivers/gpu/drm/mediatek/mtk_drm_plane.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_fb.c b/drivers/gpu/drm/mediatek/mtk_drm_fb.c
index 3f230a2..fd80548 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_fb.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_fb.c
@@ -69,7 +69,7 @@ struct drm_framebuffer *mtk_drm_mode_fb_create(struct drm_device *dev,
if (!gem)
return ERR_PTR(-ENOENT);
- bpp = info->cpp[0];
+ bpp = info->bpp[0] / 8;
size = (height - 1) * cmd->pitches[0] + width * bpp;
size += cmd->offsets[0];
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/mediatek/mtk_drm_plane.c
index 584a9ec..97d38db 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c
@@ -121,7 +121,7 @@ static void mtk_plane_atomic_update(struct drm_plane *plane,
pitch = fb->pitches[0];
format = fb->format->format;
- addr += (plane->state->src.x1 >> 16) * fb->format->cpp[0];
+ addr += (plane->state->src.x1 >> 16) * fb->format->bpp[0] / 8;
addr += (plane->state->src.y1 >> 16) * pitch;
state->pending.enable = true;
--
2.7.4
cpp[BytePerPlane] can't describe the 10bit data format correctly,
So we use bpp[BitPerPlane] to instead cpp.
Signed-off-by: Sandy Huang <[email protected]>
---
drivers/gpu/drm/radeon/atombios_crtc.c | 10 +++++-----
drivers/gpu/drm/radeon/r100.c | 4 ++--
drivers/gpu/drm/radeon/radeon_display.c | 6 +++---
drivers/gpu/drm/radeon/radeon_fb.c | 2 +-
drivers/gpu/drm/radeon/radeon_legacy_crtc.c | 14 +++++++-------
5 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index da2c9e2..e8a033f 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1285,7 +1285,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
/* Calculate the macrotile mode index. */
tile_split_bytes = 64 << tile_split;
- tileb = 8 * 8 * target_fb->format->cpp[0];
+ tileb = 8 * target_fb->format->bpp[0];
tileb = min(tile_split_bytes, tileb);
for (index = 0; tileb > 64; index++)
@@ -1293,14 +1293,14 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
if (index >= 16) {
DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
- target_fb->format->cpp[0] * 8,
+ target_fb->format->bpp[0],
tile_split);
return -EINVAL;
}
num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
} else {
- switch (target_fb->format->cpp[0] * 8) {
+ switch (target_fb->format->bpp[0]) {
case 8:
index = 10;
break;
@@ -1423,7 +1423,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
- fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
+ fb_pitch_pixels = target_fb->pitches[0] / (target_fb->format->bpp[0] / 8);
WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
@@ -1639,7 +1639,7 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
- fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
+ fb_pitch_pixels = target_fb->pitches[0] / (target_fb->format->bpp[0] / 8);
WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 7089dfc..85b3081 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -3229,7 +3229,7 @@ void r100_bandwidth_update(struct radeon_device *rdev)
rdev->mode_info.crtcs[0]->base.primary->fb;
mode1 = &rdev->mode_info.crtcs[0]->base.mode;
- pixel_bytes1 = fb->format->cpp[0];
+ pixel_bytes1 = fb->format->bpp[0] / 8;
}
if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
if (rdev->mode_info.crtcs[1]->base.enabled) {
@@ -3237,7 +3237,7 @@ void r100_bandwidth_update(struct radeon_device *rdev)
rdev->mode_info.crtcs[1]->base.primary->fb;
mode2 = &rdev->mode_info.crtcs[1]->base.mode;
- pixel_bytes2 = fb->format->cpp[0];
+ pixel_bytes2 = fb->format->bpp[0] / 8;
}
}
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index e81b01f..066202c 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -540,19 +540,19 @@ static int radeon_crtc_page_flip_target(struct drm_crtc *crtc,
if (!ASIC_IS_AVIVO(rdev)) {
/* crtc offset is from display base addr not FB location */
base -= radeon_crtc->legacy_display_base_addr;
- pitch_pixels = fb->pitches[0] / fb->format->cpp[0];
+ pitch_pixels = fb->pitches[0] / fb->format->bpp[0] / 8;
if (tiling_flags & RADEON_TILING_MACRO) {
if (ASIC_IS_R300(rdev)) {
base &= ~0x7ff;
} else {
- int byteshift = fb->format->cpp[0] * 8 >> 4;
+ int byteshift = fb->format->bpp[0] >> 4;
int tile_addr = (((crtc->y >> 3) * pitch_pixels + crtc->x) >> (8 - byteshift)) << 11;
base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
}
} else {
int offset = crtc->y * pitch_pixels + crtc->x;
- switch (fb->format->cpp[0] * 8) {
+ switch (fb->format->bpp[0]) {
case 8:
default:
offset *= 1;
diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
index 2c564f4..5c6057f 100644
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -138,7 +138,7 @@ static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev,
u32 cpp;
info = drm_get_format_info(rdev->ddev, mode_cmd);
- cpp = info->cpp[0];
+ cpp = info->bpp[0] / 8;
/* need to align pitch with crtc limits */
mode_cmd->pitches[0] = radeon_align_pitch(rdev, mode_cmd->width, cpp,
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index a1985a5..21f6b25 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -400,7 +400,7 @@ int radeon_crtc_do_set_base(struct drm_crtc *crtc,
else
target_fb = crtc->primary->fb;
- switch (target_fb->format->cpp[0] * 8) {
+ switch (target_fb->format->bpp[0]) {
case 8:
format = 2;
break;
@@ -474,9 +474,9 @@ int radeon_crtc_do_set_base(struct drm_crtc *crtc,
crtc_offset_cntl = 0;
- pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
- crtc_pitch = DIV_ROUND_UP(pitch_pixels * target_fb->format->cpp[0] * 8,
- target_fb->format->cpp[0] * 8 * 8);
+ pitch_pixels = target_fb->pitches[0] / target_fb->format->bpp[0] / 8;
+ crtc_pitch = DIV_ROUND_UP(pitch_pixels * target_fb->format->bpp[0],
+ target_fb->format->bpp[0] * 8);
crtc_pitch |= crtc_pitch << 16;
crtc_offset_cntl |= RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN;
@@ -501,14 +501,14 @@ int radeon_crtc_do_set_base(struct drm_crtc *crtc,
crtc_tile_x0_y0 = x | (y << 16);
base &= ~0x7ff;
} else {
- int byteshift = target_fb->format->cpp[0] * 8 >> 4;
+ int byteshift = target_fb->format->bpp[0] >> 4;
int tile_addr = (((y >> 3) * pitch_pixels + x) >> (8 - byteshift)) << 11;
base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
crtc_offset_cntl |= (y % 16);
}
} else {
int offset = y * pitch_pixels + x;
- switch (target_fb->format->cpp[0] * 8) {
+ switch (target_fb->format->bpp[0]) {
case 8:
offset *= 1;
break;
@@ -599,7 +599,7 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod
}
}
- switch (fb->format->cpp[0] * 8) {
+ switch (fb->format->bpp[0]) {
case 8:
format = 2;
break;
--
2.7.4