This patchset adds Xilinx AXI MCDMA IP support. The AXI MCDMA provides
high-bandwidth direct memory access between memory and AXI4-Stream target
peripherals. It supports up to 16 independent read/write channels.
MCDMA IP supports per channel interrupt output but driver support one
interrupt per channel for simplification. IP specification/programming
sequence and register description is mentioned in PG [1].
The driver is tested with xilinx internal dmatest client. In end usecase
MCDMA will be used by xilinx axiethernet driver using dma API's.
Changes since RFC[2]:
- Remove xilinx axidma multichannel support.
- Addressed all RFC comments except modularizing initialization of channel
segment is skipped as it would create tight coupling b/w axidma and
mcdma internal structures.
- Include MCDMA IP description in Kconfig.
- Few regression fixes from xilinx tree.
NOTE: This patchset is based on next and previous[3] axidma series.
[1] https://www.xilinx.com/support/documentation/ip_documentation/axi_mcdma/v1_0/pg288-axi-mcdma.pdf
[2] https://spinics.net/lists/devicetree/msg242427.html
[3] https://www.spinics.net/lists/dmaengine/msg19910.html
Radhey Shyam Pandey (6):
dt-bindings: dmaengine: xilinx_dma: Remove axidma multichannel support
dt-bindings: dmaengine: xilinx_dma: Fix formatting and style
dt-bindings: dmaengine: xilinx_dma: Add binding for Xilinx MCDMA IP
dmaengine: xilinx_dma: Remove axidma multichannel mode support
dmaengine: xilinx_dma: Extend dma_config struct to store irq routine
handle
dmaengine: xilinx_dma: Add Xilinx AXI MCDMA Engine driver support
.../devicetree/bindings/dma/xilinx/xilinx_dma.txt | 24 +-
drivers/dma/Kconfig | 4 +
drivers/dma/xilinx/xilinx_dma.c | 517 ++++++++++++++++-----
3 files changed, 431 insertions(+), 114 deletions(-)
--
2.7.4
The AXI DMA multichannel support is deprecated in the IP and it is no
longer actively supported. For multichannel support, refer to the AXI
multichannel direct memory access IP product guide(PG228) and MCDMA
driver(added in the subsequent commits). Inline with it remove axidma
multichannel optional properties i.e xlnx,mcdma and dma-channels from
the binding description.
Signed-off-by: Radhey Shyam Pandey <[email protected]>
---
Changes since RFC:
New patch.
---
Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 3 ---
1 file changed, 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
index 93b6d96..99d06f9 100644
--- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
@@ -42,7 +42,6 @@ Optional properties for AXI DMA:
register as configured in h/w. Takes values {8...26}. If the property
is missing or invalid then the default value 23 is used. This is the
maximum value that is supported by all IP versions.
-- xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware.
Optional properties for VDMA:
- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
It takes following values:
@@ -69,8 +68,6 @@ Optional child node properties for VDMA:
enabled/disabled in hardware.
- xlnx,enable-vert-flip: Tells vertical flip is
enabled/disabled in hardware(S2MM path).
-Optional child node properties for AXI DMA:
--dma-channels: Number of dma channels in child node.
Example:
++++++++
--
2.7.4
Add devicetree binding for Xilinx AXI Multichannel Direct Memory Access
(AXI MCDMA) IP. The AXI MCDMA provides high-bandwidth direct memory
access between memory and AXI4-Stream target peripherals. The AXI MCDMA
core provides a scatter-gather interface with multiple channel support
with independent configuration.
Signed-off-by: Radhey Shyam Pandey <[email protected]>
---
Keep compatible string one per line. Suggested by Rob.
Reuse the existing xlnx,axi-dma-* channel names. Suggested by Rob.
---
.../devicetree/bindings/dma/xilinx/xilinx_dma.txt | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
index d4ba1cb..325aca5 100644
--- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
@@ -11,11 +11,16 @@ is to receive from the device.
Xilinx AXI CDMA engine, it does transfers between memory-mapped source
address and a memory-mapped destination address.
+Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream
+target devices. It can be configured to have up to 16 independent transmit
+and receive channels.
+
Required properties:
- compatible: Should be one of-
"xlnx,axi-vdma-1.00.a"
"xlnx,axi-dma-1.00.a"
"xlnx,axi-cdma-1.00.a"
+ "xlnx,axi-mcdma-1.00.a"
- #dma-cells: Should be <1>, see "dmas" property below
- reg: Should contain VDMA registers location and length.
- xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits).
@@ -31,7 +36,7 @@ Required properties:
"m_axis_mm2s_aclk", "s_axis_s2mm_aclk"
For CDMA:
Required elements: "s_axi_lite_aclk", "m_axi_aclk"
- For AXIDMA:
+ For AXIDMA and MCDMA:
Required elements: "s_axi_lite_aclk"
Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
"m_axi_sg_aclk"
@@ -39,7 +44,7 @@ Required properties:
Required properties for VDMA:
- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.
-Optional properties for AXI DMA:
+Optional properties for AXI DMA and MCDMA:
- xlnx,sg-length-width: Should be set to the width in bits of the length
register as configured in h/w. Takes values {8...26}. If the property
is missing or invalid then the default value 23 is used. This is the
@@ -56,8 +61,8 @@ Required child node properties:
For VDMA: It should be either "xlnx,axi-vdma-mm2s-channel" or
"xlnx,axi-vdma-s2mm-channel".
For CDMA: It should be "xlnx,axi-cdma-channel".
- For AXIDMA: It should be either "xlnx,axi-dma-mm2s-channel" or
- "xlnx,axi-dma-s2mm-channel".
+ For AXIDMA and MCDMA: It should be either "xlnx,axi-dma-mm2s-channel"
+ or "xlnx,axi-dma-s2mm-channel".
- interrupts: Should contain per channel VDMA interrupts.
- xlnx,datawidth: Should contain the stream data width, take values
{32,64...1024}.
@@ -70,6 +75,8 @@ Optional child node properties for VDMA:
enabled/disabled in hardware.
- xlnx,enable-vert-flip: Tells vertical flip is
enabled/disabled in hardware(S2MM path).
+Optional child node properties for MCDMA:
+- dma-channels: Number of dma channels in child node.
Example:
++++++++
--
2.7.4
Extend dma_config structure to store irq routine handle. It enables runtime
handler selection based on xdma_ip_type and serves as preparatory patch for
adding MCDMA IP support.
Signed-off-by: Radhey Shyam Pandey <[email protected]>
Suggested-by: Vinod Koul <[email protected]>
---
Changes since RFC:
New patch. It serve as a preparatory patch for MCDMA driver support.
---
drivers/dma/xilinx/xilinx_dma.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index 6d45865..25042a9 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -391,6 +391,7 @@ struct xilinx_dma_config {
int (*clk_init)(struct platform_device *pdev, struct clk **axi_clk,
struct clk **tx_clk, struct clk **txs_clk,
struct clk **rx_clk, struct clk **rxs_clk);
+ irqreturn_t (*irq_handler)(int irq, void *data);
};
/**
@@ -2402,8 +2403,8 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
/* Request the interrupt */
chan->irq = irq_of_parse_and_map(node, 0);
- err = request_irq(chan->irq, xilinx_dma_irq_handler, IRQF_SHARED,
- "xilinx-dma-controller", chan);
+ err = request_irq(chan->irq, xdev->dma_config->irq_handler,
+ IRQF_SHARED, "xilinx-dma-controller", chan);
if (err) {
dev_err(xdev->dev, "unable to request IRQ %d\n", chan->irq);
return err;
@@ -2497,16 +2498,19 @@ static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec,
static const struct xilinx_dma_config axidma_config = {
.dmatype = XDMA_TYPE_AXIDMA,
.clk_init = axidma_clk_init,
+ .irq_handler = xilinx_dma_irq_handler,
};
static const struct xilinx_dma_config axicdma_config = {
.dmatype = XDMA_TYPE_CDMA,
.clk_init = axicdma_clk_init,
+ .irq_handler = xilinx_dma_irq_handler,
};
static const struct xilinx_dma_config axivdma_config = {
.dmatype = XDMA_TYPE_VDMA,
.clk_init = axivdma_clk_init,
+ .irq_handler = xilinx_dma_irq_handler,
};
static const struct of_device_id xilinx_dma_of_ids[] = {
--
2.7.4
On Tue, 22 Oct 2019 22:30:17 +0530, Radhey Shyam Pandey wrote:
> The AXI DMA multichannel support is deprecated in the IP and it is no
> longer actively supported. For multichannel support, refer to the AXI
> multichannel direct memory access IP product guide(PG228) and MCDMA
> driver(added in the subsequent commits). Inline with it remove axidma
> multichannel optional properties i.e xlnx,mcdma and dma-channels from
> the binding description.
>
> Signed-off-by: Radhey Shyam Pandey <[email protected]>
> ---
> Changes since RFC:
> New patch.
> ---
> Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 3 ---
> 1 file changed, 3 deletions(-)
>
Acked-by: Rob Herring <[email protected]>
On Tue, 22 Oct 2019 22:30:19 +0530, Radhey Shyam Pandey wrote:
> Add devicetree binding for Xilinx AXI Multichannel Direct Memory Access
> (AXI MCDMA) IP. The AXI MCDMA provides high-bandwidth direct memory
> access between memory and AXI4-Stream target peripherals. The AXI MCDMA
> core provides a scatter-gather interface with multiple channel support
> with independent configuration.
>
> Signed-off-by: Radhey Shyam Pandey <[email protected]>
> ---
> Keep compatible string one per line. Suggested by Rob.
> Reuse the existing xlnx,axi-dma-* channel names. Suggested by Rob.
> ---
> .../devicetree/bindings/dma/xilinx/xilinx_dma.txt | 15 +++++++++++----
> 1 file changed, 11 insertions(+), 4 deletions(-)
>
Reviewed-by: Rob Herring <[email protected]>
On 22-10-19, 22:30, Radhey Shyam Pandey wrote:
> This patchset adds Xilinx AXI MCDMA IP support. The AXI MCDMA provides
> high-bandwidth direct memory access between memory and AXI4-Stream target
> peripherals. It supports up to 16 independent read/write channels.
>
> MCDMA IP supports per channel interrupt output but driver support one
> interrupt per channel for simplification. IP specification/programming
> sequence and register description is mentioned in PG [1].
>
> The driver is tested with xilinx internal dmatest client. In end usecase
> MCDMA will be used by xilinx axiethernet driver using dma API's.
Applied, thanks
--
~Vinod