This series is based on v5.4-rc1
changes since v7:
- reword in binding document [PATCH 02/14]
- fix error return checking bug in subsys clock control [PATCH 10/14]
- add power domains properity to mfgcfg patch [PATCH 14/14] from
https://patchwork.kernel.org/patch/11126199/
changes since v6:
- remove the patch of SPDX license identifier because it's already fixed
changes since v5:
- fix documentation in [PATCH 04/14]
- remove useless variable checking and reuse API of clock control in [PATCH 06/14]
- coding style fix of bus protection control in [PATCH 08/14]
- fix naming of new added data in [PATCH 09/14]
- small refactor of multiple step bus protection control in [PATCH 10/14]
changes since v4:
- add property to mt8183 smi-common
- seperate refactor patches and new add function
- add power controller device node
Weiyi Lu (14):
dt-bindings: mediatek: Add property to mt8183 smi-common
dt-bindings: soc: Add MT8183 power dt-bindings
soc: mediatek: Refactor polling timeout and documentation
soc: mediatek: Refactor regulator control
soc: mediatek: Refactor clock control
soc: mediatek: Refactor sram control
soc: mediatek: Refactor bus protection control
soc: mediatek: Add basic_clk_id to scp_power_data
soc: mediatek: Add multiple step bus protection control
soc: mediatek: Add subsys clock control for bus protection
soc: mediatek: Add extra sram control
soc: mediatek: Add MT8183 scpsys support
arm64: dts: Add power controller device node of MT8183
arm64: dts: Add power-domains properity to mfgcfg
.../memory-controllers/mediatek,smi-common.txt | 2 +-
.../devicetree/bindings/soc/mediatek/scpsys.txt | 20 +-
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 63 +++
drivers/soc/mediatek/Makefile | 2 +-
drivers/soc/mediatek/mtk-scpsys-ext.c | 99 ++++
drivers/soc/mediatek/mtk-scpsys.c | 575 ++++++++++++++++++---
include/dt-bindings/power/mt8183-power.h | 26 +
include/linux/soc/mediatek/scpsys-ext.h | 39 ++
8 files changed, 745 insertions(+), 81 deletions(-)
create mode 100644 drivers/soc/mediatek/mtk-scpsys-ext.c
create mode 100644 include/dt-bindings/power/mt8183-power.h
create mode 100644 include/linux/soc/mediatek/scpsys-ext.h
Try to stop extending the clk_id or clk_names if there are
more and more new BASIC clocks. To get its own clocks by the
basic_clk_id of each power domain.
Signed-off-by: Weiyi Lu <[email protected]>
---
drivers/soc/mediatek/mtk-scpsys.c | 29 +++++++++++++++++++++--------
1 file changed, 21 insertions(+), 8 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index fb2b027..d31e1a4 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -117,6 +117,8 @@ enum clk_id {
* @sram_pdn_ack_bits: The mask for sram power control acked bits.
* @bus_prot_mask: The mask for single step bus protection.
* @clk_id: The basic clocks required by this power domain.
+ * @basic_clk_id: provide the same purpose with field "clk_id"
+ * by declaring basic clock prefix name rather than clk_id.
* @caps: The flag for active wake-up action.
*/
struct scp_domain_data {
@@ -127,6 +129,7 @@ struct scp_domain_data {
u32 sram_pdn_ack_bits;
u32 bus_prot_mask;
enum clk_id clk_id[MAX_CLKS];
+ const char *basic_clk_id[MAX_CLKS];
u8 caps;
};
@@ -490,16 +493,26 @@ static struct scp *init_scp(struct platform_device *pdev,
scpd->data = data;
- for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) {
- struct clk *c = clk[data->clk_id[j]];
+ if (data->clk_id[0]) {
+ WARN_ON(data->basic_clk_id[0]);
- if (IS_ERR(c)) {
- dev_err(&pdev->dev, "%s: clk unavailable\n",
- data->name);
- return ERR_CAST(c);
- }
+ for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) {
+ struct clk *c = clk[data->clk_id[j]];
+
+ if (IS_ERR(c)) {
+ dev_err(&pdev->dev,
+ "%s: clk unavailable\n",
+ data->name);
+ return ERR_CAST(c);
+ }
- scpd->clk[j] = c;
+ scpd->clk[j] = c;
+ }
+ } else if (data->basic_clk_id[0]) {
+ for (j = 0; j < MAX_CLKS &&
+ data->basic_clk_id[j]; j++)
+ scpd->clk[j] = devm_clk_get(&pdev->dev,
+ data->basic_clk_id[j]);
}
genpd->name = data->name;
--
1.8.1.1.dirty
Put clock enable and disable control in separate function.
Signed-off-by: Weiyi Lu <[email protected]>
---
drivers/soc/mediatek/mtk-scpsys.c | 45 ++++++++++++++++++++++++---------------
1 file changed, 28 insertions(+), 17 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index aed540d..73e4a1a 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -207,6 +207,29 @@ static int scpsys_regulator_disable(struct scp_domain *scpd)
return regulator_disable(scpd->supply);
}
+static void scpsys_clk_disable(struct clk *clk[], int max_num)
+{
+ int i;
+
+ for (i = max_num - 1; i >= 0; i--)
+ clk_disable_unprepare(clk[i]);
+}
+
+static int scpsys_clk_enable(struct clk *clk[], int max_num)
+{
+ int i, ret = 0;
+
+ for (i = 0; i < max_num && clk[i]; i++) {
+ ret = clk_prepare_enable(clk[i]);
+ if (ret) {
+ scpsys_clk_disable(clk, i);
+ break;
+ }
+ }
+
+ return ret;
+}
+
static int scpsys_power_on(struct generic_pm_domain *genpd)
{
struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
@@ -215,21 +238,14 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
u32 val;
int ret, tmp;
- int i;
ret = scpsys_regulator_enable(scpd);
if (ret < 0)
return ret;
- for (i = 0; i < MAX_CLKS && scpd->clk[i]; i++) {
- ret = clk_prepare_enable(scpd->clk[i]);
- if (ret) {
- for (--i; i >= 0; i--)
- clk_disable_unprepare(scpd->clk[i]);
-
- goto err_clk;
- }
- }
+ ret = scpsys_clk_enable(scpd->clk, MAX_CLKS);
+ if (ret)
+ goto err_clk;
val = readl(ctl_addr);
val |= PWR_ON_BIT;
@@ -282,10 +298,7 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
return 0;
err_pwr_ack:
- for (i = MAX_CLKS - 1; i >= 0; i--) {
- if (scpd->clk[i])
- clk_disable_unprepare(scpd->clk[i]);
- }
+ scpsys_clk_disable(scpd->clk, MAX_CLKS);
err_clk:
scpsys_regulator_disable(scpd);
@@ -302,7 +315,6 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
u32 val;
int ret, tmp;
- int i;
if (scpd->data->bus_prot_mask) {
ret = mtk_infracfg_set_bus_protection(scp->infracfg,
@@ -343,8 +355,7 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
if (ret < 0)
goto out;
- for (i = 0; i < MAX_CLKS && scpd->clk[i]; i++)
- clk_disable_unprepare(scpd->clk[i]);
+ scpsys_clk_disable(scpd->clk, MAX_CLKS);
ret = scpsys_regulator_disable(scpd);
if (ret < 0)
--
1.8.1.1.dirty
Both MT8183 & MT6765 have more control steps of bus protection
than previous project. And there add more bus protection registers
reside at infracfg & smi-common. Also add new APIs for multiple
step bus protection control with more customized arguments.
Signed-off-by: Weiyi Lu <[email protected]>
---
drivers/soc/mediatek/Makefile | 2 +-
drivers/soc/mediatek/mtk-scpsys-ext.c | 99 +++++++++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-scpsys.c | 39 +++++++++----
include/linux/soc/mediatek/scpsys-ext.h | 39 +++++++++++++
4 files changed, 168 insertions(+), 11 deletions(-)
create mode 100644 drivers/soc/mediatek/mtk-scpsys-ext.c
create mode 100644 include/linux/soc/mediatek/scpsys-ext.h
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index b017330..b442be9 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
-obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
+obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o mtk-scpsys-ext.o
obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
diff --git a/drivers/soc/mediatek/mtk-scpsys-ext.c b/drivers/soc/mediatek/mtk-scpsys-ext.c
new file mode 100644
index 0000000..b24321e
--- /dev/null
+++ b/drivers/soc/mediatek/mtk-scpsys-ext.c
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Owen Chen <[email protected]>
+ */
+#include <linux/ktime.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+#include <linux/soc/mediatek/scpsys-ext.h>
+
+#define MTK_POLL_DELAY_US 10
+#define MTK_POLL_TIMEOUT USEC_PER_SEC
+
+static int set_bus_protection(struct regmap *map, u32 mask, u32 ack_mask,
+ u32 reg_set, u32 reg_sta, u32 reg_en)
+{
+ u32 val;
+
+ if (reg_set)
+ regmap_write(map, reg_set, mask);
+ else
+ regmap_update_bits(map, reg_en, mask, mask);
+
+ return regmap_read_poll_timeout(map, reg_sta,
+ val, (val & ack_mask) == ack_mask,
+ MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+}
+
+static int clear_bus_protection(struct regmap *map, u32 mask, u32 ack_mask,
+ u32 reg_clr, u32 reg_sta, u32 reg_en)
+{
+ u32 val;
+
+ if (reg_clr)
+ regmap_write(map, reg_clr, mask);
+ else
+ regmap_update_bits(map, reg_en, mask, 0);
+
+ return regmap_read_poll_timeout(map, reg_sta,
+ val, !(val & ack_mask),
+ MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+}
+
+int mtk_scpsys_ext_set_bus_protection(const struct bus_prot *bp_table,
+ struct regmap *infracfg, struct regmap *smi_common)
+{
+ int i;
+
+ for (i = 0; i < MAX_STEPS; i++) {
+ struct regmap *map;
+ int ret;
+
+ if (bp_table[i].type == INVALID_TYPE)
+ continue;
+ else if (bp_table[i].type == IFR_TYPE)
+ map = infracfg;
+ else if (bp_table[i].type == SMI_TYPE)
+ map = smi_common;
+
+ ret = set_bus_protection(map,
+ bp_table[i].mask, bp_table[i].mask,
+ bp_table[i].set_ofs, bp_table[i].sta_ofs,
+ bp_table[i].en_ofs);
+
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+int mtk_scpsys_ext_clear_bus_protection(const struct bus_prot *bp_table,
+ struct regmap *infracfg, struct regmap *smi_common)
+{
+ int i;
+
+ for (i = MAX_STEPS - 1; i >= 0; i--) {
+ struct regmap *map;
+ int ret;
+
+ if (bp_table[i].type == INVALID_TYPE)
+ continue;
+ else if (bp_table[i].type == IFR_TYPE)
+ map = infracfg;
+ else if (bp_table[i].type == SMI_TYPE)
+ map = smi_common;
+
+ ret = clear_bus_protection(map,
+ bp_table[i].mask, bp_table[i].clr_ack_mask,
+ bp_table[i].clr_ofs, bp_table[i].sta_ofs,
+ bp_table[i].en_ofs);
+
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index d31e1a4..f25101f 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -12,6 +12,7 @@
#include <linux/pm_domain.h>
#include <linux/regulator/consumer.h>
#include <linux/soc/mediatek/infracfg.h>
+#include <linux/soc/mediatek/scpsys-ext.h>
#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/power/mt2712-power.h>
@@ -120,6 +121,7 @@ enum clk_id {
* @basic_clk_id: provide the same purpose with field "clk_id"
* by declaring basic clock prefix name rather than clk_id.
* @caps: The flag for active wake-up action.
+ * @bp_table: The mask table for multiple step bus protection.
*/
struct scp_domain_data {
const char *name;
@@ -131,6 +133,7 @@ struct scp_domain_data {
enum clk_id clk_id[MAX_CLKS];
const char *basic_clk_id[MAX_CLKS];
u8 caps;
+ struct bus_prot bp_table[MAX_STEPS];
};
struct scp;
@@ -154,6 +157,7 @@ struct scp {
struct device *dev;
void __iomem *base;
struct regmap *infracfg;
+ struct regmap *smi_common;
struct scp_ctrl_reg ctrl_reg;
bool bus_prot_reg_update;
};
@@ -281,24 +285,28 @@ static int scpsys_bus_protect_enable(struct scp_domain *scpd)
{
struct scp *scp = scpd->scp;
- if (!scpd->data->bus_prot_mask)
- return 0;
+ if (scpd->data->bus_prot_mask) {
+ return mtk_infracfg_set_bus_protection(scp->infracfg,
+ scpd->data->bus_prot_mask,
+ scp->bus_prot_reg_update);
+ }
- return mtk_infracfg_set_bus_protection(scp->infracfg,
- scpd->data->bus_prot_mask,
- scp->bus_prot_reg_update);
+ return mtk_scpsys_ext_set_bus_protection(scpd->data->bp_table,
+ scp->infracfg, scp->smi_common);
}
static int scpsys_bus_protect_disable(struct scp_domain *scpd)
{
struct scp *scp = scpd->scp;
- if (!scpd->data->bus_prot_mask)
- return 0;
+ if (scpd->data->bus_prot_mask) {
+ return mtk_infracfg_clear_bus_protection(scp->infracfg,
+ scpd->data->bus_prot_mask,
+ scp->bus_prot_reg_update);
+ }
- return mtk_infracfg_clear_bus_protection(scp->infracfg,
- scpd->data->bus_prot_mask,
- scp->bus_prot_reg_update);
+ return mtk_scpsys_ext_clear_bus_protection(scpd->data->bp_table,
+ scp->infracfg, scp->smi_common);
}
static int scpsys_power_on(struct generic_pm_domain *genpd)
@@ -466,6 +474,17 @@ static struct scp *init_scp(struct platform_device *pdev,
return ERR_CAST(scp->infracfg);
}
+ scp->smi_common = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+ "smi_comm");
+
+ if (scp->smi_common == ERR_PTR(-ENODEV)) {
+ scp->smi_common = NULL;
+ } else if (IS_ERR(scp->smi_common)) {
+ dev_err(&pdev->dev, "Cannot find smi_common controller: %ld\n",
+ PTR_ERR(scp->smi_common));
+ return ERR_CAST(scp->smi_common);
+ }
+
for (i = 0; i < num; i++) {
struct scp_domain *scpd = &scp->domains[i];
const struct scp_domain_data *data = &scp_domain_data[i];
diff --git a/include/linux/soc/mediatek/scpsys-ext.h b/include/linux/soc/mediatek/scpsys-ext.h
new file mode 100644
index 0000000..3e5b84d
--- /dev/null
+++ b/include/linux/soc/mediatek/scpsys-ext.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __SOC_MEDIATEK_SCPSYS_EXT_H
+#define __SOC_MEDIATEK_SCPSYS_EXT_H
+
+#define MAX_STEPS 4
+
+#define BUS_PROT(_type, _set_ofs, _clr_ofs, \
+ _en_ofs, _sta_ofs, _mask, _clr_ack_mask) { \
+ .type = _type, \
+ .set_ofs = _set_ofs, \
+ .clr_ofs = _clr_ofs, \
+ .en_ofs = _en_ofs, \
+ .sta_ofs = _sta_ofs, \
+ .mask = _mask, \
+ .clr_ack_mask = _clr_ack_mask, \
+ }
+
+enum regmap_type {
+ INVALID_TYPE = 0,
+ IFR_TYPE,
+ SMI_TYPE,
+};
+
+struct bus_prot {
+ enum regmap_type type;
+ u32 set_ofs;
+ u32 clr_ofs;
+ u32 en_ofs;
+ u32 sta_ofs;
+ u32 mask;
+ u32 clr_ack_mask;
+};
+
+int mtk_scpsys_ext_set_bus_protection(const struct bus_prot *bp_table,
+ struct regmap *infracfg, struct regmap *smi_common);
+int mtk_scpsys_ext_clear_bus_protection(const struct bus_prot *bp_table,
+ struct regmap *infracfg, struct regmap *smi_common);
+
+#endif /* __SOC_MEDIATEK_SCPSYS_EXT_H */
--
1.8.1.1.dirty
Put sram enable and disable control in separate functions.
Signed-off-by: Weiyi Lu <[email protected]>
Reviewed-by: Nicolas Boichat <[email protected]>
---
drivers/soc/mediatek/mtk-scpsys.c | 79 +++++++++++++++++++++++++--------------
1 file changed, 51 insertions(+), 28 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index 73e4a1a..ad0f619 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -230,12 +230,55 @@ static int scpsys_clk_enable(struct clk *clk[], int max_num)
return ret;
}
+static int scpsys_sram_enable(struct scp_domain *scpd, void __iomem *ctl_addr)
+{
+ u32 val;
+ u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
+ int tmp;
+
+ val = readl(ctl_addr) & ~scpd->data->sram_pdn_bits;
+ writel(val, ctl_addr);
+
+ /* Either wait until SRAM_PDN_ACK all 0 or have a force wait */
+ if (MTK_SCPD_CAPS(scpd, MTK_SCPD_FWAIT_SRAM)) {
+ /*
+ * Currently, MTK_SCPD_FWAIT_SRAM is necessary only for
+ * MT7622_POWER_DOMAIN_WB and thus just a trivial setup
+ * is applied here.
+ */
+ usleep_range(12000, 12100);
+ } else {
+ /* Either wait until SRAM_PDN_ACK all 1 or 0 */
+ int ret = readl_poll_timeout(ctl_addr, tmp,
+ (tmp & pdn_ack) == 0,
+ MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int scpsys_sram_disable(struct scp_domain *scpd, void __iomem *ctl_addr)
+{
+ u32 val;
+ u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
+ int tmp;
+
+ val = readl(ctl_addr) | scpd->data->sram_pdn_bits;
+ writel(val, ctl_addr);
+
+ /* Either wait until SRAM_PDN_ACK all 1 or 0 */
+ return readl_poll_timeout(ctl_addr, tmp,
+ (tmp & pdn_ack) == pdn_ack,
+ MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+}
+
static int scpsys_power_on(struct generic_pm_domain *genpd)
{
struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
struct scp *scp = scpd->scp;
void __iomem *ctl_addr = scp->base + scpd->data->ctl_offs;
- u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
u32 val;
int ret, tmp;
@@ -247,6 +290,7 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
if (ret)
goto err_clk;
+ /* subsys power on */
val = readl(ctl_addr);
val |= PWR_ON_BIT;
writel(val, ctl_addr);
@@ -268,24 +312,9 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
val |= PWR_RST_B_BIT;
writel(val, ctl_addr);
- val &= ~scpd->data->sram_pdn_bits;
- writel(val, ctl_addr);
-
- /* Either wait until SRAM_PDN_ACK all 0 or have a force wait */
- if (MTK_SCPD_CAPS(scpd, MTK_SCPD_FWAIT_SRAM)) {
- /*
- * Currently, MTK_SCPD_FWAIT_SRAM is necessary only for
- * MT7622_POWER_DOMAIN_WB and thus just a trivial setup is
- * applied here.
- */
- usleep_range(12000, 12100);
-
- } else {
- ret = readl_poll_timeout(ctl_addr, tmp, (tmp & pdn_ack) == 0,
- MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
- if (ret < 0)
- goto err_pwr_ack;
- }
+ ret = scpsys_sram_enable(scpd, ctl_addr);
+ if (ret < 0)
+ goto err_pwr_ack;
if (scpd->data->bus_prot_mask) {
ret = mtk_infracfg_clear_bus_protection(scp->infracfg,
@@ -312,7 +341,6 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
struct scp *scp = scpd->scp;
void __iomem *ctl_addr = scp->base + scpd->data->ctl_offs;
- u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
u32 val;
int ret, tmp;
@@ -324,17 +352,12 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
goto out;
}
- val = readl(ctl_addr);
- val |= scpd->data->sram_pdn_bits;
- writel(val, ctl_addr);
-
- /* wait until SRAM_PDN_ACK all 1 */
- ret = readl_poll_timeout(ctl_addr, tmp, (tmp & pdn_ack) == pdn_ack,
- MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+ ret = scpsys_sram_disable(scpd, ctl_addr);
if (ret < 0)
goto out;
- val |= PWR_ISO_BIT;
+ /* subsys power off */
+ val = readl(ctl_addr) | PWR_ISO_BIT;
writel(val, ctl_addr);
val &= ~PWR_RST_B_BIT;
--
1.8.1.1.dirty
For scpsys driver using regmap based syscon driver API.
Signed-off-by: Weiyi Lu <[email protected]>
---
.../devicetree/bindings/memory-controllers/mediatek,smi-common.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
index b478ade..01744ec 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
@@ -20,7 +20,7 @@ Required properties:
"mediatek,mt2712-smi-common"
"mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
"mediatek,mt8173-smi-common"
- "mediatek,mt8183-smi-common"
+ "mediatek,mt8183-smi-common", "syscon"
- reg : the register and size of the SMI block.
- power-domains : a phandle to the power domain of this local arbiter.
- clocks : Must contain an entry for each entry in clock-names.
--
1.8.1.1.dirty
Add subsys CG control flow before/after the bus protect control
due to bus protection need SMI bus relative CGs enabled to feedback
its ack.
Signed-off-by: Weiyi Lu <[email protected]>
---
drivers/soc/mediatek/mtk-scpsys.c | 72 +++++++++++++++++++++++++++++++++++++--
1 file changed, 70 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index f25101f..0b5055c 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -108,6 +108,7 @@ enum clk_id {
};
#define MAX_CLKS 3
+#define MAX_SUBSYS_CLKS 10
/**
* struct scp_domain_data - scp domain data for power on/off flow
@@ -120,6 +121,8 @@ enum clk_id {
* @clk_id: The basic clocks required by this power domain.
* @basic_clk_id: provide the same purpose with field "clk_id"
* by declaring basic clock prefix name rather than clk_id.
+ * @subsys_clk_prefix: The prefix name of the clocks need to be enabled
+ * before releasing bus protection.
* @caps: The flag for active wake-up action.
* @bp_table: The mask table for multiple step bus protection.
*/
@@ -132,6 +135,7 @@ struct scp_domain_data {
u32 bus_prot_mask;
enum clk_id clk_id[MAX_CLKS];
const char *basic_clk_id[MAX_CLKS];
+ const char *subsys_clk_prefix;
u8 caps;
struct bus_prot bp_table[MAX_STEPS];
};
@@ -142,6 +146,7 @@ struct scp_domain {
struct generic_pm_domain genpd;
struct scp *scp;
struct clk *clk[MAX_CLKS];
+ struct clk *subsys_clk[MAX_SUBSYS_CLKS];
const struct scp_domain_data *data;
struct regulator *supply;
};
@@ -347,16 +352,22 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
val |= PWR_RST_B_BIT;
writel(val, ctl_addr);
- ret = scpsys_sram_enable(scpd, ctl_addr);
+ ret = scpsys_clk_enable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
if (ret < 0)
goto err_pwr_ack;
+ ret = scpsys_sram_enable(scpd, ctl_addr);
+ if (ret < 0)
+ goto err_sram;
+
ret = scpsys_bus_protect_disable(scpd);
if (ret < 0)
- goto err_pwr_ack;
+ goto err_sram;
return 0;
+err_sram:
+ scpsys_clk_disable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
err_pwr_ack:
scpsys_clk_disable(scpd->clk, MAX_CLKS);
err_clk:
@@ -383,6 +394,8 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
if (ret < 0)
goto out;
+ scpsys_clk_disable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
+
/* subsys power off */
val = readl(ctl_addr) | PWR_ISO_BIT;
writel(val, ctl_addr);
@@ -419,6 +432,48 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
return ret;
}
+static int init_subsys_clks(struct platform_device *pdev,
+ const char *prefix, struct clk **clk)
+{
+ struct device_node *node = pdev->dev.of_node;
+ u32 prefix_len, sub_clk_cnt = 0;
+ struct property *prop;
+ const char *clk_name;
+
+ if (!node) {
+ dev_err(&pdev->dev, "Cannot find scpsys node: %ld\n",
+ PTR_ERR(node));
+ return PTR_ERR(node);
+ }
+
+ prefix_len = strlen(prefix);
+
+ of_property_for_each_string(node, "clock-names", prop, clk_name) {
+ if (!strncmp(clk_name, prefix, prefix_len) &&
+ (clk_name[prefix_len] == '-')) {
+ if (sub_clk_cnt >= MAX_SUBSYS_CLKS) {
+ dev_err(&pdev->dev,
+ "subsys clk out of range %d\n",
+ sub_clk_cnt);
+ return -ENOMEM;
+ }
+
+ clk[sub_clk_cnt] = devm_clk_get(&pdev->dev,
+ clk_name);
+
+ if (IS_ERR(clk[sub_clk_cnt])) {
+ dev_err(&pdev->dev,
+ "Subsys clk get fail %ld\n",
+ PTR_ERR(clk[sub_clk_cnt]));
+ return PTR_ERR(clk[sub_clk_cnt]);
+ }
+ sub_clk_cnt++;
+ }
+ }
+
+ return sub_clk_cnt;
+}
+
static void init_clks(struct platform_device *pdev, struct clk **clk)
{
int i;
@@ -506,6 +561,7 @@ static struct scp *init_scp(struct platform_device *pdev,
struct scp_domain *scpd = &scp->domains[i];
struct generic_pm_domain *genpd = &scpd->genpd;
const struct scp_domain_data *data = &scp_domain_data[i];
+ int clk_cnt;
pd_data->domains[i] = genpd;
scpd->scp = scp;
@@ -534,6 +590,18 @@ static struct scp *init_scp(struct platform_device *pdev,
data->basic_clk_id[j]);
}
+ if (data->subsys_clk_prefix) {
+ clk_cnt = init_subsys_clks(pdev,
+ data->subsys_clk_prefix,
+ scpd->subsys_clk);
+ if (clk_cnt < 0) {
+ dev_err(&pdev->dev,
+ "%s: subsys clk unavailable\n",
+ data->name);
+ return ERR_PTR(clk_cnt);
+ }
+ }
+
genpd->name = data->name;
genpd->power_off = scpsys_power_off;
genpd->power_on = scpsys_power_on;
--
1.8.1.1.dirty
Put bus protection enable and disable control in separate functions.
Signed-off-by: Weiyi Lu <[email protected]>
---
drivers/soc/mediatek/mtk-scpsys.c | 44 ++++++++++++++++++++++++++-------------
1 file changed, 30 insertions(+), 14 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index ad0f619..fb2b027 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -274,6 +274,30 @@ static int scpsys_sram_disable(struct scp_domain *scpd, void __iomem *ctl_addr)
MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
}
+static int scpsys_bus_protect_enable(struct scp_domain *scpd)
+{
+ struct scp *scp = scpd->scp;
+
+ if (!scpd->data->bus_prot_mask)
+ return 0;
+
+ return mtk_infracfg_set_bus_protection(scp->infracfg,
+ scpd->data->bus_prot_mask,
+ scp->bus_prot_reg_update);
+}
+
+static int scpsys_bus_protect_disable(struct scp_domain *scpd)
+{
+ struct scp *scp = scpd->scp;
+
+ if (!scpd->data->bus_prot_mask)
+ return 0;
+
+ return mtk_infracfg_clear_bus_protection(scp->infracfg,
+ scpd->data->bus_prot_mask,
+ scp->bus_prot_reg_update);
+}
+
static int scpsys_power_on(struct generic_pm_domain *genpd)
{
struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
@@ -316,13 +340,9 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
if (ret < 0)
goto err_pwr_ack;
- if (scpd->data->bus_prot_mask) {
- ret = mtk_infracfg_clear_bus_protection(scp->infracfg,
- scpd->data->bus_prot_mask,
- scp->bus_prot_reg_update);
- if (ret)
- goto err_pwr_ack;
- }
+ ret = scpsys_bus_protect_disable(scpd);
+ if (ret < 0)
+ goto err_pwr_ack;
return 0;
@@ -344,13 +364,9 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
u32 val;
int ret, tmp;
- if (scpd->data->bus_prot_mask) {
- ret = mtk_infracfg_set_bus_protection(scp->infracfg,
- scpd->data->bus_prot_mask,
- scp->bus_prot_reg_update);
- if (ret)
- goto out;
- }
+ ret = scpsys_bus_protect_enable(scpd);
+ if (ret < 0)
+ goto out;
ret = scpsys_sram_disable(scpd, ctl_addr);
if (ret < 0)
--
1.8.1.1.dirty
mfgcfg clock is under MFG_ASYNC power domain
Signed-off-by: Weiyi Lu <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 6cbbd77..7e23179 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -634,6 +634,7 @@
compatible = "mediatek,mt8183-mfgcfg", "syscon";
reg = <0 0x13000000 0 0x1000>;
#clock-cells = <1>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_MFG_ASYNC>;
};
mmsys: syscon@14000000 {
--
1.8.1.1.dirty
Add scpsys driver for MT8183
Signed-off-by: Weiyi Lu <[email protected]>
---
drivers/soc/mediatek/mtk-scpsys.c | 226 ++++++++++++++++++++++++++++++++++++++
1 file changed, 226 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index 992e5b3..eb828d9 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -20,6 +20,7 @@
#include <dt-bindings/power/mt7622-power.h>
#include <dt-bindings/power/mt7623a-power.h>
#include <dt-bindings/power/mt8173-power.h>
+#include <dt-bindings/power/mt8183-power.h>
#define MTK_POLL_DELAY_US 10
#define MTK_POLL_TIMEOUT USEC_PER_SEC
@@ -1129,6 +1130,217 @@ static void mtk_register_power_domains(struct platform_device *pdev,
{MT8173_POWER_DOMAIN_MFG_2D, MT8173_POWER_DOMAIN_MFG},
};
+/*
+ * MT8183 power domain support
+ */
+
+static const struct scp_domain_data scp_domain_data_mt8183[] = {
+ [MT8183_POWER_DOMAIN_AUDIO] = {
+ .name = "audio",
+ .sta_mask = PWR_STATUS_AUDIO,
+ .ctl_offs = 0x0314,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .basic_clk_id = {"audio", "audio1", "audio2"},
+ },
+ [MT8183_POWER_DOMAIN_CONN] = {
+ .name = "conn",
+ .sta_mask = PWR_STATUS_CONN,
+ .ctl_offs = 0x032c,
+ .sram_pdn_bits = 0,
+ .sram_pdn_ack_bits = 0,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228,
+ BIT(13) | BIT(14), BIT(13) | BIT(14)),
+ },
+ },
+ [MT8183_POWER_DOMAIN_MFG_ASYNC] = {
+ .name = "mfg_async",
+ .sta_mask = PWR_STATUS_MFG_ASYNC,
+ .ctl_offs = 0x0334,
+ .sram_pdn_bits = 0,
+ .sram_pdn_ack_bits = 0,
+ .basic_clk_id = {"mfg"},
+ },
+ [MT8183_POWER_DOMAIN_MFG] = {
+ .name = "mfg",
+ .sta_mask = PWR_STATUS_MFG,
+ .ctl_offs = 0x0338,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT8183_POWER_DOMAIN_MFG_CORE0] = {
+ .name = "mfg_core0",
+ .sta_mask = BIT(7),
+ .ctl_offs = 0x034c,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT8183_POWER_DOMAIN_MFG_CORE1] = {
+ .name = "mfg_core1",
+ .sta_mask = BIT(20),
+ .ctl_offs = 0x0310,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT8183_POWER_DOMAIN_MFG_2D] = {
+ .name = "mfg_2d",
+ .sta_mask = PWR_STATUS_MFG_2D,
+ .ctl_offs = 0x0348,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2a8, 0x2ac, 0, 0x258,
+ BIT(19) | BIT(20) | BIT(21),
+ BIT(19) | BIT(20) | BIT(21)),
+ BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228,
+ BIT(21) | BIT(22), BIT(21) | BIT(22)),
+ },
+ },
+ [MT8183_POWER_DOMAIN_DISP] = {
+ .name = "disp",
+ .sta_mask = PWR_STATUS_DISP,
+ .ctl_offs = 0x030c,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .basic_clk_id = {"mm"},
+ .subsys_clk_prefix = "mm",
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2a8, 0x2ac, 0, 0x258,
+ BIT(16) | BIT(17), BIT(16) | BIT(17)),
+ BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228,
+ BIT(10) | BIT(11), BIT(10) | BIT(11)),
+ BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
+ GENMASK(7, 0), GENMASK(7, 0)),
+ },
+ },
+ [MT8183_POWER_DOMAIN_CAM] = {
+ .name = "cam",
+ .sta_mask = BIT(25),
+ .ctl_offs = 0x0344,
+ .sram_pdn_bits = GENMASK(9, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .basic_clk_id = {"cam"},
+ .subsys_clk_prefix = "cam",
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
+ BIT(4) | BIT(5) | BIT(9) | BIT(13),
+ BIT(4) | BIT(5) | BIT(9) | BIT(13)),
+ BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228,
+ BIT(28), BIT(28)),
+ BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
+ BIT(11), 0),
+ BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
+ BIT(3) | BIT(4), BIT(3) | BIT(4)),
+ },
+ },
+ [MT8183_POWER_DOMAIN_ISP] = {
+ .name = "isp",
+ .sta_mask = PWR_STATUS_ISP,
+ .ctl_offs = 0x0308,
+ .sram_pdn_bits = GENMASK(9, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .basic_clk_id = {"isp"},
+ .subsys_clk_prefix = "isp",
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
+ BIT(3) | BIT(8), BIT(3) | BIT(8)),
+ BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
+ BIT(10), 0),
+ BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
+ BIT(2), BIT(2)),
+ },
+ },
+ [MT8183_POWER_DOMAIN_VDEC] = {
+ .name = "vdec",
+ .sta_mask = BIT(31),
+ .ctl_offs = 0x0300,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_table = {
+ BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
+ BIT(7), BIT(7)),
+ },
+ },
+ [MT8183_POWER_DOMAIN_VENC] = {
+ .name = "venc",
+ .sta_mask = PWR_STATUS_VENC,
+ .ctl_offs = 0x0304,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .bp_table = {
+ BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
+ BIT(1), BIT(1)),
+ },
+ },
+ [MT8183_POWER_DOMAIN_VPU_TOP] = {
+ .name = "vpu_top",
+ .sta_mask = BIT(26),
+ .ctl_offs = 0x0324,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .basic_clk_id = {"vpu", "vpu1"},
+ .subsys_clk_prefix = "vpu",
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
+ GENMASK(9, 6) | BIT(12),
+ GENMASK(9, 6) | BIT(12)),
+ BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228,
+ BIT(27), BIT(27)),
+ BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
+ BIT(10) | BIT(11), BIT(10) | BIT(11)),
+ BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
+ BIT(5) | BIT(6), BIT(5) | BIT(6)),
+ },
+ },
+ [MT8183_POWER_DOMAIN_VPU_CORE0] = {
+ .name = "vpu_core0",
+ .sta_mask = BIT(27),
+ .ctl_offs = 0x33c,
+ .sram_iso_ctrl = true,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .basic_clk_id = {"vpu2"},
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4,
+ BIT(6), BIT(6)),
+ BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4,
+ BIT(0) | BIT(2) | BIT(4),
+ BIT(0) | BIT(2) | BIT(4)),
+ },
+ },
+ [MT8183_POWER_DOMAIN_VPU_CORE1] = {
+ .name = "vpu_core1",
+ .sta_mask = BIT(28),
+ .ctl_offs = 0x0340,
+ .sram_iso_ctrl = true,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .basic_clk_id = {"vpu3"},
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4,
+ BIT(7), BIT(7)),
+ BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4,
+ BIT(1) | BIT(3) | BIT(5),
+ BIT(1) | BIT(3) | BIT(5)),
+ },
+ },
+};
+
+static const struct scp_subdomain scp_subdomain_mt8183[] = {
+ {MT8183_POWER_DOMAIN_MFG_ASYNC, MT8183_POWER_DOMAIN_MFG},
+ {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_2D},
+ {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_CORE0},
+ {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_CORE1},
+ {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_CAM},
+ {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_ISP},
+ {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VDEC},
+ {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VENC},
+ {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VPU_TOP},
+ {MT8183_POWER_DOMAIN_VPU_TOP, MT8183_POWER_DOMAIN_VPU_CORE0},
+ {MT8183_POWER_DOMAIN_VPU_TOP, MT8183_POWER_DOMAIN_VPU_CORE1},
+};
+
static const struct scp_soc_data mt2701_data = {
.domains = scp_domain_data_mt2701,
.num_domains = ARRAY_SIZE(scp_domain_data_mt2701),
@@ -1195,6 +1407,17 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.bus_prot_reg_update = true,
};
+static const struct scp_soc_data mt8183_data = {
+ .domains = scp_domain_data_mt8183,
+ .num_domains = ARRAY_SIZE(scp_domain_data_mt8183),
+ .subdomains = scp_subdomain_mt8183,
+ .num_subdomains = ARRAY_SIZE(scp_subdomain_mt8183),
+ .regs = {
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184
+ }
+};
+
/*
* scpsys driver init
*/
@@ -1219,6 +1442,9 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.compatible = "mediatek,mt8173-scpsys",
.data = &mt8173_data,
}, {
+ .compatible = "mediatek,mt8183-scpsys",
+ .data = &mt8183_data,
+ }, {
/* sentinel */
}
};
--
1.8.1.1.dirty
For some power domains like vpu_core on MT8183 whose sram need to
do clock and internal isolation while power on/off sram.
We add a flag "sram_iso_ctrl" in scp_domain_data to judge if we
need to do the extra sram isolation control or not.
Signed-off-by: Weiyi Lu <[email protected]>
---
drivers/soc/mediatek/mtk-scpsys.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index 0b5055c..992e5b3 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -57,6 +57,8 @@
#define PWR_ON_BIT BIT(2)
#define PWR_ON_2ND_BIT BIT(3)
#define PWR_CLK_DIS_BIT BIT(4)
+#define PWR_SRAM_CLKISO_BIT BIT(5)
+#define PWR_SRAM_ISOINT_B_BIT BIT(6)
#define PWR_STATUS_CONN BIT(1)
#define PWR_STATUS_DISP BIT(3)
@@ -115,6 +117,8 @@ enum clk_id {
* @name: The domain name.
* @sta_mask: The mask for power on/off status bit.
* @ctl_offs: The offset for main power control register.
+ * @sram_iso_ctrl: The flag to judge if the power domain need to do
+ * the extra sram isolation control.
* @sram_pdn_bits: The mask for sram power control bits.
* @sram_pdn_ack_bits: The mask for sram power control acked bits.
* @bus_prot_mask: The mask for single step bus protection.
@@ -130,6 +134,7 @@ struct scp_domain_data {
const char *name;
u32 sta_mask;
int ctl_offs;
+ bool sram_iso_ctrl;
u32 sram_pdn_bits;
u32 sram_pdn_ack_bits;
u32 bus_prot_mask;
@@ -268,6 +273,14 @@ static int scpsys_sram_enable(struct scp_domain *scpd, void __iomem *ctl_addr)
return ret;
}
+ if (scpd->data->sram_iso_ctrl) {
+ val = readl(ctl_addr) | PWR_SRAM_ISOINT_B_BIT;
+ writel(val, ctl_addr);
+ udelay(1);
+ val &= ~PWR_SRAM_CLKISO_BIT;
+ writel(val, ctl_addr);
+ }
+
return 0;
}
@@ -277,6 +290,15 @@ static int scpsys_sram_disable(struct scp_domain *scpd, void __iomem *ctl_addr)
u32 pdn_ack = scpd->data->sram_pdn_ack_bits;
int tmp;
+ if (scpd->data->sram_iso_ctrl) {
+ val = readl(ctl_addr);
+ val |= PWR_SRAM_CLKISO_BIT;
+ writel(val, ctl_addr);
+ val &= ~PWR_SRAM_ISOINT_B_BIT;
+ writel(val, ctl_addr);
+ udelay(1);
+ }
+
val = readl(ctl_addr) | scpd->data->sram_pdn_bits;
writel(val, ctl_addr);
--
1.8.1.1.dirty
Add power dt-bindings of MT8183 and introduces "BASIC" and
"SUBSYS" clock types in binding document.
The "BASIC" type is compatible to the original power control with
clock name [a-z]+[0-9]*, e.g. mm, vpu1.
The "SUBSYS" type is used for bus protection control with clock
name [a-z]+-[0-9]+, e.g. isp-0, cam-1.
Signed-off-by: Weiyi Lu <[email protected]>
---
.../devicetree/bindings/soc/mediatek/scpsys.txt | 20 ++++++++++++++---
include/dt-bindings/power/mt8183-power.h | 26 ++++++++++++++++++++++
2 files changed, 43 insertions(+), 3 deletions(-)
create mode 100644 include/dt-bindings/power/mt8183-power.h
diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
index 876693a..ee9df27 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -14,6 +14,7 @@ power/power_domain.txt. It provides the power domains defined in
- include/dt-bindings/power/mt2701-power.h
- include/dt-bindings/power/mt2712-power.h
- include/dt-bindings/power/mt7622-power.h
+- include/dt-bindings/power/mt8183-power.h
Required properties:
- compatible: Should be one of:
@@ -25,18 +26,31 @@ Required properties:
- "mediatek,mt7623a-scpsys": For MT7623A SoC
- "mediatek,mt7629-scpsys", "mediatek,mt7622-scpsys": For MT7629 SoC
- "mediatek,mt8173-scpsys"
+ - "mediatek,mt8183-scpsys"
- #power-domain-cells: Must be 1
- reg: Address range of the SCPSYS unit
- infracfg: must contain a phandle to the infracfg controller
-- clock, clock-names: clocks according to the common clock binding.
- These are clocks which hardware needs to be
- enabled before enabling certain power domains.
+- clock, clock-names: Clocks according to the common clock binding.
+ Some SoCs have to groups of clocks.
+ BASIC clocks need to be enabled before enabling the
+ corresponding power domain.
+ SUBSYS clocks need to be enabled before releasing the
+ bus protection.
Required clocks for MT2701 or MT7623: "mm", "mfg", "ethif"
Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec"
Required clocks for MT6797: "mm", "mfg", "vdec"
Required clocks for MT7622 or MT7629: "hif_sel"
Required clocks for MT7623A: "ethif"
Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
+ Required clocks for MT8183: BASIC: "audio", "mfg", "mm", "cam", "isp",
+ "vpu", "vpu1", "vpu2", "vpu3"
+ SUBSYS: "mm-0", "mm-1", "mm-2", "mm-3",
+ "mm-4", "mm-5", "mm-6", "mm-7",
+ "mm-8", "mm-9", "isp-0", "isp-1",
+ "cam-0", "cam-1", "cam-2", "cam-3",
+ "cam-4", "cam-5", "cam-6", "vpu-0",
+ "vpu-1", "vpu-2", "vpu-3", "vpu-4",
+ "vpu-5"
Optional properties:
- vdec-supply: Power supply for the vdec power domain
diff --git a/include/dt-bindings/power/mt8183-power.h b/include/dt-bindings/power/mt8183-power.h
new file mode 100644
index 0000000..5c0c8c7
--- /dev/null
+++ b/include/dt-bindings/power/mt8183-power.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Weiyi Lu <[email protected]>
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT8183_POWER_H
+#define _DT_BINDINGS_POWER_MT8183_POWER_H
+
+#define MT8183_POWER_DOMAIN_AUDIO 0
+#define MT8183_POWER_DOMAIN_CONN 1
+#define MT8183_POWER_DOMAIN_MFG_ASYNC 2
+#define MT8183_POWER_DOMAIN_MFG 3
+#define MT8183_POWER_DOMAIN_MFG_CORE0 4
+#define MT8183_POWER_DOMAIN_MFG_CORE1 5
+#define MT8183_POWER_DOMAIN_MFG_2D 6
+#define MT8183_POWER_DOMAIN_DISP 7
+#define MT8183_POWER_DOMAIN_CAM 8
+#define MT8183_POWER_DOMAIN_ISP 9
+#define MT8183_POWER_DOMAIN_VDEC 10
+#define MT8183_POWER_DOMAIN_VENC 11
+#define MT8183_POWER_DOMAIN_VPU_TOP 12
+#define MT8183_POWER_DOMAIN_VPU_CORE0 13
+#define MT8183_POWER_DOMAIN_VPU_CORE1 14
+
+#endif /* _DT_BINDINGS_POWER_MT8183_POWER_H */
--
1.8.1.1.dirty
Add power controller node and smi-common node for MT8183
In scpsys node, it contains clocks and regmapping of
infracfg and smi-common for bus protection.
Signed-off-by: Weiyi Lu <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 62 ++++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 97f84aa..6cbbd77 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/mt8183-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/power/mt8183-power.h>
#include "mt8183-pinfunc.h"
/ {
@@ -253,6 +254,62 @@
#interrupt-cells = <2>;
};
+ scpsys: syscon@10006000 {
+ compatible = "mediatek,mt8183-scpsys", "syscon";
+ #power-domain-cells = <1>;
+ reg = <0 0x10006000 0 0x1000>;
+ clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
+ <&infracfg CLK_INFRA_AUDIO>,
+ <&infracfg CLK_INFRA_AUDIO_26M_BCLK>,
+ <&topckgen CLK_TOP_MUX_MFG>,
+ <&topckgen CLK_TOP_MUX_MM>,
+ <&topckgen CLK_TOP_MUX_CAM>,
+ <&topckgen CLK_TOP_MUX_IMG>,
+ <&topckgen CLK_TOP_MUX_IPU_IF>,
+ <&topckgen CLK_TOP_MUX_DSP>,
+ <&topckgen CLK_TOP_MUX_DSP1>,
+ <&topckgen CLK_TOP_MUX_DSP2>,
+ <&mmsys CLK_MM_SMI_COMMON>,
+ <&mmsys CLK_MM_SMI_LARB0>,
+ <&mmsys CLK_MM_SMI_LARB1>,
+ <&mmsys CLK_MM_GALS_COMM0>,
+ <&mmsys CLK_MM_GALS_COMM1>,
+ <&mmsys CLK_MM_GALS_CCU2MM>,
+ <&mmsys CLK_MM_GALS_IPU12MM>,
+ <&mmsys CLK_MM_GALS_IMG2MM>,
+ <&mmsys CLK_MM_GALS_CAM2MM>,
+ <&mmsys CLK_MM_GALS_IPU2MM>,
+ <&imgsys CLK_IMG_LARB5>,
+ <&imgsys CLK_IMG_LARB2>,
+ <&camsys CLK_CAM_LARB6>,
+ <&camsys CLK_CAM_LARB3>,
+ <&camsys CLK_CAM_SENINF>,
+ <&camsys CLK_CAM_CAMSV0>,
+ <&camsys CLK_CAM_CAMSV1>,
+ <&camsys CLK_CAM_CAMSV2>,
+ <&camsys CLK_CAM_CCU>,
+ <&ipu_conn CLK_IPU_CONN_IPU>,
+ <&ipu_conn CLK_IPU_CONN_AHB>,
+ <&ipu_conn CLK_IPU_CONN_AXI>,
+ <&ipu_conn CLK_IPU_CONN_ISP>,
+ <&ipu_conn CLK_IPU_CONN_CAM_ADL>,
+ <&ipu_conn CLK_IPU_CONN_IMG_ADL>;
+ clock-names = "audio", "audio1", "audio2",
+ "mfg", "mm", "cam",
+ "isp", "vpu", "vpu1",
+ "vpu2", "vpu3", "mm-0",
+ "mm-1", "mm-2", "mm-3",
+ "mm-4", "mm-5", "mm-6",
+ "mm-7", "mm-8", "mm-9",
+ "isp-0", "isp-1", "cam-0",
+ "cam-1", "cam-2", "cam-3",
+ "cam-4", "cam-5", "cam-6",
+ "vpu-0", "vpu-1", "vpu-2",
+ "vpu-3", "vpu-4", "vpu-5";
+ infracfg = <&infracfg>;
+ smi_comm = <&smi_common>;
+ };
+
apmixedsys: syscon@1000c000 {
compatible = "mediatek,mt8183-apmixedsys", "syscon";
reg = <0 0x1000c000 0 0x1000>;
@@ -585,6 +642,11 @@
#clock-cells = <1>;
};
+ smi_common: smi@14019000 {
+ compatible = "mediatek,mt8183-smi-common", "syscon";
+ reg = <0 0x14019000 0 0x1000>;
+ };
+
imgsys: syscon@15020000 {
compatible = "mediatek,mt8183-imgsys", "syscon";
reg = <0 0x15020000 0 0x1000>;
--
1.8.1.1.dirty
Use USEC_PER_SEC to indicate the polling timeout directly.
And add documentation of scp_domain_data.
Signed-off-by: Weiyi Lu <[email protected]>
---
drivers/soc/mediatek/mtk-scpsys.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index 503222d..e97fc0e 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -21,7 +21,7 @@
#include <dt-bindings/power/mt8173-power.h>
#define MTK_POLL_DELAY_US 10
-#define MTK_POLL_TIMEOUT (jiffies_to_usecs(HZ))
+#define MTK_POLL_TIMEOUT USEC_PER_SEC
#define MTK_SCPD_ACTIVE_WAKEUP BIT(0)
#define MTK_SCPD_FWAIT_SRAM BIT(1)
@@ -108,6 +108,17 @@ enum clk_id {
#define MAX_CLKS 3
+/**
+ * struct scp_domain_data - scp domain data for power on/off flow
+ * @name: The domain name.
+ * @sta_mask: The mask for power on/off status bit.
+ * @ctl_offs: The offset for main power control register.
+ * @sram_pdn_bits: The mask for sram power control bits.
+ * @sram_pdn_ack_bits: The mask for sram power control acked bits.
+ * @bus_prot_mask: The mask for single step bus protection.
+ * @clk_id: The basic clocks required by this power domain.
+ * @caps: The flag for active wake-up action.
+ */
struct scp_domain_data {
const char *name;
u32 sta_mask;
--
1.8.1.1.dirty
Put regulator enable and disable control in separate functions.
Signed-off-by: Weiyi Lu <[email protected]>
---
drivers/soc/mediatek/mtk-scpsys.c | 32 +++++++++++++++++++++++---------
1 file changed, 23 insertions(+), 9 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index e97fc0e..aed540d 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -191,6 +191,22 @@ static int scpsys_domain_is_on(struct scp_domain *scpd)
return -EINVAL;
}
+static int scpsys_regulator_enable(struct scp_domain *scpd)
+{
+ if (!scpd->supply)
+ return 0;
+
+ return regulator_enable(scpd->supply);
+}
+
+static int scpsys_regulator_disable(struct scp_domain *scpd)
+{
+ if (!scpd->supply)
+ return 0;
+
+ return regulator_disable(scpd->supply);
+}
+
static int scpsys_power_on(struct generic_pm_domain *genpd)
{
struct scp_domain *scpd = container_of(genpd, struct scp_domain, genpd);
@@ -201,11 +217,9 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
int ret, tmp;
int i;
- if (scpd->supply) {
- ret = regulator_enable(scpd->supply);
- if (ret)
- return ret;
- }
+ ret = scpsys_regulator_enable(scpd);
+ if (ret < 0)
+ return ret;
for (i = 0; i < MAX_CLKS && scpd->clk[i]; i++) {
ret = clk_prepare_enable(scpd->clk[i]);
@@ -273,8 +287,7 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
clk_disable_unprepare(scpd->clk[i]);
}
err_clk:
- if (scpd->supply)
- regulator_disable(scpd->supply);
+ scpsys_regulator_disable(scpd);
dev_err(scp->dev, "Failed to power on domain %s\n", genpd->name);
@@ -333,8 +346,9 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
for (i = 0; i < MAX_CLKS && scpd->clk[i]; i++)
clk_disable_unprepare(scpd->clk[i]);
- if (scpd->supply)
- regulator_disable(scpd->supply);
+ ret = scpsys_regulator_disable(scpd);
+ if (ret < 0)
+ goto out;
return 0;
--
1.8.1.1.dirty
Hi Weiyi,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[also build test WARNING on v5.4-rc5 next-20191029]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Weiyi-Lu/Mediatek-MT8183-scpsys-support/20191030-060526
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 23fdb198ae81f47a574296dab5167c5e136a02ba
config: mips-allmodconfig (attached as .config)
compiler: mips-linux-gcc (GCC) 7.4.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=7.4.0 make.cross ARCH=mips
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <[email protected]>
Note: it may well be a FALSE warning. FWIW you are at least aware of it now.
http://gcc.gnu.org/wiki/Better_Uninitialized_Warnings
All warnings (new ones prefixed by >>):
In file included from drivers/soc/mediatek/mtk-scpsys-ext.c:9:0:
drivers/soc/mediatek/mtk-scpsys-ext.c: In function 'mtk_scpsys_ext_set_bus_protection':
>> include/linux/regmap.h:131:9: warning: 'map' may be used uninitialized in this function [-Wmaybe-uninitialized]
__ret = regmap_read((map), (addr), &(val)); \
^
drivers/soc/mediatek/mtk-scpsys-ext.c:51:18: note: 'map' was declared here
struct regmap *map;
^~~
In file included from drivers/soc/mediatek/mtk-scpsys-ext.c:9:0:
drivers/soc/mediatek/mtk-scpsys-ext.c: In function 'mtk_scpsys_ext_clear_bus_protection':
>> include/linux/regmap.h:131:9: warning: 'map' may be used uninitialized in this function [-Wmaybe-uninitialized]
__ret = regmap_read((map), (addr), &(val)); \
^
drivers/soc/mediatek/mtk-scpsys-ext.c:79:18: note: 'map' was declared here
struct regmap *map;
^~~
--
In file included from drivers/soc//mediatek/mtk-scpsys-ext.c:9:0:
drivers/soc//mediatek/mtk-scpsys-ext.c: In function 'mtk_scpsys_ext_set_bus_protection':
>> include/linux/regmap.h:131:9: warning: 'map' may be used uninitialized in this function [-Wmaybe-uninitialized]
__ret = regmap_read((map), (addr), &(val)); \
^
drivers/soc//mediatek/mtk-scpsys-ext.c:51:18: note: 'map' was declared here
struct regmap *map;
^~~
In file included from drivers/soc//mediatek/mtk-scpsys-ext.c:9:0:
drivers/soc//mediatek/mtk-scpsys-ext.c: In function 'mtk_scpsys_ext_clear_bus_protection':
>> include/linux/regmap.h:131:9: warning: 'map' may be used uninitialized in this function [-Wmaybe-uninitialized]
__ret = regmap_read((map), (addr), &(val)); \
^
drivers/soc//mediatek/mtk-scpsys-ext.c:79:18: note: 'map' was declared here
struct regmap *map;
^~~
vim +/map +131 include/linux/regmap.h
8019ff6cfc0440 Nariman Poushin 2015-07-16 73
ca7a94464b5457 Kuninori Morimoto 2016-02-15 74 #define regmap_update_bits(map, reg, mask, val) \
ca7a94464b5457 Kuninori Morimoto 2016-02-15 75 regmap_update_bits_base(map, reg, mask, val, NULL, false, false)
30ed9cb7a49b49 Kuninori Morimoto 2016-02-15 76 #define regmap_update_bits_async(map, reg, mask, val)\
30ed9cb7a49b49 Kuninori Morimoto 2016-02-15 77 regmap_update_bits_base(map, reg, mask, val, NULL, true, false)
98c2dc48694a47 Kuninori Morimoto 2016-02-15 78 #define regmap_update_bits_check(map, reg, mask, val, change)\
98c2dc48694a47 Kuninori Morimoto 2016-02-15 79 regmap_update_bits_base(map, reg, mask, val, change, false, false)
89d8d4b833b0b2 Kuninori Morimoto 2016-02-15 80 #define regmap_update_bits_check_async(map, reg, mask, val, change)\
89d8d4b833b0b2 Kuninori Morimoto 2016-02-15 81 regmap_update_bits_base(map, reg, mask, val, change, true, false)
ca7a94464b5457 Kuninori Morimoto 2016-02-15 82
b821957a5ae769 Kuninori Morimoto 2016-03-03 83 #define regmap_write_bits(map, reg, mask, val) \
b821957a5ae769 Kuninori Morimoto 2016-03-03 84 regmap_update_bits_base(map, reg, mask, val, NULL, false, true)
b821957a5ae769 Kuninori Morimoto 2016-03-03 85
3674124b358946 Kuninori Morimoto 2016-02-15 86 #define regmap_field_write(field, val) \
3674124b358946 Kuninori Morimoto 2016-02-15 87 regmap_field_update_bits_base(field, ~0, val, NULL, false, false)
489061bba6c655 Kuninori Morimoto 2016-02-15 88 #define regmap_field_force_write(field, val) \
489061bba6c655 Kuninori Morimoto 2016-02-15 89 regmap_field_update_bits_base(field, ~0, val, NULL, false, true)
721ed64dda3774 Kuninori Morimoto 2016-02-15 90 #define regmap_field_update_bits(field, mask, val)\
721ed64dda3774 Kuninori Morimoto 2016-02-15 91 regmap_field_update_bits_base(field, mask, val, NULL, false, false)
489061bba6c655 Kuninori Morimoto 2016-02-15 92 #define regmap_field_force_update_bits(field, mask, val) \
489061bba6c655 Kuninori Morimoto 2016-02-15 93 regmap_field_update_bits_base(field, mask, val, NULL, false, true)
3674124b358946 Kuninori Morimoto 2016-02-15 94
bbf2c46f46e23a Kuninori Morimoto 2016-02-15 95 #define regmap_fields_write(field, id, val) \
bbf2c46f46e23a Kuninori Morimoto 2016-02-15 96 regmap_fields_update_bits_base(field, id, ~0, val, NULL, false, false)
e6ef243fa4660f Kuninori Morimoto 2016-02-15 97 #define regmap_fields_force_write(field, id, val) \
e6ef243fa4660f Kuninori Morimoto 2016-02-15 98 regmap_fields_update_bits_base(field, id, ~0, val, NULL, false, true)
48138609135fc9 Kuninori Morimoto 2016-02-15 99 #define regmap_fields_update_bits(field, id, mask, val)\
48138609135fc9 Kuninori Morimoto 2016-02-15 100 regmap_fields_update_bits_base(field, id, mask, val, NULL, false, false)
e6ef243fa4660f Kuninori Morimoto 2016-02-15 101 #define regmap_fields_force_update_bits(field, id, mask, val) \
e6ef243fa4660f Kuninori Morimoto 2016-02-15 102 regmap_fields_update_bits_base(field, id, mask, val, NULL, false, true)
bbf2c46f46e23a Kuninori Morimoto 2016-02-15 103
08188ba8822163 Philipp Zabel 2016-07-06 104 /**
08188ba8822163 Philipp Zabel 2016-07-06 105 * regmap_read_poll_timeout - Poll until a condition is met or a timeout occurs
2cf8e2dfdf8836 Charles Keepax 2017-01-12 106 *
08188ba8822163 Philipp Zabel 2016-07-06 107 * @map: Regmap to read from
08188ba8822163 Philipp Zabel 2016-07-06 108 * @addr: Address to poll
08188ba8822163 Philipp Zabel 2016-07-06 109 * @val: Unsigned integer variable to read the value into
08188ba8822163 Philipp Zabel 2016-07-06 110 * @cond: Break condition (usually involving @val)
08188ba8822163 Philipp Zabel 2016-07-06 111 * @sleep_us: Maximum time to sleep between reads in us (0
08188ba8822163 Philipp Zabel 2016-07-06 112 * tight-loops). Should be less than ~20ms since usleep_range
458f69ef36656d Mauro Carvalho Chehab 2019-06-12 113 * is used (see Documentation/timers/timers-howto.rst).
08188ba8822163 Philipp Zabel 2016-07-06 114 * @timeout_us: Timeout in us, 0 means never timeout
08188ba8822163 Philipp Zabel 2016-07-06 115 *
08188ba8822163 Philipp Zabel 2016-07-06 116 * Returns 0 on success and -ETIMEDOUT upon a timeout or the regmap_read
08188ba8822163 Philipp Zabel 2016-07-06 117 * error return value in case of a error read. In the two former cases,
08188ba8822163 Philipp Zabel 2016-07-06 118 * the last read value at @addr is stored in @val. Must not be called
08188ba8822163 Philipp Zabel 2016-07-06 119 * from atomic context if sleep_us or timeout_us are used.
08188ba8822163 Philipp Zabel 2016-07-06 120 *
08188ba8822163 Philipp Zabel 2016-07-06 121 * This is modelled after the readx_poll_timeout macros in linux/iopoll.h.
08188ba8822163 Philipp Zabel 2016-07-06 122 */
08188ba8822163 Philipp Zabel 2016-07-06 123 #define regmap_read_poll_timeout(map, addr, val, cond, sleep_us, timeout_us) \
08188ba8822163 Philipp Zabel 2016-07-06 124 ({ \
1b0c22e45508ff Arnd Bergmann 2017-10-13 125 u64 __timeout_us = (timeout_us); \
1b0c22e45508ff Arnd Bergmann 2017-10-13 126 unsigned long __sleep_us = (sleep_us); \
1b0c22e45508ff Arnd Bergmann 2017-10-13 127 ktime_t __timeout = ktime_add_us(ktime_get(), __timeout_us); \
780b1350d316fd Ramesh Shanmugasundaram 2017-07-03 128 int __ret; \
1b0c22e45508ff Arnd Bergmann 2017-10-13 129 might_sleep_if(__sleep_us); \
08188ba8822163 Philipp Zabel 2016-07-06 130 for (;;) { \
780b1350d316fd Ramesh Shanmugasundaram 2017-07-03 @131 __ret = regmap_read((map), (addr), &(val)); \
780b1350d316fd Ramesh Shanmugasundaram 2017-07-03 132 if (__ret) \
08188ba8822163 Philipp Zabel 2016-07-06 133 break; \
08188ba8822163 Philipp Zabel 2016-07-06 134 if (cond) \
08188ba8822163 Philipp Zabel 2016-07-06 135 break; \
1b0c22e45508ff Arnd Bergmann 2017-10-13 136 if ((__timeout_us) && \
780b1350d316fd Ramesh Shanmugasundaram 2017-07-03 137 ktime_compare(ktime_get(), __timeout) > 0) { \
780b1350d316fd Ramesh Shanmugasundaram 2017-07-03 138 __ret = regmap_read((map), (addr), &(val)); \
08188ba8822163 Philipp Zabel 2016-07-06 139 break; \
08188ba8822163 Philipp Zabel 2016-07-06 140 } \
1b0c22e45508ff Arnd Bergmann 2017-10-13 141 if (__sleep_us) \
1b0c22e45508ff Arnd Bergmann 2017-10-13 142 usleep_range((__sleep_us >> 2) + 1, __sleep_us); \
08188ba8822163 Philipp Zabel 2016-07-06 143 } \
780b1350d316fd Ramesh Shanmugasundaram 2017-07-03 144 __ret ?: ((cond) ? 0 : -ETIMEDOUT); \
08188ba8822163 Philipp Zabel 2016-07-06 145 })
08188ba8822163 Philipp Zabel 2016-07-06 146
:::::: The code at line 131 was first introduced by commit
:::::: 780b1350d316fda28d85fcae17854c778d89cbbe regmap: Avoid namespace collision within macro & tidy up
:::::: TO: Ramesh Shanmugasundaram <[email protected]>
:::::: CC: Mark Brown <[email protected]>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
Hi Weiyi,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on linus/master]
[also build test ERROR on v5.4-rc5 next-20191029]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Weiyi-Lu/Mediatek-MT8183-scpsys-support/20191030-060526
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 23fdb198ae81f47a574296dab5167c5e136a02ba
config: mips-allmodconfig (attached as .config)
compiler: mips-linux-gcc (GCC) 7.4.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=7.4.0 make.cross ARCH=mips
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <[email protected]>
All error/warnings (new ones prefixed by >>):
In file included from <command-line>:0:0:
>> include/linux/soc/mediatek/scpsys-ext.h:26:2: error: unknown type name 'u32'
u32 set_ofs;
^~~
include/linux/soc/mediatek/scpsys-ext.h:27:2: error: unknown type name 'u32'
u32 clr_ofs;
^~~
include/linux/soc/mediatek/scpsys-ext.h:28:2: error: unknown type name 'u32'
u32 en_ofs;
^~~
include/linux/soc/mediatek/scpsys-ext.h:29:2: error: unknown type name 'u32'
u32 sta_ofs;
^~~
include/linux/soc/mediatek/scpsys-ext.h:30:2: error: unknown type name 'u32'
u32 mask;
^~~
include/linux/soc/mediatek/scpsys-ext.h:31:2: error: unknown type name 'u32'
u32 clr_ack_mask;
^~~
>> include/linux/soc/mediatek/scpsys-ext.h:35:9: warning: 'struct regmap' declared inside parameter list will not be visible outside of this definition or declaration
struct regmap *infracfg, struct regmap *smi_common);
^~~~~~
include/linux/soc/mediatek/scpsys-ext.h:37:9: warning: 'struct regmap' declared inside parameter list will not be visible outside of this definition or declaration
struct regmap *infracfg, struct regmap *smi_common);
^~~~~~
vim +/u32 +26 include/linux/soc/mediatek/scpsys-ext.h
23
24 struct bus_prot {
25 enum regmap_type type;
> 26 u32 set_ofs;
27 u32 clr_ofs;
28 u32 en_ofs;
> 29 u32 sta_ofs;
30 u32 mask;
31 u32 clr_ack_mask;
32 };
33
34 int mtk_scpsys_ext_set_bus_protection(const struct bus_prot *bp_table,
> 35 struct regmap *infracfg, struct regmap *smi_common);
36 int mtk_scpsys_ext_clear_bus_protection(const struct bus_prot *bp_table,
37 struct regmap *infracfg, struct regmap *smi_common);
38
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation