DesignWare controller driver provides the support to handle the PHYs which
are compliant to ZRX-DC specification based on "snps,phy-zrxdc-compliant"
DT property. So, add "snps,phy-zrxdc-compliant" property in tegra pcie
controller DT nodes and remove platform specific code from platform driver.
Anvesh Salveru (2):
PCI: tegra: Remove support for ZRX-DC compliant PHY from platform
driver
arm64: tegra: Add support for ZRX-DC phy property
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 6 ++++++
drivers/pci/controller/dwc/pcie-tegra194.c | 4 ----
2 files changed, 6 insertions(+), 4 deletions(-)
--
2.17.1
As part of dw_pcie_setup(), PHYs which are compliant to ZRX-DC
specification are already handled based on "snps,phy-zrxdc-compliant"
property in controller DT node. So, instead of handling ZRX-DC
compliant settings in each platform driver, remove this driver
specific code.
CC: Lorenzo Pieralisi <[email protected]>
CC: Andrew Murray <[email protected]>
CC: Bjorn Helgaas <[email protected]>
CC: Vidya Sagar <[email protected]>
Signed-off-by: Anvesh Salveru <[email protected]>
Signed-off-by: Pankaj Dubey <[email protected]>
---
Depends on the following patch:
https://patchwork.kernel.org/patch/11215241/
https://patchwork.kernel.org/patch/11215239/
drivers/pci/controller/dwc/pcie-tegra194.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index f89f5acee72d..f3a6ea89b8a8 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -782,10 +782,6 @@ static void tegra_pcie_prepare_host(struct pcie_port *pp)
init_host_aspm(pcie);
- val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
- val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
- dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
-
if (pcie->update_fc_fixup) {
val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF);
val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT;
--
2.17.1
DesignWare controller driver provides the support to handle the PHYs which
are compliant to ZRX-DC specification based on "snps,phy-zrxdc-compliant"
DT property. So, add "snps,phy-zrxdc-compliant" property in tegra pcie
controller DT nodes.
CC: Rob Herring <[email protected]>
CC: Mark Rutland <[email protected]>
Signed-off-by: Anvesh Salveru <[email protected]>
Signed-off-by: Pankaj Dubey <[email protected]>
---
Depends on the following patch:
https://patchwork.kernel.org/patch/11215241/
https://patchwork.kernel.org/patch/11215239/
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 3c0cf54f0aab..bf2dbf84c8c9 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -1194,6 +1194,7 @@
ranges = <0x81000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000 /* downstream I/O (1MB) */
0xc2000000 0x12 0x00000000 0x12 0x00000000 0x0 0x30000000 /* prefetchable memory (768MB) */
0x82000000 0x0 0x40000000 0x12 0x30000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
+ snps,phy-zrxdc-compliant;
};
pcie@14120000 {
@@ -1240,6 +1241,7 @@
ranges = <0x81000000 0x0 0x32100000 0x0 0x32100000 0x0 0x00100000 /* downstream I/O (1MB) */
0xc2000000 0x12 0x40000000 0x12 0x40000000 0x0 0x30000000 /* prefetchable memory (768MB) */
0x82000000 0x0 0x40000000 0x12 0x70000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
+ snps,phy-zrxdc-compliant;
};
pcie@14140000 {
@@ -1286,6 +1288,7 @@
ranges = <0x81000000 0x0 0x34100000 0x0 0x34100000 0x0 0x00100000 /* downstream I/O (1MB) */
0xc2000000 0x12 0x80000000 0x12 0x80000000 0x0 0x30000000 /* prefetchable memory (768MB) */
0x82000000 0x0 0x40000000 0x12 0xb0000000 0x0 0x10000000>; /* non-prefetchable memory (256MB) */
+ snps,phy-zrxdc-compliant;
};
pcie@14160000 {
@@ -1332,6 +1335,7 @@
ranges = <0x81000000 0x0 0x36100000 0x0 0x36100000 0x0 0x00100000 /* downstream I/O (1MB) */
0xc2000000 0x14 0x00000000 0x14 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
0x82000000 0x0 0x40000000 0x17 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
+ snps,phy-zrxdc-compliant;
};
pcie@14180000 {
@@ -1378,6 +1382,7 @@
ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */
0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
0x82000000 0x0 0x40000000 0x1b 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
+ snps,phy-zrxdc-compliant;
};
pcie@141a0000 {
@@ -1428,6 +1433,7 @@
ranges = <0x81000000 0x0 0x3a100000 0x0 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */
0xc2000000 0x1c 0x00000000 0x1c 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */
0x82000000 0x0 0x40000000 0x1f 0x40000000 0x0 0xc0000000>; /* non-prefetchable memory (3GB) */
+ snps,phy-zrxdc-compliant;
};
sysram@40000000 {
--
2.17.1