This patch series does the following:
- Reorganize the Clock Handling in Arasan SD driver
- Adds new sampling clock in Arasan SD driver
- Adds support to set Clock Delays in SD Arasan Driver
- Add SDIO Tap Delay handling in ZynqMP firmware driver
- Add support for ZynqMP Tap Delays setting in Arasan SD driver
Changes in v2:
- Replaced the deprecated calls to clock framework APIs
- Added support for dev_clk_get() call to work for SD card clock
- Separated the clock data struct
- Fragmented the patch series in smaller patches to make it more
readable
Changes in v3:
- Reverted "Replaced the deprecated calls to clock framework APIs"
- Removed devm_clk_get() call which was added in v2
Changes in v4:
- Made the Phase Delay properties Arasan specific
Changes in v5:
- Made Clock Phase Delay properties common
- Moved documentation of them to the common mmc documentation.
Manish Narani (8):
mmc: sdhci-of-arasan: Separate out clk related data to another
structure
dt-bindings: mmc: arasan: Update Documentation for the input clock
mmc: sdhci-of-arasan: Add sampling clock for a phy to use
dt-bindings: mmc: Add optional generic properties for mmc
mmc: sdhci-of-arasan: Add support to set clock phase delays for SD
firmware: xilinx: Add SDIO Tap Delay nodes
dt-bindings: mmc: arasan: Document 'xlnx,zynqmp-8.9a' controller
mmc: sdhci-of-arasan: Add support for ZynqMP Platform Tap Delays Setup
.../devicetree/bindings/mmc/arasan,sdhci.txt | 25 +-
.../bindings/mmc/mmc-controller.yaml | 92 ++++
drivers/mmc/host/sdhci-of-arasan.c | 478 +++++++++++++++++-
include/linux/firmware/xlnx-zynqmp.h | 13 +-
4 files changed, 576 insertions(+), 32 deletions(-)
--
2.17.1
Add support to read Clock Phase Delays from the DT and set it via
clk_set_phase() API from clock framework. Some of the controllers might
have their own handling of setting clock delays, for this keep the
set_clk_delays as function pointer which can be assigned controller
specific handling of the same.
Signed-off-by: Manish Narani <[email protected]>
---
drivers/mmc/host/sdhci-of-arasan.c | 92 ++++++++++++++++++++++++++++++
1 file changed, 92 insertions(+)
diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
index b75ba780f902..9452ae01f6fa 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -77,12 +77,18 @@ struct sdhci_arasan_soc_ctl_map {
* @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw.
* @sampleclk_hw: Struct for the clock we might provide to a PHY.
* @sampleclk: Pointer to normal 'struct clock' for sampleclk_hw.
+ * @clk_phase_in: Array of Input Clock Phase Delays for all speed modes
+ * @clk_phase_out: Array of Output Clock Phase Delays for all speed modes
+ * @set_clk_delays: Function pointer for setting Clock Delays
*/
struct sdhci_arasan_clk_data {
struct clk_hw sdcardclk_hw;
struct clk *sdcardclk;
struct clk_hw sampleclk_hw;
struct clk *sampleclk;
+ int clk_phase_in[MMC_TIMING_MMC_HS400 + 1];
+ int clk_phase_out[MMC_TIMING_MMC_HS400 + 1];
+ void (*set_clk_delays)(struct sdhci_host *host);
};
/**
@@ -186,6 +192,7 @@ static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
+ struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
bool ctrl_phy = false;
if (!IS_ERR(sdhci_arasan->phy)) {
@@ -227,6 +234,10 @@ static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock)
sdhci_arasan->is_phy_on = false;
}
+ /* Set the Input and Output Clock Phase Delays */
+ if (clk_data->set_clk_delays)
+ clk_data->set_clk_delays(host);
+
sdhci_set_clock(host, clock);
if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE)
@@ -650,6 +661,85 @@ static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host)
sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz);
}
+static void sdhci_arasan_set_clk_delays(struct sdhci_host *host)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host);
+ struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
+
+ clk_set_phase(clk_data->sampleclk,
+ clk_data->clk_phase_in[host->timing]);
+ clk_set_phase(clk_data->sdcardclk,
+ clk_data->clk_phase_out[host->timing]);
+}
+
+static void arasan_dt_read_clk_phase(struct device *dev,
+ struct sdhci_arasan_clk_data *clk_data,
+ unsigned int timing, const char *prop)
+{
+ struct device_node *np = dev->of_node;
+
+ int clk_phase[2] = {0};
+
+ /*
+ * Read Tap Delay values from DT, if the DT does not contain the
+ * Tap Values then use the pre-defined values.
+ */
+ if (of_property_read_variable_u32_array(np, prop, &clk_phase[0],
+ 2, 0)) {
+ dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n",
+ prop, clk_data->clk_phase_in[timing],
+ clk_data->clk_phase_out[timing]);
+ return;
+ }
+
+ /* The values read are Input and Output Clock Delays in order */
+ clk_data->clk_phase_in[timing] = clk_phase[0];
+ clk_data->clk_phase_out[timing] = clk_phase[1];
+}
+
+/**
+ * arasan_dt_parse_clk_phases - Read Clock Delay values from DT
+ *
+ * Called at initialization to parse the values of Clock Delays.
+ *
+ * @dev: Pointer to our struct device.
+ * @clk_data: Pointer to the Clock Data structure
+ */
+static void arasan_dt_parse_clk_phases(struct device *dev,
+ struct sdhci_arasan_clk_data *clk_data)
+{
+ /*
+ * This has been kept as a pointer and is assigned a function here.
+ * So that different controller variants can assign their own handling
+ * function.
+ */
+ clk_data->set_clk_delays = sdhci_arasan_set_clk_delays;
+
+ arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_LEGACY,
+ "clk-phase-legacy");
+ arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS,
+ "clk-phase-mmc-hs");
+ arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_SD_HS,
+ "clk-phase-sd-hs");
+ arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR12,
+ "clk-phase-uhs-sdr12");
+ arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR25,
+ "clk-phase-uhs-sdr25");
+ arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR50,
+ "clk-phase-uhs-sdr50");
+ arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_SDR104,
+ "clk-phase-uhs-sdr104");
+ arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_UHS_DDR50,
+ "clk-phase-uhs-ddr50");
+ arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_DDR52,
+ "clk-phase-mmc-ddr52");
+ arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS200,
+ "clk-phase-mmc-hs200");
+ arasan_dt_read_clk_phase(dev, clk_data, MMC_TIMING_MMC_HS400,
+ "clk-phase-mmc-hs400");
+}
+
/**
* sdhci_arasan_register_sdcardclk - Register the sdcardclk for a PHY to use
*
@@ -942,6 +1032,8 @@ static int sdhci_arasan_probe(struct platform_device *pdev)
if (ret)
goto clk_disable_all;
+ arasan_dt_parse_clk_phases(&pdev->dev, &sdhci_arasan->clk_data);
+
ret = mmc_of_parse(host->mmc);
if (ret) {
if (ret != -EPROBE_DEFER)
--
2.17.1
There are some operations like setting the clock delays may need to have
two clocks, one for output path and one for input path. Adding input
path clock for some phys to use.
Signed-off-by: Manish Narani <[email protected]>
---
drivers/mmc/host/sdhci-of-arasan.c | 151 +++++++++++++++++++++++++----
1 file changed, 134 insertions(+), 17 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
index 701b6cc0f9a3..b75ba780f902 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -75,10 +75,14 @@ struct sdhci_arasan_soc_ctl_map {
* struct sdhci_arasan_clk_data
* @sdcardclk_hw: Struct for the clock we might provide to a PHY.
* @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw.
+ * @sampleclk_hw: Struct for the clock we might provide to a PHY.
+ * @sampleclk: Pointer to normal 'struct clock' for sampleclk_hw.
*/
struct sdhci_arasan_clk_data {
struct clk_hw sdcardclk_hw;
struct clk *sdcardclk;
+ struct clk_hw sampleclk_hw;
+ struct clk *sampleclk;
};
/**
@@ -541,6 +545,33 @@ static const struct clk_ops arasan_sdcardclk_ops = {
.recalc_rate = sdhci_arasan_sdcardclk_recalc_rate,
};
+/**
+ * sdhci_arasan_sampleclk_recalc_rate - Return the sampling clock rate
+ *
+ * Return the current actual rate of the sampling clock. This can be used
+ * to communicate with out PHY.
+ *
+ * @hw: Pointer to the hardware clock structure.
+ * @parent_rate The parent rate (should be rate of clk_xin).
+ * Returns the sample clock rate.
+ */
+static unsigned long sdhci_arasan_sampleclk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+
+{
+ struct sdhci_arasan_clk_data *clk_data =
+ container_of(hw, struct sdhci_arasan_clk_data, sampleclk_hw);
+ struct sdhci_arasan_data *sdhci_arasan =
+ container_of(clk_data, struct sdhci_arasan_data, clk_data);
+ struct sdhci_host *host = sdhci_arasan->host;
+
+ return host->mmc->actual_clock;
+}
+
+static const struct clk_ops arasan_sampleclk_ops = {
+ .recalc_rate = sdhci_arasan_sampleclk_recalc_rate,
+};
+
/**
* sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
*
@@ -620,28 +651,21 @@ static void sdhci_arasan_update_baseclkfreq(struct sdhci_host *host)
}
/**
- * sdhci_arasan_register_sdclk - Register the sdclk for a PHY to use
+ * sdhci_arasan_register_sdcardclk - Register the sdcardclk for a PHY to use
*
* Some PHY devices need to know what the actual card clock is. In order for
* them to find out, we'll provide a clock through the common clock framework
* for them to query.
*
- * Note: without seriously re-architecting SDHCI's clock code and testing on
- * all platforms, there's no way to create a totally beautiful clock here
- * with all clock ops implemented. Instead, we'll just create a clock that can
- * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
- * framework that we're doing things behind its back. This should be sufficient
- * to create nice clean device tree bindings and later (if needed) we can try
- * re-architecting SDHCI if we see some benefit to it.
- *
* @sdhci_arasan: Our private data structure.
* @clk_xin: Pointer to the functional clock
* @dev: Pointer to our struct device.
* Returns 0 on success and error value on error
*/
-static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan,
- struct clk *clk_xin,
- struct device *dev)
+static int
+sdhci_arasan_register_sdcardclk(struct sdhci_arasan_data *sdhci_arasan,
+ struct clk *clk_xin,
+ struct device *dev)
{
struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
struct device_node *np = dev->of_node;
@@ -649,10 +673,6 @@ static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan,
const char *parent_clk_name;
int ret;
- /* Providing a clock to the PHY is optional; no error if missing */
- if (!of_find_property(np, "#clock-cells", NULL))
- return 0;
-
ret = of_property_read_string_index(np, "clock-output-names", 0,
&sdcardclk_init.name);
if (ret) {
@@ -674,7 +694,56 @@ static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan,
ret = of_clk_add_provider(np, of_clk_src_simple_get,
clk_data->sdcardclk);
if (ret)
- dev_err(dev, "Failed to add clock provider\n");
+ dev_err(dev, "Failed to add sdcard clock provider\n");
+
+ return ret;
+}
+
+/**
+ * sdhci_arasan_register_sampleclk - Register the sampleclk for a PHY to use
+ *
+ * Some PHY devices need to know what the actual card clock is. In order for
+ * them to find out, we'll provide a clock through the common clock framework
+ * for them to query.
+ *
+ * @sdhci_arasan: Our private data structure.
+ * @clk_xin: Pointer to the functional clock
+ * @dev: Pointer to our struct device.
+ * Returns 0 on success and error value on error
+ */
+static int
+sdhci_arasan_register_sampleclk(struct sdhci_arasan_data *sdhci_arasan,
+ struct clk *clk_xin,
+ struct device *dev)
+{
+ struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
+ struct device_node *np = dev->of_node;
+ struct clk_init_data sampleclk_init;
+ const char *parent_clk_name;
+ int ret;
+
+ ret = of_property_read_string_index(np, "clock-output-names", 1,
+ &sampleclk_init.name);
+ if (ret) {
+ dev_err(dev, "DT has #clock-cells but no clock-output-names\n");
+ return ret;
+ }
+
+ parent_clk_name = __clk_get_name(clk_xin);
+ sampleclk_init.parent_names = &parent_clk_name;
+ sampleclk_init.num_parents = 1;
+ sampleclk_init.flags = CLK_GET_RATE_NOCACHE;
+ sampleclk_init.ops = &arasan_sampleclk_ops;
+
+ clk_data->sampleclk_hw.init = &sampleclk_init;
+ clk_data->sampleclk =
+ devm_clk_register(dev, &clk_data->sampleclk_hw);
+ clk_data->sampleclk_hw.init = NULL;
+
+ ret = of_clk_add_provider(np, of_clk_src_simple_get,
+ clk_data->sampleclk);
+ if (ret)
+ dev_err(dev, "Failed to add sample clock provider\n");
return ret;
}
@@ -697,6 +766,54 @@ static void sdhci_arasan_unregister_sdclk(struct device *dev)
of_clk_del_provider(dev->of_node);
}
+/**
+ * sdhci_arasan_register_sdclk - Register the sdcardclk for a PHY to use
+ *
+ * Some PHY devices need to know what the actual card clock is. In order for
+ * them to find out, we'll provide a clock through the common clock framework
+ * for them to query.
+ *
+ * Note: without seriously re-architecting SDHCI's clock code and testing on
+ * all platforms, there's no way to create a totally beautiful clock here
+ * with all clock ops implemented. Instead, we'll just create a clock that can
+ * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
+ * framework that we're doing things behind its back. This should be sufficient
+ * to create nice clean device tree bindings and later (if needed) we can try
+ * re-architecting SDHCI if we see some benefit to it.
+ *
+ * @sdhci_arasan: Our private data structure.
+ * @clk_xin: Pointer to the functional clock
+ * @dev: Pointer to our struct device.
+ * Returns 0 on success and error value on error
+ */
+static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan,
+ struct clk *clk_xin,
+ struct device *dev)
+{
+ struct device_node *np = dev->of_node;
+ u32 num_clks = 0;
+ int ret;
+
+ /* Providing a clock to the PHY is optional; no error if missing */
+ if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0)
+ return 0;
+
+ ret = sdhci_arasan_register_sdcardclk(sdhci_arasan, clk_xin, dev);
+ if (ret)
+ return ret;
+
+ if (num_clks) {
+ ret = sdhci_arasan_register_sampleclk(sdhci_arasan, clk_xin,
+ dev);
+ if (ret) {
+ sdhci_arasan_unregister_sdclk(dev);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
static int sdhci_arasan_add_host(struct sdhci_arasan_data *sdhci_arasan)
{
struct sdhci_host *host = sdhci_arasan->host;
--
2.17.1
dd documentation for 'xlnx,zynqmp-8.9a' SDHCI controller and optional
properties followed by example.
Signed-off-by: Manish Narani <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../devicetree/bindings/mmc/arasan,sdhci.txt | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
index b51e40b2e0c5..6f28e9d612d9 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
@@ -15,6 +15,9 @@ Required Properties:
- "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY
- "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY
For this device it is strongly suggested to include arasan,soc-ctl-syscon.
+ - "xlnx,zynqmp-8.9a": ZynqMP SDHCI 8.9a PHY
+ For this device it is strongly suggested to include clock-output-names and
+ #clock-cells.
- "ti,am654-sdhci-5.1", "arasan,sdhci-5.1": TI AM654 MMC PHY
Note: This binding has been deprecated and moved to [5].
- "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel LGM eMMC PHY
@@ -47,6 +50,10 @@ Optional Properties:
- xlnx,int-clock-stable-broken: when present, the controller always reports
that the internal clock is stable even when it is not.
+ - xlnx,mio-bank: When specified, this will indicate the MIO bank number in
+ which the command and data lines are configured. If not specified, driver
+ will assume this as 0.
+
Example:
sdhci@e0100000 {
compatible = "arasan,sdhci-8.9a";
@@ -83,6 +90,18 @@ Example:
#clock-cells = <0>;
};
+ sdhci: mmc@ff160000 {
+ compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
+ interrupt-parent = <&gic>;
+ interrupts = <0 48 4>;
+ reg = <0x0 0xff160000 0x0 0x1000>;
+ clocks = <&clk200>, <&clk200>;
+ clock-names = "clk_xin", "clk_ahb";
+ clock-output-names = "clk_out_sd0", "clk_in_sd0";
+ #clock-cells = <1>;
+ arasan-clk-phase-sd-hs = <63>, <72>;
+ };
+
emmc: sdhci@ec700000 {
compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
reg = <0xec700000 0x300>;
--
2.17.1
Add optional properties for mmc hosts which are used to set clk delays
for different speed modes in the controller.
Signed-off-by: Manish Narani <[email protected]>
---
.../bindings/mmc/mmc-controller.yaml | 92 +++++++++++++++++++
1 file changed, 92 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml
index 080754e0ef35..87a83d966851 100644
--- a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml
+++ b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml
@@ -212,6 +212,98 @@ properties:
description:
eMMC HS400 enhanced strobe mode is supported
+ # Below mentioned are the clock (phase) delays which are to be configured
+ # in the controller while switching to particular speed mode. The range
+ # of values are 0 to 359 degrees.
+
+ clk-phase-legacy:
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - minimum: 0
+ - maximum: 359
+ description:
+ Input/Output Clock Delay pair in degrees for Legacy Mode.
+
+ clk-phase-mmc-hs:
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - minimum: 0
+ - maximum: 359
+ description:
+ Input/Output Clock Delay pair degrees for MMC HS.
+
+ clk-phase-sd-hs:
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - minimum: 0
+ - maximum: 359
+ description:
+ Input/Output Clock Delay pair in degrees for SD HS.
+
+ clk-phase-uhs-sdr12:
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - minimum: 0
+ - maximum: 359
+ description:
+ Input/Output Clock Delay pair in degrees for SDR12.
+
+ clk-phase-uhs-sdr25:
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - minimum: 0
+ - maximum: 359
+ description:
+ Input/Output Clock Delay pair in degrees for SDR25.
+
+ clk-phase-uhs-sdr50:
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - minimum: 0
+ - maximum: 359
+ description:
+ Input/Output Clock Delay pair in degrees for SDR50.
+
+ clk-phase-uhs-sdr104:
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - minimum: 0
+ - maximum: 359
+ description:
+ Input/Output Clock Delay pair in degrees for SDR104.
+
+ clk-phase-uhs-ddr50:
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - minimum: 0
+ - maximum: 359
+ description:
+ Input/Output Clock Delay pair in degrees for SD DDR50.
+
+ clk-phase-mmc-ddr52:
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - minimum: 0
+ - maximum: 359
+ description:
+ Input/Output Clock Delay pair in degrees for MMC DDR52.
+
+ clk-phase-mmc-hs200:
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - minimum: 0
+ - maximum: 359
+ description:
+ Input/Output Clock Delay pair in degrees for MMC HS200.
+
+ clk-phase-mmc-hs400:
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - minimum: 0
+ - maximum: 359
+ description:
+ Input/Output Clock Delay pair in degrees for MMC HS400.
+
dsr:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
--
2.17.1
Add tap delay nodes for setting SDIO Tap Delays on ZynqMP platform.
Signed-off-by: Manish Narani <[email protected]>
---
include/linux/firmware/xlnx-zynqmp.h | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index 778abbbc7d94..df366f1a4cb4 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -91,7 +91,8 @@ enum pm_ret_status {
};
enum pm_ioctl_id {
- IOCTL_SET_PLL_FRAC_MODE = 8,
+ IOCTL_SET_SD_TAPDELAY = 7,
+ IOCTL_SET_PLL_FRAC_MODE,
IOCTL_GET_PLL_FRAC_MODE,
IOCTL_SET_PLL_FRAC_DATA,
IOCTL_GET_PLL_FRAC_DATA,
@@ -250,6 +251,16 @@ enum zynqmp_pm_request_ack {
ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING,
};
+enum pm_node_id {
+ NODE_SD_0 = 39,
+ NODE_SD_1,
+};
+
+enum tap_delay_type {
+ PM_TAPDELAY_INPUT = 0,
+ PM_TAPDELAY_OUTPUT,
+};
+
/**
* struct zynqmp_pm_query_data - PM query data
* @qid: query ID
--
2.17.1
To improve the code readability, use two different structs, one for
clock provider data and one for mmc platform data.
Signed-off-by: Manish Narani <[email protected]>
---
drivers/mmc/host/sdhci-of-arasan.c | 31 ++++++++++++++++++++----------
1 file changed, 21 insertions(+), 10 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
index 7023cbec4017..701b6cc0f9a3 100644
--- a/drivers/mmc/host/sdhci-of-arasan.c
+++ b/drivers/mmc/host/sdhci-of-arasan.c
@@ -71,14 +71,23 @@ struct sdhci_arasan_soc_ctl_map {
bool hiword_update;
};
+/**
+ * struct sdhci_arasan_clk_data
+ * @sdcardclk_hw: Struct for the clock we might provide to a PHY.
+ * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw.
+ */
+struct sdhci_arasan_clk_data {
+ struct clk_hw sdcardclk_hw;
+ struct clk *sdcardclk;
+};
+
/**
* struct sdhci_arasan_data
* @host: Pointer to the main SDHCI host structure.
* @clk_ahb: Pointer to the AHB clock
* @phy: Pointer to the generic phy
* @is_phy_on: True if the PHY is on; false if not.
- * @sdcardclk_hw: Struct for the clock we might provide to a PHY.
- * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw.
+ * @clk_data: Struct for the Arasan Controller Clock Data.
* @soc_ctl_base: Pointer to regmap for syscon for soc_ctl registers.
* @soc_ctl_map: Map to get offsets into soc_ctl registers.
*/
@@ -89,8 +98,7 @@ struct sdhci_arasan_data {
bool is_phy_on;
bool has_cqe;
- struct clk_hw sdcardclk_hw;
- struct clk *sdcardclk;
+ struct sdhci_arasan_clk_data clk_data;
struct regmap *soc_ctl_base;
const struct sdhci_arasan_soc_ctl_map *soc_ctl_map;
@@ -520,8 +528,10 @@ static unsigned long sdhci_arasan_sdcardclk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
+ struct sdhci_arasan_clk_data *clk_data =
+ container_of(hw, struct sdhci_arasan_clk_data, sdcardclk_hw);
struct sdhci_arasan_data *sdhci_arasan =
- container_of(hw, struct sdhci_arasan_data, sdcardclk_hw);
+ container_of(clk_data, struct sdhci_arasan_data, clk_data);
struct sdhci_host *host = sdhci_arasan->host;
return host->mmc->actual_clock;
@@ -633,6 +643,7 @@ static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan,
struct clk *clk_xin,
struct device *dev)
{
+ struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data;
struct device_node *np = dev->of_node;
struct clk_init_data sdcardclk_init;
const char *parent_clk_name;
@@ -655,13 +666,13 @@ static int sdhci_arasan_register_sdclk(struct sdhci_arasan_data *sdhci_arasan,
sdcardclk_init.flags = CLK_GET_RATE_NOCACHE;
sdcardclk_init.ops = &arasan_sdcardclk_ops;
- sdhci_arasan->sdcardclk_hw.init = &sdcardclk_init;
- sdhci_arasan->sdcardclk =
- devm_clk_register(dev, &sdhci_arasan->sdcardclk_hw);
- sdhci_arasan->sdcardclk_hw.init = NULL;
+ clk_data->sdcardclk_hw.init = &sdcardclk_init;
+ clk_data->sdcardclk =
+ devm_clk_register(dev, &clk_data->sdcardclk_hw);
+ clk_data->sdcardclk_hw.init = NULL;
ret = of_clk_add_provider(np, of_clk_src_simple_get,
- sdhci_arasan->sdcardclk);
+ clk_data->sdcardclk);
if (ret)
dev_err(dev, "Failed to add clock provider\n");
--
2.17.1
On Fri, Nov 01, 2019 at 11:35:49AM +0530, Manish Narani wrote:
> Add optional properties for mmc hosts which are used to set clk delays
> for different speed modes in the controller.
>
> Signed-off-by: Manish Narani <[email protected]>
> ---
> .../bindings/mmc/mmc-controller.yaml | 92 +++++++++++++++++++
> 1 file changed, 92 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml
> index 080754e0ef35..87a83d966851 100644
> --- a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml
> +++ b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml
> @@ -212,6 +212,98 @@ properties:
> description:
> eMMC HS400 enhanced strobe mode is supported
>
> + # Below mentioned are the clock (phase) delays which are to be configured
> + # in the controller while switching to particular speed mode. The range
> + # of values are 0 to 359 degrees.
> +
> + clk-phase-legacy:
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - minimum: 0
> + - maximum: 359
> + description:
> + Input/Output Clock Delay pair in degrees for Legacy Mode.
> +
> + clk-phase-mmc-hs:
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - minimum: 0
> + - maximum: 359
> + description:
> + Input/Output Clock Delay pair degrees for MMC HS.
> +
> + clk-phase-sd-hs:
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - minimum: 0
> + - maximum: 359
> + description:
> + Input/Output Clock Delay pair in degrees for SD HS.
> +
> + clk-phase-uhs-sdr12:
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - minimum: 0
> + - maximum: 359
> + description:
> + Input/Output Clock Delay pair in degrees for SDR12.
> +
> + clk-phase-uhs-sdr25:
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - minimum: 0
> + - maximum: 359
> + description:
> + Input/Output Clock Delay pair in degrees for SDR25.
> +
> + clk-phase-uhs-sdr50:
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - minimum: 0
> + - maximum: 359
> + description:
> + Input/Output Clock Delay pair in degrees for SDR50.
> +
> + clk-phase-uhs-sdr104:
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - minimum: 0
> + - maximum: 359
> + description:
> + Input/Output Clock Delay pair in degrees for SDR104.
> +
> + clk-phase-uhs-ddr50:
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - minimum: 0
> + - maximum: 359
> + description:
> + Input/Output Clock Delay pair in degrees for SD DDR50.
> +
> + clk-phase-mmc-ddr52:
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - minimum: 0
> + - maximum: 359
> + description:
> + Input/Output Clock Delay pair in degrees for MMC DDR52.
> +
> + clk-phase-mmc-hs200:
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - minimum: 0
> + - maximum: 359
> + description:
> + Input/Output Clock Delay pair in degrees for MMC HS200.
> +
> + clk-phase-mmc-hs400:
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - minimum: 0
> + - maximum: 359
> + description:
> + Input/Output Clock Delay pair in degrees for MMC HS400.
This can be condensed into:
patternProperties:
"^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
Or if you want to divide them between SD and MMC ones, that would be
fine for me.
Rob
Hi Rob,
> -----Original Message-----
> From: Rob Herring <[email protected]>
> Sent: Tuesday, November 5, 2019 4:44 AM
> To: Manish Narani <[email protected]>
> Cc: [email protected]; [email protected];
> [email protected]; Michal Simek <[email protected]>; Jolly Shah
> <[email protected]>; Nava kishore Manne <[email protected]>; Rajan Vaja
> <[email protected]>; [email protected];
> [email protected]; [email protected]; linux-arm-
> [email protected]; git <[email protected]>
> Subject: Re: [PATCH v5 4/8] dt-bindings: mmc: Add optional generic
> properties for mmc
>
> On Fri, Nov 01, 2019 at 11:35:49AM +0530, Manish Narani wrote:
> > Add optional properties for mmc hosts which are used to set clk delays
> > for different speed modes in the controller.
> >
> > Signed-off-by: Manish Narani <[email protected]>
> > ---
> > .../bindings/mmc/mmc-controller.yaml | 92 +++++++++++++++++++
> > 1 file changed, 92 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml
> b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml
> > index 080754e0ef35..87a83d966851 100644
> > --- a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml
> > +++ b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml
> > @@ -212,6 +212,98 @@ properties:
> > description:
> > eMMC HS400 enhanced strobe mode is supported
> >
> > + # Below mentioned are the clock (phase) delays which are to be
> configured
> > + # in the controller while switching to particular speed mode. The range
> > + # of values are 0 to 359 degrees.
> > +
> > + clk-phase-legacy:
> > + allOf:
> > + - $ref: /schemas/types.yaml#/definitions/uint32
> > + - minimum: 0
> > + - maximum: 359
> > + description:
> > + Input/Output Clock Delay pair in degrees for Legacy Mode.
> > +
> > + clk-phase-mmc-hs:
> > + allOf:
> > + - $ref: /schemas/types.yaml#/definitions/uint32
> > + - minimum: 0
> > + - maximum: 359
> > + description:
> > + Input/Output Clock Delay pair degrees for MMC HS.
> > +
> > + clk-phase-sd-hs:
> > + allOf:
> > + - $ref: /schemas/types.yaml#/definitions/uint32
> > + - minimum: 0
> > + - maximum: 359
> > + description:
> > + Input/Output Clock Delay pair in degrees for SD HS.
> > +
> > + clk-phase-uhs-sdr12:
> > + allOf:
> > + - $ref: /schemas/types.yaml#/definitions/uint32
> > + - minimum: 0
> > + - maximum: 359
> > + description:
> > + Input/Output Clock Delay pair in degrees for SDR12.
> > +
> > + clk-phase-uhs-sdr25:
> > + allOf:
> > + - $ref: /schemas/types.yaml#/definitions/uint32
> > + - minimum: 0
> > + - maximum: 359
> > + description:
> > + Input/Output Clock Delay pair in degrees for SDR25.
> > +
> > + clk-phase-uhs-sdr50:
> > + allOf:
> > + - $ref: /schemas/types.yaml#/definitions/uint32
> > + - minimum: 0
> > + - maximum: 359
> > + description:
> > + Input/Output Clock Delay pair in degrees for SDR50.
> > +
> > + clk-phase-uhs-sdr104:
> > + allOf:
> > + - $ref: /schemas/types.yaml#/definitions/uint32
> > + - minimum: 0
> > + - maximum: 359
> > + description:
> > + Input/Output Clock Delay pair in degrees for SDR104.
> > +
> > + clk-phase-uhs-ddr50:
> > + allOf:
> > + - $ref: /schemas/types.yaml#/definitions/uint32
> > + - minimum: 0
> > + - maximum: 359
> > + description:
> > + Input/Output Clock Delay pair in degrees for SD DDR50.
> > +
> > + clk-phase-mmc-ddr52:
> > + allOf:
> > + - $ref: /schemas/types.yaml#/definitions/uint32
> > + - minimum: 0
> > + - maximum: 359
> > + description:
> > + Input/Output Clock Delay pair in degrees for MMC DDR52.
> > +
> > + clk-phase-mmc-hs200:
> > + allOf:
> > + - $ref: /schemas/types.yaml#/definitions/uint32
> > + - minimum: 0
> > + - maximum: 359
> > + description:
> > + Input/Output Clock Delay pair in degrees for MMC HS200.
> > +
> > + clk-phase-mmc-hs400:
> > + allOf:
> > + - $ref: /schemas/types.yaml#/definitions/uint32
> > + - minimum: 0
> > + - maximum: 359
> > + description:
> > + Input/Output Clock Delay pair in degrees for MMC HS400.
>
> This can be condensed into:
>
> patternProperties:
>
> "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-
> (sdr(12|25|50|104)|ddr50))$":
>
> Or if you want to divide them between SD and MMC ones, that would be
> fine for me.
Below change should work? Please review.
--- a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml
+++ b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml
@@ -333,6 +333,16 @@ patternProperties:
required:
- reg
+ "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - minimum: 0
+ - maximum: 359
+ description:
+ Set the clock (phase) delays which are to be configured in the
+ controller while switching to particular speed mode. These values
+ are in pair of degrees.
+
dependencies:
cd-debounce-delay-ms: [ cd-gpios ]
fixed-emmc-driver-type: [ non-removable ]
@@ -351,6 +361,7 @@ examples:
keep-power-in-suspend;
wakeup-source;
mmc-pwrseq = <&sdhci0_pwrseq>;
+ clk-phase-sd-hs = <63>, <72>;
};
- |
Thanks,
Manish
Hi Rob,
> -----Original Message-----
> From: Manish Narani
> Sent: Monday, November 11, 2019 3:38 PM
> To: Rob Herring <[email protected]>
> Cc: [email protected]; [email protected];
> [email protected]; Michal Simek <[email protected]>; Jolly Shah
> <[email protected]>; Nava kishore Manne <[email protected]>; Rajan Vaja
> <[email protected]>; [email protected];
> [email protected]; [email protected]; linux-arm-
> [email protected]; git <[email protected]>
> Subject: RE: [PATCH v5 4/8] dt-bindings: mmc: Add optional generic properties
> for mmc
>
> Hi Rob,
>
>
> > -----Original Message-----
> > From: Rob Herring <[email protected]>
> > Sent: Tuesday, November 5, 2019 4:44 AM
> > To: Manish Narani <[email protected]>
> > Cc: [email protected]; [email protected];
> > [email protected]; Michal Simek <[email protected]>; Jolly Shah
> > <[email protected]>; Nava kishore Manne <[email protected]>; Rajan
> Vaja
> > <[email protected]>; [email protected];
> > [email protected]; [email protected]; linux-arm-
> > [email protected]; git <[email protected]>
> > Subject: Re: [PATCH v5 4/8] dt-bindings: mmc: Add optional generic
> > properties for mmc
> >
> > On Fri, Nov 01, 2019 at 11:35:49AM +0530, Manish Narani wrote:
> > > Add optional properties for mmc hosts which are used to set clk delays
> > > for different speed modes in the controller.
> > >
> > > Signed-off-by: Manish Narani <[email protected]>
> > > ---
> > > .../bindings/mmc/mmc-controller.yaml | 92 +++++++++++++++++++
> > > 1 file changed, 92 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/mmc/mmc-
> controller.yaml
> > b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml
> > > index 080754e0ef35..87a83d966851 100644
> > > --- a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml
> > > +++ b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml
> > > @@ -212,6 +212,98 @@ properties:
> > > description:
> > > eMMC HS400 enhanced strobe mode is supported
> > >
> > > + # Below mentioned are the clock (phase) delays which are to be
> > configured
> > > + # in the controller while switching to particular speed mode. The range
> > > + # of values are 0 to 359 degrees.
> > > +
> > > + clk-phase-legacy:
> > > + allOf:
> > > + - $ref: /schemas/types.yaml#/definitions/uint32
> > > + - minimum: 0
> > > + - maximum: 359
> > > + description:
> > > + Input/Output Clock Delay pair in degrees for Legacy Mode.
> > > +
> > > + clk-phase-mmc-hs:
> > > + allOf:
> > > + - $ref: /schemas/types.yaml#/definitions/uint32
> > > + - minimum: 0
> > > + - maximum: 359
> > > + description:
> > > + Input/Output Clock Delay pair degrees for MMC HS.
> > > +
> > > + clk-phase-sd-hs:
> > > + allOf:
> > > + - $ref: /schemas/types.yaml#/definitions/uint32
> > > + - minimum: 0
> > > + - maximum: 359
> > > + description:
> > > + Input/Output Clock Delay pair in degrees for SD HS.
> > > +
> > > + clk-phase-uhs-sdr12:
> > > + allOf:
> > > + - $ref: /schemas/types.yaml#/definitions/uint32
> > > + - minimum: 0
> > > + - maximum: 359
> > > + description:
> > > + Input/Output Clock Delay pair in degrees for SDR12.
> > > +
> > > + clk-phase-uhs-sdr25:
> > > + allOf:
> > > + - $ref: /schemas/types.yaml#/definitions/uint32
> > > + - minimum: 0
> > > + - maximum: 359
> > > + description:
> > > + Input/Output Clock Delay pair in degrees for SDR25.
> > > +
> > > + clk-phase-uhs-sdr50:
> > > + allOf:
> > > + - $ref: /schemas/types.yaml#/definitions/uint32
> > > + - minimum: 0
> > > + - maximum: 359
> > > + description:
> > > + Input/Output Clock Delay pair in degrees for SDR50.
> > > +
> > > + clk-phase-uhs-sdr104:
> > > + allOf:
> > > + - $ref: /schemas/types.yaml#/definitions/uint32
> > > + - minimum: 0
> > > + - maximum: 359
> > > + description:
> > > + Input/Output Clock Delay pair in degrees for SDR104.
> > > +
> > > + clk-phase-uhs-ddr50:
> > > + allOf:
> > > + - $ref: /schemas/types.yaml#/definitions/uint32
> > > + - minimum: 0
> > > + - maximum: 359
> > > + description:
> > > + Input/Output Clock Delay pair in degrees for SD DDR50.
> > > +
> > > + clk-phase-mmc-ddr52:
> > > + allOf:
> > > + - $ref: /schemas/types.yaml#/definitions/uint32
> > > + - minimum: 0
> > > + - maximum: 359
> > > + description:
> > > + Input/Output Clock Delay pair in degrees for MMC DDR52.
> > > +
> > > + clk-phase-mmc-hs200:
> > > + allOf:
> > > + - $ref: /schemas/types.yaml#/definitions/uint32
> > > + - minimum: 0
> > > + - maximum: 359
> > > + description:
> > > + Input/Output Clock Delay pair in degrees for MMC HS200.
> > > +
> > > + clk-phase-mmc-hs400:
> > > + allOf:
> > > + - $ref: /schemas/types.yaml#/definitions/uint32
> > > + - minimum: 0
> > > + - maximum: 359
> > > + description:
> > > + Input/Output Clock Delay pair in degrees for MMC HS400.
> >
> > This can be condensed into:
> >
> > patternProperties:
> >
> > "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-
> > (sdr(12|25|50|104)|ddr50))$":
> >
> > Or if you want to divide them between SD and MMC ones, that would be
> > fine for me.
>
> Below change should work? Please review.
>
> --- a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml
> +++ b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml
> @@ -333,6 +333,16 @@ patternProperties:
> required:
> - reg
>
> + "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-
> (sdr(12|25|50|104)|ddr50))$":
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - minimum: 0
> + - maximum: 359
> + description:
> + Set the clock (phase) delays which are to be configured in the
> + controller while switching to particular speed mode. These values
> + are in pair of degrees.
> +
> dependencies:
> cd-debounce-delay-ms: [ cd-gpios ]
> fixed-emmc-driver-type: [ non-removable ]
> @@ -351,6 +361,7 @@ examples:
> keep-power-in-suspend;
> wakeup-source;
> mmc-pwrseq = <&sdhci0_pwrseq>;
> + clk-phase-sd-hs = <63>, <72>;
> };
>
> - |
Any comment on above change?
Thanks,
Manish
On Mon, Nov 11, 2019 at 4:07 AM Manish Narani <[email protected]> wrote:
>
> Hi Rob,
>
>
> > -----Original Message-----
> > From: Rob Herring <[email protected]>
> > Sent: Tuesday, November 5, 2019 4:44 AM
> > To: Manish Narani <[email protected]>
> > Cc: [email protected]; [email protected];
> > [email protected]; Michal Simek <[email protected]>; Jolly Shah
> > <[email protected]>; Nava kishore Manne <[email protected]>; Rajan Vaja
> > <[email protected]>; [email protected];
> > [email protected]; [email protected]; linux-arm-
> > [email protected]; git <[email protected]>
> > Subject: Re: [PATCH v5 4/8] dt-bindings: mmc: Add optional generic
> > properties for mmc
> >
> > On Fri, Nov 01, 2019 at 11:35:49AM +0530, Manish Narani wrote:
> > > Add optional properties for mmc hosts which are used to set clk delays
> > > for different speed modes in the controller.
> > >
> > > Signed-off-by: Manish Narani <[email protected]>
> > > ---
> > > .../bindings/mmc/mmc-controller.yaml | 92 +++++++++++++++++++
> > > 1 file changed, 92 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml
> > b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml
> > > index 080754e0ef35..87a83d966851 100644
> > > --- a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml
> > > +++ b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml
> > > @@ -212,6 +212,98 @@ properties:
> > > description:
> > > eMMC HS400 enhanced strobe mode is supported
> > >
> > > + # Below mentioned are the clock (phase) delays which are to be
> > configured
> > > + # in the controller while switching to particular speed mode. The range
> > > + # of values are 0 to 359 degrees.
> > > +
> > > + clk-phase-legacy:
> > > + allOf:
> > > + - $ref: /schemas/types.yaml#/definitions/uint32
> > > + - minimum: 0
> > > + - maximum: 359
> > > + description:
> > > + Input/Output Clock Delay pair in degrees for Legacy Mode.
> > > +
> > > + clk-phase-mmc-hs:
> > > + allOf:
> > > + - $ref: /schemas/types.yaml#/definitions/uint32
> > > + - minimum: 0
> > > + - maximum: 359
> > > + description:
> > > + Input/Output Clock Delay pair degrees for MMC HS.
> > > +
> > > + clk-phase-sd-hs:
> > > + allOf:
> > > + - $ref: /schemas/types.yaml#/definitions/uint32
> > > + - minimum: 0
> > > + - maximum: 359
> > > + description:
> > > + Input/Output Clock Delay pair in degrees for SD HS.
> > > +
> > > + clk-phase-uhs-sdr12:
> > > + allOf:
> > > + - $ref: /schemas/types.yaml#/definitions/uint32
> > > + - minimum: 0
> > > + - maximum: 359
> > > + description:
> > > + Input/Output Clock Delay pair in degrees for SDR12.
> > > +
> > > + clk-phase-uhs-sdr25:
> > > + allOf:
> > > + - $ref: /schemas/types.yaml#/definitions/uint32
> > > + - minimum: 0
> > > + - maximum: 359
> > > + description:
> > > + Input/Output Clock Delay pair in degrees for SDR25.
> > > +
> > > + clk-phase-uhs-sdr50:
> > > + allOf:
> > > + - $ref: /schemas/types.yaml#/definitions/uint32
> > > + - minimum: 0
> > > + - maximum: 359
> > > + description:
> > > + Input/Output Clock Delay pair in degrees for SDR50.
> > > +
> > > + clk-phase-uhs-sdr104:
> > > + allOf:
> > > + - $ref: /schemas/types.yaml#/definitions/uint32
> > > + - minimum: 0
> > > + - maximum: 359
> > > + description:
> > > + Input/Output Clock Delay pair in degrees for SDR104.
> > > +
> > > + clk-phase-uhs-ddr50:
> > > + allOf:
> > > + - $ref: /schemas/types.yaml#/definitions/uint32
> > > + - minimum: 0
> > > + - maximum: 359
> > > + description:
> > > + Input/Output Clock Delay pair in degrees for SD DDR50.
> > > +
> > > + clk-phase-mmc-ddr52:
> > > + allOf:
> > > + - $ref: /schemas/types.yaml#/definitions/uint32
> > > + - minimum: 0
> > > + - maximum: 359
> > > + description:
> > > + Input/Output Clock Delay pair in degrees for MMC DDR52.
> > > +
> > > + clk-phase-mmc-hs200:
> > > + allOf:
> > > + - $ref: /schemas/types.yaml#/definitions/uint32
> > > + - minimum: 0
> > > + - maximum: 359
> > > + description:
> > > + Input/Output Clock Delay pair in degrees for MMC HS200.
> > > +
> > > + clk-phase-mmc-hs400:
> > > + allOf:
> > > + - $ref: /schemas/types.yaml#/definitions/uint32
> > > + - minimum: 0
> > > + - maximum: 359
> > > + description:
> > > + Input/Output Clock Delay pair in degrees for MMC HS400.
> >
> > This can be condensed into:
> >
> > patternProperties:
> >
> > "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-
> > (sdr(12|25|50|104)|ddr50))$":
> >
> > Or if you want to divide them between SD and MMC ones, that would be
> > fine for me.
>
> Below change should work? Please review.
Running 'make dt_binding_check' would tell you...
> --- a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml
> +++ b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml
> @@ -333,6 +333,16 @@ patternProperties:
> required:
> - reg
>
> + "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - minimum: 0
> + - maximum: 359
Drop the '-' on maximum so that minimum/maximum are 1 item in the list.
> + description:
> + Set the clock (phase) delays which are to be configured in the
> + controller while switching to particular speed mode. These values
> + are in pair of degrees.
> +
> dependencies:
> cd-debounce-delay-ms: [ cd-gpios ]
> fixed-emmc-driver-type: [ non-removable ]
> @@ -351,6 +361,7 @@ examples:
> keep-power-in-suspend;
> wakeup-source;
> mmc-pwrseq = <&sdhci0_pwrseq>;
> + clk-phase-sd-hs = <63>, <72>;
This should fail because it is defined as a single int.
Rob