According the PCI Express base specification when PHY does not meet
ZRX-DC specification, after every 100ms timeout the link should
transition to recovery state when the link is in low power states.
Ports that meet the ZRX-DC specification for 2.5 GT/s while in the
L1.Idle state and are therefore not required to implement the 100 ms
timeout and transition to Recovery should avoid implementing it, since
it will reduce the power savings expected from the L1 state.
DesignWare controller provides GEN3_ZRXDC_NONCOMPL field in
GEN3_RELATED_OFF to specify about ZRX-DC compliant PHY.
We need to get the PHY property in controller driver. So, we are
proposing a new method phy_property_present() in the phy driver.
Platform specific phy drivers should implement the callback for
property_present which will return true if the property exists in
the PHY.
static bool xxxx_phy_property_present(struct phy *phy, const char *property)
{
struct device *dev = &phy->dev;
return of_property_read_bool(dev->of_node, property);
}
And controller platform driver should populate the phy_zrxdc_compliant
flag, which will be used by generic DesignWare driver.
pci->phy_zrxdc_compliant = phy_property_present(xxxx_ctrl->phy, "phy-zrxdc-compliant");
Anvesh Salveru (2):
phy: core: add phy_property_present method
PCI: dwc: add support to handle ZRX-DC Compliant PHYs
drivers/pci/controller/dwc/pcie-designware.c | 6 ++++++
drivers/pci/controller/dwc/pcie-designware.h | 4 ++++
drivers/phy/phy-core.c | 26 ++++++++++++++++++++++++++
include/linux/phy/phy.h | 8 ++++++++
4 files changed, 44 insertions(+)
--
2.7.4
Many platforms use DesignWare controller but the PHY can be different in
different platforms. If the PHY is compliant is to ZRX-DC specification
it helps in low power consumption during power states.
If current data rate is 8.0 GT/s or higher and PHY is not compliant to
ZRX-DC specification, then after every 100ms link should transition to
recovery state during the low power states.
DesignWare controller provides GEN3_ZRXDC_NONCOMPL field in
GEN3_RELATED_OFF to specify about ZRX-DC compliant PHY.
Platforms with ZRX-DC compliant PHY can set phy_zrxdc_compliant variable
to specify this property to the controller.
Signed-off-by: Anvesh Salveru <[email protected]>
Signed-off-by: Pankaj Dubey <[email protected]>
---
Patchset v2 can be found at:
- 1/2: https://lkml.org/lkml/2019/11/11/672
- 2/2: https://lkml.org/lkml/2019/10/28/285
Changes w.r.t v2:
- Addressed review comments
- Rebased on latest linus/master
drivers/pci/controller/dwc/pcie-designware.c | 6 ++++++
drivers/pci/controller/dwc/pcie-designware.h | 4 ++++
2 files changed, 10 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 820488d..36a01b7 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -556,4 +556,10 @@ void dw_pcie_setup(struct dw_pcie *pci)
PCIE_PL_CHK_REG_CHK_REG_START;
dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
}
+
+ if (pci->phy_zrxdc_compliant) {
+ val = dw_pcie_readl_dbi(pci, PCIE_PORT_GEN3_RELATED);
+ val &= ~PORT_LOGIC_GEN3_ZRXDC_NONCOMPL;
+ dw_pcie_writel_dbi(pci, PCIE_PORT_GEN3_RELATED, val);
+ }
}
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 5a18e94..f43f986 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -60,6 +60,9 @@
#define PCIE_MSI_INTR0_MASK 0x82C
#define PCIE_MSI_INTR0_STATUS 0x830
+#define PCIE_PORT_GEN3_RELATED 0x890
+#define PORT_LOGIC_GEN3_ZRXDC_NONCOMPL BIT(0)
+
#define PCIE_ATU_VIEWPORT 0x900
#define PCIE_ATU_REGION_INBOUND BIT(31)
#define PCIE_ATU_REGION_OUTBOUND 0
@@ -249,6 +252,7 @@ struct dw_pcie {
void __iomem *atu_base;
u32 num_viewport;
u8 iatu_unroll_enabled;
+ bool phy_zrxdc_compliant;
struct pcie_port pp;
struct dw_pcie_ep ep;
const struct dw_pcie_ops *ops;
--
2.7.4
Hi,
You missed to sending this patch series to [email protected].
Regards,
Gustavo
On Wed, Nov 20, 2019 at 13:26:9, Anvesh Salveru <[email protected]>
wrote:
> According the PCI Express base specification when PHY does not meet
> ZRX-DC specification, after every 100ms timeout the link should
> transition to recovery state when the link is in low power states.
>
> Ports that meet the ZRX-DC specification for 2.5 GT/s while in the
> L1.Idle state and are therefore not required to implement the 100 ms
> timeout and transition to Recovery should avoid implementing it, since
> it will reduce the power savings expected from the L1 state.
>
> DesignWare controller provides GEN3_ZRXDC_NONCOMPL field in
> GEN3_RELATED_OFF to specify about ZRX-DC compliant PHY.
>
> We need to get the PHY property in controller driver. So, we are
> proposing a new method phy_property_present() in the phy driver.
>
> Platform specific phy drivers should implement the callback for
> property_present which will return true if the property exists in
> the PHY.
>
> static bool xxxx_phy_property_present(struct phy *phy, const char *property)
> {
> struct device *dev = &phy->dev;
>
> return of_property_read_bool(dev->of_node, property);
> }
>
> And controller platform driver should populate the phy_zrxdc_compliant
> flag, which will be used by generic DesignWare driver.
>
> pci->phy_zrxdc_compliant = phy_property_present(xxxx_ctrl->phy, "phy-zrxdc-compliant");
>
> Anvesh Salveru (2):
> phy: core: add phy_property_present method
> PCI: dwc: add support to handle ZRX-DC Compliant PHYs
>
> drivers/pci/controller/dwc/pcie-designware.c | 6 ++++++
> drivers/pci/controller/dwc/pcie-designware.h | 4 ++++
> drivers/phy/phy-core.c | 26 ++++++++++++++++++++++++++
> include/linux/phy/phy.h | 8 ++++++++
> 4 files changed, 44 insertions(+)
>
> --
> 2.7.4