This patch series applies to the Cadence SD0801 PHY driver. Cadence SD0801 PHY driver
is Torrent PHY driver for Display Port.
Torrent PHY is a multiprotocol PHY supporting PHY configurations including Display Port,
USB and PCIe.
This patch series first adds Display Port configuration then updates the driver to make
it a generic Torrent driver and finally adds SoC platform dependent initialization.
The patch series has 15 patches which applies the changes in the below sequence
1. 001-phy-cadance-dp-Add-DisplayPort-configuration-options
This patch adds generic DisplayPort API for configuring PHY.The parameters configured are
link rate, number of lanes, voltage swing and pre-emphasis.
2. 002-dt-bindings-phy-Convert-Cadence-MHDP-PHY-bindings-to-YAML
This patch converts the MHDP PHY device tree bindings to yaml schemas
3. 003-phy-cadence-dp-Rename-to-phy-Cadence-Torrent
Rename Cadence DP PHY driver from phy-cadence-dp to phy-cadence-torrent
4. 004-phy-cadence-torrent-Adopt-Torrent-nomenclature
Update private data structures, module descriptions and functions prefix to Torrent
5. 005-phy-cadence-torrent-Add-wrapper-for-PHY-register-access
Add a wrapper function to write Torrent PHY registers to improve code readability.
6. 006-phy-cadence-torrent-Add-wrapper-for-DPTX-register-access
Add wrapper functions to read, write DisplayPort specific PHY registers to improve code
readability.
7. 007-phy-cadence-torrent-Refactor-code-for-reusability
Add separate function to set different power state values.
Use of uniform polling timeout value. Check return values of functions for error handling.
8. 008-phy-cadence-torrent-Add clock bindings
Add Torrent PHY reference clock bindings.
9. 009-phy-cadence-torrent-Add-19.2-MHz-reference-clock-support
Add configuration functions for 19.2 MHz reference clock support.Add register configurations
for SSC support.
10. 010-phy-cadence-torrent-Add-phy-lane-reset-support
Add reset support for PHY lane group.
11. 011-phy-cadence-torrent-Implement-phy-configure-APIs
Add PHY configuration APIs for link rate, number of lanes, voltage swing and pre-emphasis values.
12. 012-phy-cadence-torrent-Use-regmap
Use regmap for accessing Torrent PHY registers. Update register offsets. Abstract address
calculation using regmap APIs.
13. 013-phy: cadence-torrent-Use-regmap-to-read-and-write-DPTX-PHY-registers
Use regmap to read and write DPTX specific PHY registers.
14. 014-dt-bindings-phy-phy-cadence-torrent-Add-platform-dependent-compatible-string
Add a new compatible string used for TI SoCs using Torrent PHY.
15. 015-phy-cadence-torrent-Add-platform-dependent-initialization-structure
Add platform dependent initialization data for Torrent PHY used in TI's J721E SoC.
Swapnil Jakhade (8):
phy: cadence-torrent: Adopt Torrent nomenclature
phy: cadence-torrent: Add wrapper for PHY register access
phy: cadence-torrent: Add wrapper for DPTX register access
phy: cadence-torrent: Refactor code for reusability
phy: cadence-torrent: Add 19.2 MHz reference clock support
phy: cadence-torrent: Add PHY lane reset support
phy: cadence-torrent: Implement PHY configure APIs
phy: cadence-torrent: Use regmap to read and write DPTX PHY registers
Yuti Amonkar (7):
phy: Add DisplayPort configuration options
dt-bindings:phy: Convert Cadence MHDP PHY bindings to YAML.
phy: cadence-dp: Rename to phy-cadence-torrent
dt-bindings: phy: phy-cadence-torrent: Add clock bindings
phy: cadence-torrent: Use regmap to read and write Torrent PHY
registers
dt-bindings: phy: phy-cadence-torrent: Add platform dependent
compatible string
phy: cadence-torrent: Add platform dependent initialization structure
.../devicetree/bindings/phy/phy-cadence-dp.txt | 30 -
.../bindings/phy/phy-cadence-torrent.yaml | 71 +
drivers/phy/cadence/Kconfig | 6 +-
drivers/phy/cadence/Makefile | 2 +-
drivers/phy/cadence/phy-cadence-dp.c | 541 ------
drivers/phy/cadence/phy-cadence-torrent.c | 1824 ++++++++++++++++++++
include/linux/phy/phy-dp.h | 95 +
include/linux/phy/phy.h | 4 +
8 files changed, 1998 insertions(+), 575 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
delete mode 100644 drivers/phy/cadence/phy-cadence-dp.c
create mode 100644 drivers/phy/cadence/phy-cadence-torrent.c
create mode 100644 include/linux/phy/phy-dp.h
--
2.7.4
Add a new compatible string used for TI SoCs using Torrent PHY.
Signed-off-by: Yuti Amonkar <[email protected]>
---
Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
index 8069498..60e024b 100644
--- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
@@ -15,7 +15,9 @@ maintainers:
properties:
compatible:
- const: cdns,torrent-phy
+ anyOf:
+ - const: cdns,torrent-phy
+ - const: ti,j721e-serdes-10g
clocks:
maxItems: 1
--
2.7.4
- Convert the MHDP PHY devicetree bindings to yaml schemas.
- Rename DP PHY to have generic Torrent PHY nomrnclature.
- Rename compatible string from "cdns,dp-phy" to "cdns,torrent-phy".
Signed-off-by: Yuti Amonkar <[email protected]>
---
.../devicetree/bindings/phy/phy-cadence-dp.txt | 30 ------------
.../bindings/phy/phy-cadence-torrent.yaml | 57 ++++++++++++++++++++++
2 files changed, 57 insertions(+), 30 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt b/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
deleted file mode 100644
index 7f49fd54e..0000000
--- a/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
+++ /dev/null
@@ -1,30 +0,0 @@
-Cadence MHDP DisplayPort SD0801 PHY binding
-===========================================
-
-This binding describes the Cadence SD0801 PHY hardware included with
-the Cadence MHDP DisplayPort controller.
-
--------------------------------------------------------------------------------
-Required properties (controller (parent) node):
-- compatible : Should be "cdns,dp-phy"
-- reg : Defines the following sets of registers in the parent
- mhdp device:
- - Offset of the DPTX PHY configuration registers
- - Offset of the SD0801 PHY configuration registers
-- #phy-cells : from the generic PHY bindings, must be 0.
-
-Optional properties:
-- num_lanes : Number of DisplayPort lanes to use (1, 2 or 4)
-- max_bit_rate : Maximum DisplayPort link bit rate to use, in Mbps (2160,
- 2430, 2700, 3240, 4320, 5400 or 8100)
--------------------------------------------------------------------------------
-
-Example:
- dp_phy: phy@f0fb030a00 {
- compatible = "cdns,dp-phy";
- reg = <0xf0 0xfb030a00 0x0 0x00000040>,
- <0xf0 0xfb500000 0x0 0x00100000>;
- num_lanes = <4>;
- max_bit_rate = <8100>;
- #phy-cells = <0>;
- };
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
new file mode 100644
index 0000000..4fa9d0a
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
@@ -0,0 +1,57 @@
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Cadence Torrent SD0801 PHY binding for DisplayPort
+
+description:
+ This binding describes the Cadence SD0801 PHY hardware included with
+ the Cadence MHDP DisplayPort controller.
+
+maintainers:
+ - Swapnil Jakhade <[email protected]>
+ - Yuti Amonkar <[email protected]>
+
+properties:
+ compatible:
+ const: cdns,torrent-phy
+
+ reg:
+ items:
+ - description: Offset of the DPTX PHY configuration registers.
+ - description: Offset of the SD0801 PHY configuration registers.
+
+ "#phy-cells":
+ const: 0
+
+ num_lanes:
+ description:
+ Number of DisplayPort lanes.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [1, 2, 4]
+
+ max_bit_rate:
+ description:
+ Maximum DisplayPort link bit rate to use, in Mbps
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100]
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+
+examples:
+ - |
+ dp_phy: phy@f0fb030a00 {
+ compatible = "cdns,torrent-phy";
+ reg = <0xf0 0xfb030a00 0x0 0x00000040>,
+ <0xf0 0xfb500000 0x0 0x00100000>;
+ num_lanes = <4>;
+ max_bit_rate = <8100>;
+ #phy-cells = <0>;
+ };
+...
--
2.7.4
From: Swapnil Jakhade <[email protected]>
Add reset support for PHY lane group.
Signed-off-by: Swapnil Jakhade <[email protected]>
---
drivers/phy/cadence/phy-cadence-torrent.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
index 6c3eaaa..ebc3b68 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -18,6 +18,7 @@
#include <linux/of_device.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include <linux/reset.h>
#define REF_CLK_19_2MHz 19200000
#define REF_CLK_25MHz 25000000
@@ -144,6 +145,7 @@ struct cdns_torrent_phy {
void __iomem *sd_base; /* SD0801 registers base */
u32 num_lanes; /* Number of lanes to use */
u32 max_bit_rate; /* Maximum link bit rate to use (in Mbps) */
+ struct reset_control *phy_rst;
struct device *dev;
struct clk *clk;
unsigned long ref_clk_rate;
@@ -182,9 +184,14 @@ static void cdns_dp_phy_write_field(struct cdns_torrent_phy *cdns_phy,
unsigned char num_bits,
unsigned int val);
+static int cdns_torrent_phy_on(struct phy *phy);
+static int cdns_torrent_phy_off(struct phy *phy);
+
static const struct phy_ops cdns_torrent_phy_ops = {
.init = cdns_torrent_dp_init,
.exit = cdns_torrent_dp_exit,
+ .power_on = cdns_torrent_phy_on,
+ .power_off = cdns_torrent_phy_off,
.owner = THIS_MODULE,
};
@@ -317,6 +324,9 @@ static int cdns_torrent_dp_init(struct phy *phy)
/* take out of reset */
cdns_dp_phy_write_field(cdns_phy, PHY_RESET, 8, 1, 1);
+
+ cdns_torrent_phy_on(phy);
+
ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
if (ret)
return ret;
@@ -945,6 +955,21 @@ static void cdns_dp_phy_write_field(struct cdns_torrent_phy *cdns_phy,
start_bit))));
}
+static int cdns_torrent_phy_on(struct phy *phy)
+{
+ struct cdns_torrent_phy *cdns_phy = phy_get_drvdata(phy);
+
+ /* Take the PHY lane group out of reset */
+ return reset_control_deassert(cdns_phy->phy_rst);
+}
+
+static int cdns_torrent_phy_off(struct phy *phy)
+{
+ struct cdns_torrent_phy *cdns_phy = phy_get_drvdata(phy);
+
+ return reset_control_assert(cdns_phy->phy_rst);
+}
+
static int cdns_torrent_phy_probe(struct platform_device *pdev)
{
struct resource *regs;
@@ -976,6 +1001,8 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev)
if (IS_ERR(cdns_phy->sd_base))
return PTR_ERR(cdns_phy->sd_base);
+ cdns_phy->phy_rst = devm_reset_control_array_get_exclusive(dev);
+
err = device_property_read_u32(dev, "num_lanes",
&cdns_phy->num_lanes);
if (err)
--
2.7.4
From: Swapnil Jakhade <[email protected]>
Add a separate function to set different power state values.
Use uniform polling timeout value. Also check return values
of functions for proper error handling.
Signed-off-by: Swapnil Jakhade <[email protected]>
---
drivers/phy/cadence/phy-cadence-torrent.c | 230 ++++++++++++++++++------------
1 file changed, 137 insertions(+), 93 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
index 5c7c185..b180fba 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -22,7 +22,7 @@
#define MAX_NUM_LANES 4
#define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */
-#define POLL_TIMEOUT_US 2000
+#define POLL_TIMEOUT_US 5000
#define LANE_MASK 0x7
/*
@@ -39,6 +39,7 @@
#define PHY_POWER_STATE_LN_1 0x0008
#define PHY_POWER_STATE_LN_2 0x0010
#define PHY_POWER_STATE_LN_3 0x0018
+#define PMA_XCVR_POWER_STATE_REQ_LN_MASK 0x3FU
#define PHY_PMA_XCVR_POWER_STATE_ACK 0x30
#define PHY_PMA_CMN_READY 0x34
#define PHY_PMA_XCVR_TX_VMARGIN 0x38
@@ -109,10 +110,17 @@ struct cdns_torrent_phy {
struct device *dev;
};
+enum phy_powerstate {
+ POWERSTATE_A0 = 0,
+ /* Powerstate A1 is unused */
+ POWERSTATE_A2 = 2,
+ POWERSTATE_A3 = 3,
+};
+
static int cdns_torrent_dp_init(struct phy *phy);
-static void cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy);
+static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy);
static
-void cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy);
+int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy);
static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy);
static
void cdns_torrent_dp_pma_cmn_cfg_25mhz(struct cdns_torrent_phy *cdns_phy);
@@ -158,9 +166,46 @@ static u32 cdns_torrent_dp_read(struct cdns_torrent_phy *cdns_phy, u32 offset)
readl_poll_timeout((cdns_phy)->base + (offset), \
val, cond, delay_us, timeout_us)
+/* Set power state A0 and PLL clock enable to 0 on enabled lanes. */
+static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy,
+ u32 num_lanes)
+{
+ u32 pwr_state = cdns_torrent_dp_read(cdns_phy,
+ PHY_PMA_XCVR_POWER_STATE_REQ);
+ u32 pll_clk_en = cdns_torrent_dp_read(cdns_phy,
+ PHY_PMA_XCVR_PLLCLK_EN);
+
+ /* Lane 0 is always enabled. */
+ pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
+ PHY_POWER_STATE_LN_0);
+ pll_clk_en &= ~0x01U;
+
+ if (num_lanes > 1) {
+ /* lane 1 */
+ pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
+ PHY_POWER_STATE_LN_1);
+ pll_clk_en &= ~(0x01U << 1);
+ }
+
+ if (num_lanes > 2) {
+ /* lanes 2 and 3 */
+ pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
+ PHY_POWER_STATE_LN_2);
+ pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK <<
+ PHY_POWER_STATE_LN_3);
+ pll_clk_en &= ~(0x01U << 2);
+ pll_clk_en &= ~(0x01U << 3);
+ }
+
+ cdns_torrent_dp_write(cdns_phy,
+ PHY_PMA_XCVR_POWER_STATE_REQ, pwr_state);
+ cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_PLLCLK_EN, pll_clk_en);
+}
+
static int cdns_torrent_dp_init(struct phy *phy)
{
unsigned char lane_bits;
+ int ret;
struct cdns_torrent_phy *cdns_phy = phy_get_drvdata(phy);
@@ -173,40 +218,7 @@ static int cdns_torrent_dp_init(struct phy *phy)
* Set lines power state to A0
* Set lines pll clk enable to 0
*/
-
- cdns_dp_phy_write_field(cdns_phy, PHY_PMA_XCVR_POWER_STATE_REQ,
- PHY_POWER_STATE_LN_0, 6, 0x0000);
-
- if (cdns_phy->num_lanes >= 2) {
- cdns_dp_phy_write_field(cdns_phy,
- PHY_PMA_XCVR_POWER_STATE_REQ,
- PHY_POWER_STATE_LN_1, 6, 0x0000);
-
- if (cdns_phy->num_lanes == 4) {
- cdns_dp_phy_write_field(cdns_phy,
- PHY_PMA_XCVR_POWER_STATE_REQ,
- PHY_POWER_STATE_LN_2, 6, 0);
- cdns_dp_phy_write_field(cdns_phy,
- PHY_PMA_XCVR_POWER_STATE_REQ,
- PHY_POWER_STATE_LN_3, 6, 0);
- }
- }
-
- cdns_dp_phy_write_field(cdns_phy, PHY_PMA_XCVR_PLLCLK_EN,
- 0, 1, 0x0000);
-
- if (cdns_phy->num_lanes >= 2) {
- cdns_dp_phy_write_field(cdns_phy, PHY_PMA_XCVR_PLLCLK_EN,
- 1, 1, 0x0000);
- if (cdns_phy->num_lanes == 4) {
- cdns_dp_phy_write_field(cdns_phy,
- PHY_PMA_XCVR_PLLCLK_EN,
- 2, 1, 0x0000);
- cdns_dp_phy_write_field(cdns_phy,
- PHY_PMA_XCVR_PLLCLK_EN,
- 3, 1, 0x0000);
- }
- }
+ cdns_torrent_dp_set_a0_pll(cdns_phy, cdns_phy->num_lanes);
/*
* release phy_l0*_reset_n and pma_tx_elec_idle_ln_* based on
@@ -225,23 +237,31 @@ static int cdns_torrent_dp_init(struct phy *phy)
/* take out of reset */
cdns_dp_phy_write_field(cdns_phy, PHY_RESET, 8, 1, 1);
- cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
- cdns_torrent_dp_run(cdns_phy);
+ ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);
+ if (ret)
+ return ret;
- return 0;
+ ret = cdns_torrent_dp_run(cdns_phy);
+
+ return ret;
}
static
-void cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy)
+int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy)
{
unsigned int reg;
int ret;
ret = cdns_torrent_dp_read_poll_timeout(cdns_phy, PHY_PMA_CMN_READY,
- reg, reg & 1, 0, 500);
- if (ret == -ETIMEDOUT)
+ reg, reg & 1, 0,
+ POLL_TIMEOUT_US);
+ if (ret == -ETIMEDOUT) {
dev_err(cdns_phy->dev,
"timeout waiting for PMA common ready\n");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
}
static void cdns_torrent_dp_pma_cfg(struct cdns_torrent_phy *cdns_phy)
@@ -397,12 +417,73 @@ static void cdns_torrent_dp_pma_lane_cfg(struct cdns_torrent_phy *cdns_phy,
(XCVR_DIAG_HSCLK_SEL | lane_bits), 0x0000);
}
-static void cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy)
+static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,
+ u32 num_lanes,
+ enum phy_powerstate powerstate)
+{
+ /* Register value for power state for a single byte. */
+ u32 value_part;
+ u32 value;
+ u32 mask;
+ u32 read_val;
+ u32 ret;
+
+ switch (powerstate) {
+ case (POWERSTATE_A0):
+ value_part = 0x01U;
+ break;
+ case (POWERSTATE_A2):
+ value_part = 0x04U;
+ break;
+ default:
+ /* Powerstate A3 */
+ value_part = 0x08U;
+ break;
+ }
+
+ /* Select values of registers and mask, depending on enabled
+ * lane count.
+ */
+ switch (num_lanes) {
+ /* lane 0 */
+ case (1):
+ value = value_part;
+ mask = 0x0000003FU;
+ break;
+ /* lanes 0-1 */
+ case (2):
+ value = (value_part
+ | (value_part << 8));
+ mask = 0x00003F3FU;
+ break;
+ /* lanes 0-3, all */
+ default:
+ value = (value_part
+ | (value_part << 8)
+ | (value_part << 16)
+ | (value_part << 24));
+ mask = 0x3F3F3F3FU;
+ break;
+ }
+
+ /* Set power state A<n>. */
+ cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_POWER_STATE_REQ, value);
+ /* Wait, until PHY acknowledges power state completion. */
+ ret = cdns_torrent_dp_read_poll_timeout(cdns_phy,
+ PHY_PMA_XCVR_POWER_STATE_ACK,
+ read_val,
+ (read_val & mask) == value, 0,
+ POLL_TIMEOUT_US);
+ cdns_torrent_dp_write(cdns_phy,
+ PHY_PMA_XCVR_POWER_STATE_REQ, 0x00000000);
+ ndelay(100);
+
+ return ret;
+}
+
+static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy)
{
unsigned int read_val;
- u32 write_val1 = 0;
- u32 write_val2 = 0;
- u32 mask = 0;
int ret;
/*
@@ -413,60 +494,23 @@ static void cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy)
PHY_PMA_XCVR_PLLCLK_EN_ACK,
read_val, read_val & 1, 0,
POLL_TIMEOUT_US);
- if (ret == -ETIMEDOUT)
+ if (ret == -ETIMEDOUT) {
dev_err(cdns_phy->dev,
"timeout waiting for link PLL clock enable ack\n");
-
- ndelay(100);
-
- switch (cdns_phy->num_lanes) {
- case 1: /* lane 0 */
- write_val1 = 0x00000004;
- write_val2 = 0x00000001;
- mask = 0x0000003f;
- break;
- case 2: /* lane 0-1 */
- write_val1 = 0x00000404;
- write_val2 = 0x00000101;
- mask = 0x00003f3f;
- break;
- case 4: /* lane 0-3 */
- write_val1 = 0x04040404;
- write_val2 = 0x01010101;
- mask = 0x3f3f3f3f;
- break;
+ return ret;
}
- cdns_torrent_dp_write(cdns_phy,
- PHY_PMA_XCVR_POWER_STATE_REQ, write_val1);
-
- ret = cdns_torrent_dp_read_poll_timeout(cdns_phy,
- PHY_PMA_XCVR_POWER_STATE_ACK,
- read_val,
- (read_val & mask) == write_val1,
- 0, POLL_TIMEOUT_US);
-
- if (ret == -ETIMEDOUT)
- dev_err(cdns_phy->dev,
- "timeout waiting for link power state ack\n");
-
- cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_POWER_STATE_REQ, 0);
ndelay(100);
- cdns_torrent_dp_write(cdns_phy,
- PHY_PMA_XCVR_POWER_STATE_REQ, write_val2);
+ ret = cdns_torrent_dp_set_power_state(cdns_phy, cdns_phy->num_lanes,
+ POWERSTATE_A2);
+ if (ret)
+ return ret;
- ret = cdns_torrent_dp_read_poll_timeout(cdns_phy,
- PHY_PMA_XCVR_POWER_STATE_ACK,
- read_val,
- (read_val & mask) == write_val2,
- 0, POLL_TIMEOUT_US);
- if (ret == -ETIMEDOUT)
- dev_err(cdns_phy->dev,
- "timeout waiting for link power state ack\n");
+ ret = cdns_torrent_dp_set_power_state(cdns_phy, cdns_phy->num_lanes,
+ POWERSTATE_A0);
- cdns_torrent_dp_write(cdns_phy, PHY_PMA_XCVR_POWER_STATE_REQ, 0);
- ndelay(100);
+ return ret;
}
static void cdns_dp_phy_write_field(struct cdns_torrent_phy *cdns_phy,
--
2.7.4
On Wed, Dec 11, 2019 at 02:09:07PM +0100, Yuti Amonkar wrote:
> - Convert the MHDP PHY devicetree bindings to yaml schemas.
> - Rename DP PHY to have generic Torrent PHY nomrnclature.
> - Rename compatible string from "cdns,dp-phy" to "cdns,torrent-phy".
You can't just change compatible strings. It's an ABI. Unless you know
for sure there are no users that would care.
>
> Signed-off-by: Yuti Amonkar <[email protected]>
> ---
> .../devicetree/bindings/phy/phy-cadence-dp.txt | 30 ------------
> .../bindings/phy/phy-cadence-torrent.yaml | 57 ++++++++++++++++++++++
> 2 files changed, 57 insertions(+), 30 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
> create mode 100644 Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt b/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
> deleted file mode 100644
> index 7f49fd54e..0000000
> --- a/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
> +++ /dev/null
> @@ -1,30 +0,0 @@
> -Cadence MHDP DisplayPort SD0801 PHY binding
> -===========================================
> -
> -This binding describes the Cadence SD0801 PHY hardware included with
> -the Cadence MHDP DisplayPort controller.
> -
> --------------------------------------------------------------------------------
> -Required properties (controller (parent) node):
> -- compatible : Should be "cdns,dp-phy"
> -- reg : Defines the following sets of registers in the parent
> - mhdp device:
> - - Offset of the DPTX PHY configuration registers
> - - Offset of the SD0801 PHY configuration registers
> -- #phy-cells : from the generic PHY bindings, must be 0.
> -
> -Optional properties:
> -- num_lanes : Number of DisplayPort lanes to use (1, 2 or 4)
> -- max_bit_rate : Maximum DisplayPort link bit rate to use, in Mbps (2160,
> - 2430, 2700, 3240, 4320, 5400 or 8100)
> --------------------------------------------------------------------------------
> -
> -Example:
> - dp_phy: phy@f0fb030a00 {
> - compatible = "cdns,dp-phy";
> - reg = <0xf0 0xfb030a00 0x0 0x00000040>,
> - <0xf0 0xfb500000 0x0 0x00100000>;
> - num_lanes = <4>;
> - max_bit_rate = <8100>;
> - #phy-cells = <0>;
> - };
> diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> new file mode 100644
> index 0000000..4fa9d0a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
Normal file naming is using the compatible string.
> @@ -0,0 +1,57 @@
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Cadence Torrent SD0801 PHY binding for DisplayPort
> +
> +description:
> + This binding describes the Cadence SD0801 PHY hardware included with
> + the Cadence MHDP DisplayPort controller.
> +
> +maintainers:
> + - Swapnil Jakhade <[email protected]>
> + - Yuti Amonkar <[email protected]>
> +
> +properties:
> + compatible:
> + const: cdns,torrent-phy
> +
> + reg:
> + items:
> + - description: Offset of the DPTX PHY configuration registers.
> + - description: Offset of the SD0801 PHY configuration registers.
> +
> + "#phy-cells":
> + const: 0
> +
> + num_lanes:
> + description:
> + Number of DisplayPort lanes.
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - enum: [1, 2, 4]
> +
> + max_bit_rate:
> + description:
> + Maximum DisplayPort link bit rate to use, in Mbps
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100]
> +
> +required:
> + - compatible
> + - reg
> + - "#phy-cells"
> +
> +examples:
> + - |
> + dp_phy: phy@f0fb030a00 {
> + compatible = "cdns,torrent-phy";
> + reg = <0xf0 0xfb030a00 0x0 0x00000040>,
> + <0xf0 0xfb500000 0x0 0x00100000>;
> + num_lanes = <4>;
> + max_bit_rate = <8100>;
> + #phy-cells = <0>;
> + };
> +...
> --
> 2.7.4
>
On Wed, Dec 11, 2019 at 02:09:19PM +0100, Yuti Amonkar wrote:
> Add a new compatible string used for TI SoCs using Torrent PHY.
>
> Signed-off-by: Yuti Amonkar <[email protected]>
> ---
> Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> index 8069498..60e024b 100644
> --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> @@ -15,7 +15,9 @@ maintainers:
>
> properties:
> compatible:
> - const: cdns,torrent-phy
> + anyOf:
Should be an enum or if both strings can be present then you need 2
oneOf entries for 1 string and 2 strings.
> + - const: cdns,torrent-phy
> + - const: ti,j721e-serdes-10g
>
> clocks:
> maxItems: 1
> --
> 2.7.4
>
Hi,
> -----Original Message-----
> From: Rob Herring <[email protected]>
> Sent: Friday, December 20, 2019 2:41
> To: Yuti Suresh Amonkar <[email protected]>
> Cc: [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; Milind Parab
> <[email protected]>; Swapnil Kashinath Jakhade
> <[email protected]>
> Subject: Re: [RESEND PATCH v1 02/15] dt-bindings:phy: Convert Cadence
> MHDP PHY bindings to YAML.
>
> EXTERNAL MAIL
>
>
> On Wed, Dec 11, 2019 at 02:09:07PM +0100, Yuti Amonkar wrote:
>
> > - Convert the MHDP PHY devicetree bindings to yaml schemas.
>
> > - Rename DP PHY to have generic Torrent PHY nomrnclature.
>
> > - Rename compatible string from "cdns,dp-phy" to "cdns,torrent-phy".
>
>
>
> You can't just change compatible strings. It's an ABI. Unless you know
>
> for sure there are no users that would care.
>
The driver has never been functional and therefore not used in any active use cases. We will update this in the commit description
of next patch series.
>
>
> >
>
> > Signed-off-by: Yuti Amonkar <[email protected]>
>
> > ---
>
> > .../devicetree/bindings/phy/phy-cadence-dp.txt | 30 ------------
>
> > .../bindings/phy/phy-cadence-torrent.yaml | 57
> ++++++++++++++++++++++
>
> > 2 files changed, 57 insertions(+), 30 deletions(-)
>
> > delete mode 100644 Documentation/devicetree/bindings/phy/phy-
> cadence-dp.txt
>
> > create mode 100644 Documentation/devicetree/bindings/phy/phy-
> cadence-torrent.yaml
>
> >
>
> > diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
> b/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
>
> > deleted file mode 100644
>
> > index 7f49fd54e..0000000
>
> > --- a/Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
>
> > +++ /dev/null
>
> > @@ -1,30 +0,0 @@
>
> > -Cadence MHDP DisplayPort SD0801 PHY binding
>
> > -===========================================
>
> > -
>
> > -This binding describes the Cadence SD0801 PHY hardware included with
>
> > -the Cadence MHDP DisplayPort controller.
>
> > -
>
> > --------------------------------------------------------------------------------
>
> > -Required properties (controller (parent) node):
>
> > -- compatible : Should be "cdns,dp-phy"
>
> > -- reg : Defines the following sets of registers in the parent
>
> > - mhdp device:
>
> > - - Offset of the DPTX PHY configuration registers
>
> > - - Offset of the SD0801 PHY configuration registers
>
> > -- #phy-cells : from the generic PHY bindings, must be 0.
>
> > -
>
> > -Optional properties:
>
> > -- num_lanes : Number of DisplayPort lanes to use (1, 2 or 4)
>
> > -- max_bit_rate : Maximum DisplayPort link bit rate to use, in Mbps
> (2160,
>
> > - 2430, 2700, 3240, 4320, 5400 or 8100)
>
> > --------------------------------------------------------------------------------
>
> > -
>
> > -Example:
>
> > - dp_phy: phy@f0fb030a00 {
>
> > - compatible = "cdns,dp-phy";
>
> > - reg = <0xf0 0xfb030a00 0x0 0x00000040>,
>
> > - <0xf0 0xfb500000 0x0 0x00100000>;
>
> > - num_lanes = <4>;
>
> > - max_bit_rate = <8100>;
>
> > - #phy-cells = <0>;
>
> > - };
>
> > diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-
> torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-
> torrent.yaml
>
> > new file mode 100644
>
> > index 0000000..4fa9d0a
>
> > --- /dev/null
>
> > +++ b/Documentation/devicetree/bindings/phy/phy-cadence-
> torrent.yaml
>
>
>
> Normal file naming is using the compatible string.
>
>
>
> > @@ -0,0 +1,57 @@
>
> > +%YAML 1.2
>
> > +---
>
> > +$id: "https://urldefense.proofpoint.com/v2/url?u=http-
> 3A__devicetree.org_schemas_phy_phy-2Dcadence-2Dtorrent.yaml-
> 23&d=DwIBAg&c=aUq983L2pue2FqKFoP6PGHMJQyoJ7kl3s3GZ-
> _haXqY&r=xythEVTj32hrXbonw_U5uD9n5Dh9J7TTTznvmGAGKo4&m=9-
> kyiRknYkYa5DqMjgD8NdzvcteoR6ElMbozga1HYMw&s=R0d1BN7TnO9WvU1
> Wd1msGE7rObNLWn_xhVoW247Ggu0&e= "
>
> > +$schema: "https://urldefense.proofpoint.com/v2/url?u=http-
> 3A__devicetree.org_meta-2Dschemas_core.yaml-
> 23&d=DwIBAg&c=aUq983L2pue2FqKFoP6PGHMJQyoJ7kl3s3GZ-
> _haXqY&r=xythEVTj32hrXbonw_U5uD9n5Dh9J7TTTznvmGAGKo4&m=9-
> kyiRknYkYa5DqMjgD8NdzvcteoR6ElMbozga1HYMw&s=uIcZwMHgTJIbhKM1q
> hWr_-4NoZWn5KaohCrVBA28Ruk&e= "
>
> > +
>
> > +title: Cadence Torrent SD0801 PHY binding for DisplayPort
>
> > +
>
> > +description:
>
> > + This binding describes the Cadence SD0801 PHY hardware included with
>
> > + the Cadence MHDP DisplayPort controller.
>
> > +
>
> > +maintainers:
>
> > + - Swapnil Jakhade <[email protected]>
>
> > + - Yuti Amonkar <[email protected]>
>
> > +
>
> > +properties:
>
> > + compatible:
>
> > + const: cdns,torrent-phy
>
> > +
>
> > + reg:
>
> > + items:
>
> > + - description: Offset of the DPTX PHY configuration registers.
>
> > + - description: Offset of the SD0801 PHY configuration registers.
>
> > +
>
> > + "#phy-cells":
>
> > + const: 0
>
> > +
>
> > + num_lanes:
>
> > + description:
>
> > + Number of DisplayPort lanes.
>
> > + allOf:
>
> > + - $ref: /schemas/types.yaml#/definitions/uint32
>
> > + - enum: [1, 2, 4]
>
> > +
>
> > + max_bit_rate:
>
> > + description:
>
> > + Maximum DisplayPort link bit rate to use, in Mbps
>
> > + allOf:
>
> > + - $ref: /schemas/types.yaml#/definitions/uint32
>
> > + - enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100]
>
> > +
>
> > +required:
>
> > + - compatible
>
> > + - reg
>
> > + - "#phy-cells"
>
> > +
>
> > +examples:
>
> > + - |
>
> > + dp_phy: phy@f0fb030a00 {
>
> > + compatible = "cdns,torrent-phy";
>
> > + reg = <0xf0 0xfb030a00 0x0 0x00000040>,
>
> > + <0xf0 0xfb500000 0x0 0x00100000>;
>
> > + num_lanes = <4>;
>
> > + max_bit_rate = <8100>;
>
> > + #phy-cells = <0>;
>
> > + };
>
> > +...
>
> > --
>
> > 2.7.4
>
> >
Thanks & Regards
Yuti Amonkar
Hi,
> -----Original Message-----
> From: Rob Herring <[email protected]>
> Sent: Friday, December 20, 2019 2:56
> To: Yuti Suresh Amonkar <[email protected]>
> Cc: [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; Milind Parab
> <[email protected]>; Swapnil Kashinath Jakhade
> <[email protected]>
> Subject: Re: [RESEND PATCH v1 14/15] dt-bindings: phy: phy-cadence-
> torrent: Add platform dependent compatible string
>
> EXTERNAL MAIL
>
>
> On Wed, Dec 11, 2019 at 02:09:19PM +0100, Yuti Amonkar wrote:
> > Add a new compatible string used for TI SoCs using Torrent PHY.
> >
> > Signed-off-by: Yuti Amonkar <[email protected]>
> > ---
> > Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml | 4
> > +++-
> > 1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> > b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> > index 8069498..60e024b 100644
> > --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> > +++ b/Documentation/devicetree/bindings/phy/phy-cadence-
> torrent.yaml
> > @@ -15,7 +15,9 @@ maintainers:
> >
> > properties:
> > compatible:
> > - const: cdns,torrent-phy
> > + anyOf:
>
> Should be an enum or if both strings can be present then you need 2 oneOf
> entries for 1 string and 2 strings.
>
We can have only one compatible string at a time, so should I use like this?
compatible:
enum:
- cdns,torrent-phy
- ti,j721e-serdes-10g
> > + - const: cdns,torrent-phy
> > + - const: ti,j721e-serdes-10g
> >
> > clocks:
> > maxItems: 1
> > --
> > 2.7.4
> >
Thanks & Regards,
Yuti Amonkar
On Fri, Dec 20, 2019 at 2:43 AM Yuti Suresh Amonkar
<[email protected]> wrote:
>
> Hi,
>
> > -----Original Message-----
> > From: Rob Herring <[email protected]>
> > Sent: Friday, December 20, 2019 2:56
> > To: Yuti Suresh Amonkar <[email protected]>
> > Cc: [email protected]; [email protected];
> > [email protected]; [email protected]; [email protected];
> > [email protected]; [email protected]; Milind Parab
> > <[email protected]>; Swapnil Kashinath Jakhade
> > <[email protected]>
> > Subject: Re: [RESEND PATCH v1 14/15] dt-bindings: phy: phy-cadence-
> > torrent: Add platform dependent compatible string
> >
> > EXTERNAL MAIL
> >
> >
> > On Wed, Dec 11, 2019 at 02:09:19PM +0100, Yuti Amonkar wrote:
> > > Add a new compatible string used for TI SoCs using Torrent PHY.
> > >
> > > Signed-off-by: Yuti Amonkar <[email protected]>
> > > ---
> > > Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml | 4
> > > +++-
> > > 1 file changed, 3 insertions(+), 1 deletion(-)
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> > > b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> > > index 8069498..60e024b 100644
> > > --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
> > > +++ b/Documentation/devicetree/bindings/phy/phy-cadence-
> > torrent.yaml
> > > @@ -15,7 +15,9 @@ maintainers:
> > >
> > > properties:
> > > compatible:
> > > - const: cdns,torrent-phy
> > > + anyOf:
> >
> > Should be an enum or if both strings can be present then you need 2 oneOf
> > entries for 1 string and 2 strings.
> >
>
> We can have only one compatible string at a time, so should I use like this?
>
> compatible:
> enum:
> - cdns,torrent-phy
> - ti,j721e-serdes-10g
Yes.