This series adds device tree support and clock drivers support
for SM8250 SoC.
As part of the device tree, the sm8250 dts file has basic nodes
like CPU, PSCI, intc, timer and clock controller.
Required clock controller driver and RPMH cloks are added to
support peripherals like USB.
All this configuration is added to support SM8250 to boot up to the
serial console.
This patchset depends on one of the RPMH clock driver fix
https://patchwork.kernel.org/patch/11318949/
Taniya Das (6):
dt-bindings: clock: Add RPMHCC bindings for SM8250
clk: qcom: rpmh: Add support for RPMH clocks on SM8250
clk: qcom: clk-alpha-pll: Refactor and cleanup trion PLL
clk: qcom: clk-alpha-pll: Add support for controlling Lucid PLLs
dt-bindings: clock: Add SM8250 GCC clock bindings
clk: qcom: gcc: Add global clock controller driver for SM8250
Venkata Narendra Kumar Gutta (1):
arm64: dts: qcom: sm8250: Add sm8250 dts file
.../devicetree/bindings/clock/qcom,gcc.yaml | 1 +
.../devicetree/bindings/clock/qcom,rpmhcc.yaml | 1 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sm8250-mtp.dts | 29 +
arch/arm64/boot/dts/qcom/sm8250.dtsi | 450 +++
drivers/clk/qcom/Kconfig | 7 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-alpha-pll.c | 259 +-
drivers/clk/qcom/clk-alpha-pll.h | 12 +
drivers/clk/qcom/clk-rpmh.c | 25 +-
drivers/clk/qcom/gcc-sm8250.c | 3720 ++++++++++++++++++++
include/dt-bindings/clock/qcom,gcc-sm8250.h | 271 ++
include/dt-bindings/clock/qcom,rpmh.h | 4 +-
13 files changed, 4731 insertions(+), 50 deletions(-)
create mode 100644 arch/arm64/boot/dts/qcom/sm8250-mtp.dts
create mode 100644 arch/arm64/boot/dts/qcom/sm8250.dtsi
create mode 100644 drivers/clk/qcom/gcc-sm8250.c
create mode 100644 include/dt-bindings/clock/qcom,gcc-sm8250.h
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
From: Taniya Das <[email protected]>
Add device tree bindings for global clock controller on SM8250 SoCs.
Signed-off-by: Taniya Das <[email protected]>
Signed-off-by: Venkata Narendra Kumar Gutta <[email protected]>
---
.../devicetree/bindings/clock/qcom,gcc.yaml | 1 +
include/dt-bindings/clock/qcom,gcc-sm8250.h | 271 +++++++++++++++++++++
2 files changed, 272 insertions(+)
create mode 100644 include/dt-bindings/clock/qcom,gcc-sm8250.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
index 19d0079..e6d586d 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
@@ -39,6 +39,7 @@ properties:
- qcom,gcc-sdm660
- qcom,gcc-sdm845
- qcom,gcc-sm8150
+ - qcom,gcc-sm8250
clocks:
oneOf:
diff --git a/include/dt-bindings/clock/qcom,gcc-sm8250.h b/include/dt-bindings/clock/qcom,gcc-sm8250.h
new file mode 100644
index 0000000..287d5dd
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-sm8250.h
@@ -0,0 +1,271 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8250_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_SM8250_H
+
+/* GCC clocks */
+#define GPLL0 0
+#define GPLL0_OUT_EVEN 1
+#define GPLL4 2
+#define GPLL9 3
+#define GCC_AGGRE_NOC_PCIE_TBU_CLK 4
+#define GCC_AGGRE_UFS_CARD_AXI_CLK 5
+#define GCC_AGGRE_UFS_PHY_AXI_CLK 6
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK 7
+#define GCC_AGGRE_USB3_SEC_AXI_CLK 8
+#define GCC_BOOT_ROM_AHB_CLK 9
+#define GCC_CAMERA_AHB_CLK 10
+#define GCC_CAMERA_HF_AXI_CLK 11
+#define GCC_CAMERA_SF_AXI_CLK 12
+#define GCC_CAMERA_XO_CLK 13
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 14
+#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 15
+#define GCC_CPUSS_AHB_CLK 16
+#define GCC_CPUSS_AHB_CLK_SRC 17
+#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 18
+#define GCC_CPUSS_DVM_BUS_CLK 19
+#define GCC_CPUSS_RBCPR_CLK 20
+#define GCC_DDRSS_GPU_AXI_CLK 21
+#define GCC_DDRSS_PCIE_SF_TBU_CLK 22
+#define GCC_DISP_AHB_CLK 23
+#define GCC_DISP_HF_AXI_CLK 24
+#define GCC_DISP_SF_AXI_CLK 25
+#define GCC_DISP_XO_CLK 26
+#define GCC_GP1_CLK 27
+#define GCC_GP1_CLK_SRC 28
+#define GCC_GP2_CLK 29
+#define GCC_GP2_CLK_SRC 30
+#define GCC_GP3_CLK 31
+#define GCC_GP3_CLK_SRC 32
+#define GCC_GPU_CFG_AHB_CLK 33
+#define GCC_GPU_GPLL0_CLK_SRC 34
+#define GCC_GPU_GPLL0_DIV_CLK_SRC 35
+#define GCC_GPU_IREF_EN 36
+#define GCC_GPU_MEMNOC_GFX_CLK 37
+#define GCC_GPU_SNOC_DVM_GFX_CLK 38
+#define GCC_NPU_AXI_CLK 39
+#define GCC_NPU_BWMON_AXI_CLK 40
+#define GCC_NPU_BWMON_CFG_AHB_CLK 41
+#define GCC_NPU_CFG_AHB_CLK 42
+#define GCC_NPU_DMA_CLK 43
+#define GCC_NPU_GPLL0_CLK_SRC 44
+#define GCC_NPU_GPLL0_DIV_CLK_SRC 45
+#define GCC_PCIE0_PHY_REFGEN_CLK 46
+#define GCC_PCIE1_PHY_REFGEN_CLK 47
+#define GCC_PCIE2_PHY_REFGEN_CLK 48
+#define GCC_PCIE_0_AUX_CLK 49
+#define GCC_PCIE_0_AUX_CLK_SRC 50
+#define GCC_PCIE_0_CFG_AHB_CLK 51
+#define GCC_PCIE_0_MSTR_AXI_CLK 52
+#define GCC_PCIE_0_PIPE_CLK 53
+#define GCC_PCIE_0_SLV_AXI_CLK 54
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 55
+#define GCC_PCIE_1_AUX_CLK 56
+#define GCC_PCIE_1_AUX_CLK_SRC 57
+#define GCC_PCIE_1_CFG_AHB_CLK 58
+#define GCC_PCIE_1_MSTR_AXI_CLK 59
+#define GCC_PCIE_1_PIPE_CLK 60
+#define GCC_PCIE_1_SLV_AXI_CLK 61
+#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 62
+#define GCC_PCIE_2_AUX_CLK 63
+#define GCC_PCIE_2_AUX_CLK_SRC 64
+#define GCC_PCIE_2_CFG_AHB_CLK 65
+#define GCC_PCIE_2_MSTR_AXI_CLK 66
+#define GCC_PCIE_2_PIPE_CLK 67
+#define GCC_PCIE_2_SLV_AXI_CLK 68
+#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 69
+#define GCC_PCIE_MDM_CLKREF_EN 70
+#define GCC_PCIE_PHY_AUX_CLK 71
+#define GCC_PCIE_PHY_REFGEN_CLK_SRC 72
+#define GCC_PCIE_WIFI_CLKREF_EN 73
+#define GCC_PCIE_WIGIG_CLKREF_EN 74
+#define GCC_PDM2_CLK 75
+#define GCC_PDM2_CLK_SRC 76
+#define GCC_PDM_AHB_CLK 77
+#define GCC_PDM_XO4_CLK 78
+#define GCC_PRNG_AHB_CLK 89
+#define GCC_QMIP_CAMERA_NRT_AHB_CLK 80
+#define GCC_QMIP_CAMERA_RT_AHB_CLK 81
+#define GCC_QMIP_DISP_AHB_CLK 82
+#define GCC_QMIP_VIDEO_CVP_AHB_CLK 83
+#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 84
+#define GCC_QUPV3_WRAP0_CORE_2X_CLK 85
+#define GCC_QUPV3_WRAP0_CORE_CLK 86
+#define GCC_QUPV3_WRAP0_S0_CLK 87
+#define GCC_QUPV3_WRAP0_S0_CLK_SRC 88
+#define GCC_QUPV3_WRAP0_S1_CLK 89
+#define GCC_QUPV3_WRAP0_S1_CLK_SRC 90
+#define GCC_QUPV3_WRAP0_S2_CLK 91
+#define GCC_QUPV3_WRAP0_S2_CLK_SRC 92
+#define GCC_QUPV3_WRAP0_S3_CLK 93
+#define GCC_QUPV3_WRAP0_S3_CLK_SRC 94
+#define GCC_QUPV3_WRAP0_S4_CLK 95
+#define GCC_QUPV3_WRAP0_S4_CLK_SRC 96
+#define GCC_QUPV3_WRAP0_S5_CLK 97
+#define GCC_QUPV3_WRAP0_S5_CLK_SRC 98
+#define GCC_QUPV3_WRAP0_S6_CLK 99
+#define GCC_QUPV3_WRAP0_S6_CLK_SRC 100
+#define GCC_QUPV3_WRAP0_S7_CLK 101
+#define GCC_QUPV3_WRAP0_S7_CLK_SRC 102
+#define GCC_QUPV3_WRAP1_CORE_2X_CLK 103
+#define GCC_QUPV3_WRAP1_CORE_CLK 104
+#define GCC_QUPV3_WRAP1_S0_CLK 105
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC 106
+#define GCC_QUPV3_WRAP1_S1_CLK 107
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC 108
+#define GCC_QUPV3_WRAP1_S2_CLK 109
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC 110
+#define GCC_QUPV3_WRAP1_S3_CLK 111
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC 112
+#define GCC_QUPV3_WRAP1_S4_CLK 113
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC 114
+#define GCC_QUPV3_WRAP1_S5_CLK 115
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC 116
+#define GCC_QUPV3_WRAP2_CORE_2X_CLK 117
+#define GCC_QUPV3_WRAP2_CORE_CLK 118
+#define GCC_QUPV3_WRAP2_S0_CLK 119
+#define GCC_QUPV3_WRAP2_S0_CLK_SRC 120
+#define GCC_QUPV3_WRAP2_S1_CLK 121
+#define GCC_QUPV3_WRAP2_S1_CLK_SRC 122
+#define GCC_QUPV3_WRAP2_S2_CLK 123
+#define GCC_QUPV3_WRAP2_S2_CLK_SRC 124
+#define GCC_QUPV3_WRAP2_S3_CLK 125
+#define GCC_QUPV3_WRAP2_S3_CLK_SRC 126
+#define GCC_QUPV3_WRAP2_S4_CLK 127
+#define GCC_QUPV3_WRAP2_S4_CLK_SRC 128
+#define GCC_QUPV3_WRAP2_S5_CLK 129
+#define GCC_QUPV3_WRAP2_S5_CLK_SRC 130
+#define GCC_QUPV3_WRAP_0_M_AHB_CLK 131
+#define GCC_QUPV3_WRAP_0_S_AHB_CLK 132
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK 133
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK 134
+#define GCC_QUPV3_WRAP_2_M_AHB_CLK 135
+#define GCC_QUPV3_WRAP_2_S_AHB_CLK 136
+#define GCC_SDCC2_AHB_CLK 137
+#define GCC_SDCC2_APPS_CLK 138
+#define GCC_SDCC2_APPS_CLK_SRC 139
+#define GCC_SDCC4_AHB_CLK 140
+#define GCC_SDCC4_APPS_CLK 141
+#define GCC_SDCC4_APPS_CLK_SRC 142
+#define GCC_SYS_NOC_CPUSS_AHB_CLK 143
+#define GCC_TSIF_AHB_CLK 144
+#define GCC_TSIF_INACTIVITY_TIMERS_CLK 145
+#define GCC_TSIF_REF_CLK 146
+#define GCC_TSIF_REF_CLK_SRC 147
+#define GCC_UFS_1X_CLKREF_EN 148
+#define GCC_UFS_CARD_AHB_CLK 149
+#define GCC_UFS_CARD_AXI_CLK 150
+#define GCC_UFS_CARD_AXI_CLK_SRC 151
+#define GCC_UFS_CARD_ICE_CORE_CLK 152
+#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 153
+#define GCC_UFS_CARD_PHY_AUX_CLK 154
+#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 155
+#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 156
+#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 157
+#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 158
+#define GCC_UFS_CARD_UNIPRO_CORE_CLK 159
+#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 160
+#define GCC_UFS_PHY_AHB_CLK 161
+#define GCC_UFS_PHY_AXI_CLK 162
+#define GCC_UFS_PHY_AXI_CLK_SRC 163
+#define GCC_UFS_PHY_ICE_CORE_CLK 164
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 165
+#define GCC_UFS_PHY_PHY_AUX_CLK 166
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 167
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 168
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 169
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 170
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK 171
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 172
+#define GCC_USB30_PRIM_MASTER_CLK 173
+#define GCC_USB30_PRIM_MASTER_CLK_SRC 174
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK 175
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 176
+#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 177
+#define GCC_USB30_PRIM_SLEEP_CLK 178
+#define GCC_USB30_SEC_MASTER_CLK 179
+#define GCC_USB30_SEC_MASTER_CLK_SRC 180
+#define GCC_USB30_SEC_MOCK_UTMI_CLK 181
+#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 182
+#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 183
+#define GCC_USB30_SEC_SLEEP_CLK 184
+#define GCC_USB3_PRIM_PHY_AUX_CLK 185
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 186
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 187
+#define GCC_USB3_PRIM_PHY_PIPE_CLK 188
+#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 189
+#define GCC_USB3_SEC_CLKREF_EN 190
+#define GCC_USB3_SEC_PHY_AUX_CLK 191
+#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 192
+#define GCC_USB3_SEC_PHY_COM_AUX_CLK 193
+#define GCC_USB3_SEC_PHY_PIPE_CLK 194
+#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 195
+#define GCC_VIDEO_AHB_CLK 196
+#define GCC_VIDEO_AXI0_CLK 197
+#define GCC_VIDEO_AXI1_CLK 198
+#define GCC_VIDEO_XO_CLK 199
+
+/* GCC resets */
+#define GCC_GPU_BCR 0
+#define GCC_MMSS_BCR 1
+#define GCC_NPU_BWMON_BCR 2
+#define GCC_NPU_BCR 3
+#define GCC_PCIE_0_BCR 4
+#define GCC_PCIE_0_LINK_DOWN_BCR 5
+#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6
+#define GCC_PCIE_0_PHY_BCR 7
+#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8
+#define GCC_PCIE_1_BCR 9
+#define GCC_PCIE_1_LINK_DOWN_BCR 10
+#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 11
+#define GCC_PCIE_1_PHY_BCR 12
+#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 13
+#define GCC_PCIE_2_BCR 14
+#define GCC_PCIE_2_LINK_DOWN_BCR 15
+#define GCC_PCIE_2_NOCSR_COM_PHY_BCR 16
+#define GCC_PCIE_2_PHY_BCR 17
+#define GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR 18
+#define GCC_PCIE_PHY_BCR 19
+#define GCC_PCIE_PHY_CFG_AHB_BCR 20
+#define GCC_PCIE_PHY_COM_BCR 21
+#define GCC_PDM_BCR 22
+#define GCC_PRNG_BCR 23
+#define GCC_QUPV3_WRAPPER_0_BCR 24
+#define GCC_QUPV3_WRAPPER_1_BCR 25
+#define GCC_QUPV3_WRAPPER_2_BCR 26
+#define GCC_QUSB2PHY_PRIM_BCR 27
+#define GCC_QUSB2PHY_SEC_BCR 28
+#define GCC_SDCC2_BCR 29
+#define GCC_SDCC4_BCR 30
+#define GCC_TSIF_BCR 31
+#define GCC_UFS_CARD_BCR 32
+#define GCC_UFS_PHY_BCR 33
+#define GCC_USB30_PRIM_BCR 34
+#define GCC_USB30_SEC_BCR 35
+#define GCC_USB3_DP_PHY_PRIM_BCR 36
+#define GCC_USB3_DP_PHY_SEC_BCR 37
+#define GCC_USB3_PHY_PRIM_BCR 38
+#define GCC_USB3_PHY_SEC_BCR 39
+#define GCC_USB3PHY_PHY_PRIM_BCR 40
+#define GCC_USB3PHY_PHY_SEC_BCR 41
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR 42
+#define GCC_VIDEO_AXI0_CLK_ARES 43
+#define GCC_VIDEO_AXI1_CLK_ARES 44
+
+/* GCC power domains */
+#define PCIE_0_GDSC 0
+#define PCIE_1_GDSC 1
+#define PCIE_2_GDSC 2
+#define UFS_CARD_GDSC 3
+#define UFS_PHY_GDSC 4
+#define USB30_PRIM_GDSC 5
+#define USB30_SEC_GDSC 6
+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 7
+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 8
+#define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 9
+#define HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC 10
+
+#endif
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
From: Taniya Das <[email protected]>
The PLL run and standby modes are similar across the PLLs, thus rename
and refactor the code accordingly.
Remove duplicate function for calculating the round rate of PLL and also
update the trion pll ops to use the common function.
Signed-off-by: Taniya Das <[email protected]>
Signed-off-by: Venkata Narendra Kumar Gutta <[email protected]>
---
drivers/clk/qcom/clk-alpha-pll.c | 71 +++++++++++++---------------------------
1 file changed, 22 insertions(+), 49 deletions(-)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 7c2936d..1b073b2 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -134,15 +134,10 @@
#define PLL_HUAYRA_N_MASK 0xff
#define PLL_HUAYRA_ALPHA_WIDTH 16
-#define FABIA_OPMODE_STANDBY 0x0
-#define FABIA_OPMODE_RUN 0x1
-
-#define FABIA_PLL_OUT_MASK 0x7
-#define FABIA_PLL_RATE_MARGIN 500
-
-#define TRION_PLL_STANDBY 0x0
-#define TRION_PLL_RUN 0x1
-#define TRION_PLL_OUT_MASK 0x7
+#define PLL_STANDBY 0x0
+#define PLL_RUN 0x1
+#define PLL_OUT_MASK 0x7
+#define PLL_RATE_MARGIN 500
#define pll_alpha_width(p) \
((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
@@ -765,7 +760,7 @@ static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
if (ret)
return 0;
- return ((opmode_regval & TRION_PLL_RUN) && (mode_regval & PLL_OUTCTRL));
+ return ((opmode_regval & PLL_RUN) && (mode_regval & PLL_OUTCTRL));
}
static int clk_trion_pll_is_enabled(struct clk_hw *hw)
@@ -795,7 +790,7 @@ static int clk_trion_pll_enable(struct clk_hw *hw)
}
/* Set operation mode to RUN */
- regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_RUN);
+ regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
ret = wait_for_pll_enable_lock(pll);
if (ret)
@@ -803,7 +798,7 @@ static int clk_trion_pll_enable(struct clk_hw *hw)
/* Enable the PLL outputs */
ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
- TRION_PLL_OUT_MASK, TRION_PLL_OUT_MASK);
+ PLL_OUT_MASK, PLL_OUT_MASK);
if (ret)
return ret;
@@ -836,12 +831,12 @@ static void clk_trion_pll_disable(struct clk_hw *hw)
/* Disable the PLL outputs */
ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
- TRION_PLL_OUT_MASK, 0);
+ PLL_OUT_MASK, 0);
if (ret)
return;
/* Place the PLL mode in STANDBY */
- regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_STANDBY);
+ regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
}
@@ -849,33 +844,12 @@ static void clk_trion_pll_disable(struct clk_hw *hw)
clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
- struct regmap *regmap = pll->clkr.regmap;
- u32 l, frac;
- u64 prate = parent_rate;
-
- regmap_read(regmap, PLL_L_VAL(pll), &l);
- regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac);
-
- return alpha_pll_calc_rate(prate, l, frac, ALPHA_REG_16BIT_WIDTH);
-}
-
-static long clk_trion_pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
-{
- struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
- unsigned long min_freq, max_freq;
- u32 l;
- u64 a;
-
- rate = alpha_pll_round_rate(rate, *prate,
- &l, &a, ALPHA_REG_16BIT_WIDTH);
- if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
- return rate;
+ u32 l, frac, alpha_width = pll_alpha_width(pll);
- min_freq = pll->vco_table[0].min_freq;
- max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
+ regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
+ regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
- return clamp(rate, min_freq, max_freq);
+ return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
}
const struct clk_ops clk_alpha_pll_fixed_ops = {
@@ -921,7 +895,7 @@ static long clk_trion_pll_round_rate(struct clk_hw *hw, unsigned long rate,
.disable = clk_trion_pll_disable,
.is_enabled = clk_trion_pll_is_enabled,
.recalc_rate = clk_trion_pll_recalc_rate,
- .round_rate = clk_trion_pll_round_rate,
+ .round_rate = clk_alpha_pll_round_rate,
};
EXPORT_SYMBOL_GPL(clk_trion_fixed_pll_ops);
@@ -1088,14 +1062,14 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw)
return ret;
/* Skip If PLL is already running */
- if ((opmode_val & FABIA_OPMODE_RUN) && (val & PLL_OUTCTRL))
+ if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL))
return 0;
ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
if (ret)
return ret;
- ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY);
+ ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
if (ret)
return ret;
@@ -1104,7 +1078,7 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw)
if (ret)
return ret;
- ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_RUN);
+ ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
if (ret)
return ret;
@@ -1113,7 +1087,7 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw)
return ret;
ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
- FABIA_PLL_OUT_MASK, FABIA_PLL_OUT_MASK);
+ PLL_OUT_MASK, PLL_OUT_MASK);
if (ret)
return ret;
@@ -1143,13 +1117,12 @@ static void alpha_pll_fabia_disable(struct clk_hw *hw)
return;
/* Disable main outputs */
- ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), FABIA_PLL_OUT_MASK,
- 0);
+ ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
if (ret)
return;
/* Place the PLL in STANDBY */
- regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY);
+ regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
}
static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw,
@@ -1178,7 +1151,7 @@ static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
* Due to limited number of bits for fractional rate programming, the
* rounded up rate could be marginally higher than the requested rate.
*/
- if (rrate > (rate + FABIA_PLL_RATE_MARGIN) || rrate < rate) {
+ if (rrate > (rate + PLL_RATE_MARGIN) || rrate < rate) {
pr_err("Call set rate on the PLL with rounded rates!\n");
return -EINVAL;
}
@@ -1227,7 +1200,7 @@ static int alpha_pll_fabia_prepare(struct clk_hw *hw)
* Due to a limited number of bits for fractional rate programming, the
* rounded up rate could be marginally higher than the requested rate.
*/
- if (rrate > (cal_freq + FABIA_PLL_RATE_MARGIN) || rrate < cal_freq)
+ if (rrate > (cal_freq + PLL_RATE_MARGIN) || rrate < cal_freq)
return -EINVAL;
/* Setup PLL for calibration frequency */
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
From: Taniya Das <[email protected]>
Add support for RPMH clocks on SM8250.
Signed-off-by: Taniya Das <[email protected]>
Signed-off-by: Venkata Narendra Kumar Gutta <[email protected]>
---
drivers/clk/qcom/clk-rpmh.c | 25 ++++++++++++++++++++++++-
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
index 593bfa4..0e45adf 100644
--- a/drivers/clk/qcom/clk-rpmh.c
+++ b/drivers/clk/qcom/clk-rpmh.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
*/
#include <linux/clk-provider.h>
@@ -404,6 +404,28 @@ static unsigned long clk_rpmh_bcm_recalc_rate(struct clk_hw *hw,
.num_clks = ARRAY_SIZE(sc7180_rpmh_clocks),
};
+DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 2);
+
+static struct clk_hw *sm8250_rpmh_clocks[] = {
+ [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
+ [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
+ [RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1.hw,
+ [RPMH_LN_BB_CLK1_A] = &sm8250_ln_bb_clk1_ao.hw,
+ [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
+ [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
+ [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
+ [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
+ [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
+ [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
+ [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
+ [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
+};
+
+static const struct clk_rpmh_desc clk_rpmh_sm8250 = {
+ .clks = sm8250_rpmh_clocks,
+ .num_clks = ARRAY_SIZE(sm8250_rpmh_clocks),
+};
+
static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
void *data)
{
@@ -490,6 +512,7 @@ static int clk_rpmh_probe(struct platform_device *pdev)
{ .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
{ .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
{ .compatible = "qcom,sc7180-rpmh-clk", .data = &clk_rpmh_sc7180},
+ { .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250},
{ }
};
MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
On 16-01-20, 15:39, Venkata Narendra Kumar Gutta wrote:
> From: Taniya Das <[email protected]>
>
> Add support for RPMH clocks on SM8250.
Reviewed-by: Vinod Koul <[email protected]>
--
~Vinod
On 16-01-20, 15:39, Venkata Narendra Kumar Gutta wrote:
> From: Taniya Das <[email protected]>
>
> The PLL run and standby modes are similar across the PLLs, thus rename
> and refactor the code accordingly.
>
> Remove duplicate function for calculating the round rate of PLL and also
> update the trion pll ops to use the common function.
Reviewed-by: Vinod Koul <[email protected]>
--
~Vinod
On 16-01-20, 15:39, Venkata Narendra Kumar Gutta wrote:
> This series adds device tree support and clock drivers support
> for SM8250 SoC.
> As part of the device tree, the sm8250 dts file has basic nodes
> like CPU, PSCI, intc, timer and clock controller.
>
> Required clock controller driver and RPMH cloks are added to
> support peripherals like USB.
>
> All this configuration is added to support SM8250 to boot up to the
> serial console.
>
> This patchset depends on one of the RPMH clock driver fix
> https://patchwork.kernel.org/patch/11318949/
Whole series:
Tested-by: Vinod Koul <[email protected]>
--
~Vinod
On Thu, 16 Jan 2020 15:39:52 -0800, Venkata Narendra Kumar Gutta wrote:
> From: Taniya Das <[email protected]>
>
> Add device tree bindings for global clock controller on SM8250 SoCs.
>
> Signed-off-by: Taniya Das <[email protected]>
> Signed-off-by: Venkata Narendra Kumar Gutta <[email protected]>
> ---
> .../devicetree/bindings/clock/qcom,gcc.yaml | 1 +
> include/dt-bindings/clock/qcom,gcc-sm8250.h | 271 +++++++++++++++++++++
> 2 files changed, 272 insertions(+)
> create mode 100644 include/dt-bindings/clock/qcom,gcc-sm8250.h
>
Acked-by: Rob Herring <[email protected]>
Quoting Venkata Narendra Kumar Gutta (2020-01-16 15:39:49)
> @@ -490,6 +512,7 @@ static int clk_rpmh_probe(struct platform_device *pdev)
> { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
> { .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
> { .compatible = "qcom,sc7180-rpmh-clk", .data = &clk_rpmh_sc7180},
> + { .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250},
We should sort this on compatible.
> { }
> };
> MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);
On Thu 16 Jan 15:39 PST 2020, Venkata Narendra Kumar Gutta wrote:
> This series adds device tree support and clock drivers support
> for SM8250 SoC.
> As part of the device tree, the sm8250 dts file has basic nodes
> like CPU, PSCI, intc, timer and clock controller.
>
> Required clock controller driver and RPMH cloks are added to
> support peripherals like USB.
>
> All this configuration is added to support SM8250 to boot up to the
> serial console.
>
> This patchset depends on one of the RPMH clock driver fix
> https://patchwork.kernel.org/patch/11318949/
>
Validated that this boots to console, so even though most of the clock
drivers hasn't been exercised.
Tested-by: Bjorn Andersson <[email protected]>
On Wed 22 Jan 22:46 PST 2020, Stephen Boyd wrote:
> Quoting Venkata Narendra Kumar Gutta (2020-01-16 15:39:49)
> > @@ -490,6 +512,7 @@ static int clk_rpmh_probe(struct platform_device *pdev)
> > { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
> > { .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
> > { .compatible = "qcom,sc7180-rpmh-clk", .data = &clk_rpmh_sc7180},
> > + { .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250},
>
> We should sort this on compatible.
>
Yes we should, in case this was a request I sent out a patch for this:
https://lore.kernel.org/linux-arm-msm/[email protected]/
Regards,
Bjorn
> > { }
> > };
> > MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);
On Thu 16 Jan 15:39 PST 2020, Venkata Narendra Kumar Gutta wrote:
> From: Taniya Das <[email protected]>
>
> The PLL run and standby modes are similar across the PLLs, thus rename
> and refactor the code accordingly.
>
> Remove duplicate function for calculating the round rate of PLL and also
> update the trion pll ops to use the common function.
>
Reviewed-by: Bjorn Andersson <[email protected]>
> Signed-off-by: Taniya Das <[email protected]>
> Signed-off-by: Venkata Narendra Kumar Gutta <[email protected]>
> ---
> drivers/clk/qcom/clk-alpha-pll.c | 71 +++++++++++++---------------------------
> 1 file changed, 22 insertions(+), 49 deletions(-)
>
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index 7c2936d..1b073b2 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -134,15 +134,10 @@
> #define PLL_HUAYRA_N_MASK 0xff
> #define PLL_HUAYRA_ALPHA_WIDTH 16
>
> -#define FABIA_OPMODE_STANDBY 0x0
> -#define FABIA_OPMODE_RUN 0x1
> -
> -#define FABIA_PLL_OUT_MASK 0x7
> -#define FABIA_PLL_RATE_MARGIN 500
> -
> -#define TRION_PLL_STANDBY 0x0
> -#define TRION_PLL_RUN 0x1
> -#define TRION_PLL_OUT_MASK 0x7
> +#define PLL_STANDBY 0x0
> +#define PLL_RUN 0x1
> +#define PLL_OUT_MASK 0x7
> +#define PLL_RATE_MARGIN 500
>
> #define pll_alpha_width(p) \
> ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
> @@ -765,7 +760,7 @@ static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
> if (ret)
> return 0;
>
> - return ((opmode_regval & TRION_PLL_RUN) && (mode_regval & PLL_OUTCTRL));
> + return ((opmode_regval & PLL_RUN) && (mode_regval & PLL_OUTCTRL));
> }
>
> static int clk_trion_pll_is_enabled(struct clk_hw *hw)
> @@ -795,7 +790,7 @@ static int clk_trion_pll_enable(struct clk_hw *hw)
> }
>
> /* Set operation mode to RUN */
> - regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_RUN);
> + regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
>
> ret = wait_for_pll_enable_lock(pll);
> if (ret)
> @@ -803,7 +798,7 @@ static int clk_trion_pll_enable(struct clk_hw *hw)
>
> /* Enable the PLL outputs */
> ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
> - TRION_PLL_OUT_MASK, TRION_PLL_OUT_MASK);
> + PLL_OUT_MASK, PLL_OUT_MASK);
> if (ret)
> return ret;
>
> @@ -836,12 +831,12 @@ static void clk_trion_pll_disable(struct clk_hw *hw)
>
> /* Disable the PLL outputs */
> ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
> - TRION_PLL_OUT_MASK, 0);
> + PLL_OUT_MASK, 0);
> if (ret)
> return;
>
> /* Place the PLL mode in STANDBY */
> - regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_STANDBY);
> + regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
> regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
> }
>
> @@ -849,33 +844,12 @@ static void clk_trion_pll_disable(struct clk_hw *hw)
> clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> {
> struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> - struct regmap *regmap = pll->clkr.regmap;
> - u32 l, frac;
> - u64 prate = parent_rate;
> -
> - regmap_read(regmap, PLL_L_VAL(pll), &l);
> - regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac);
> -
> - return alpha_pll_calc_rate(prate, l, frac, ALPHA_REG_16BIT_WIDTH);
> -}
> -
> -static long clk_trion_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> - unsigned long *prate)
> -{
> - struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> - unsigned long min_freq, max_freq;
> - u32 l;
> - u64 a;
> -
> - rate = alpha_pll_round_rate(rate, *prate,
> - &l, &a, ALPHA_REG_16BIT_WIDTH);
> - if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
> - return rate;
> + u32 l, frac, alpha_width = pll_alpha_width(pll);
>
> - min_freq = pll->vco_table[0].min_freq;
> - max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
> + regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
> + regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
>
> - return clamp(rate, min_freq, max_freq);
> + return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
> }
>
> const struct clk_ops clk_alpha_pll_fixed_ops = {
> @@ -921,7 +895,7 @@ static long clk_trion_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> .disable = clk_trion_pll_disable,
> .is_enabled = clk_trion_pll_is_enabled,
> .recalc_rate = clk_trion_pll_recalc_rate,
> - .round_rate = clk_trion_pll_round_rate,
> + .round_rate = clk_alpha_pll_round_rate,
> };
> EXPORT_SYMBOL_GPL(clk_trion_fixed_pll_ops);
>
> @@ -1088,14 +1062,14 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw)
> return ret;
>
> /* Skip If PLL is already running */
> - if ((opmode_val & FABIA_OPMODE_RUN) && (val & PLL_OUTCTRL))
> + if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL))
> return 0;
>
> ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
> if (ret)
> return ret;
>
> - ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY);
> + ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
> if (ret)
> return ret;
>
> @@ -1104,7 +1078,7 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw)
> if (ret)
> return ret;
>
> - ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_RUN);
> + ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
> if (ret)
> return ret;
>
> @@ -1113,7 +1087,7 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw)
> return ret;
>
> ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
> - FABIA_PLL_OUT_MASK, FABIA_PLL_OUT_MASK);
> + PLL_OUT_MASK, PLL_OUT_MASK);
> if (ret)
> return ret;
>
> @@ -1143,13 +1117,12 @@ static void alpha_pll_fabia_disable(struct clk_hw *hw)
> return;
>
> /* Disable main outputs */
> - ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), FABIA_PLL_OUT_MASK,
> - 0);
> + ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
> if (ret)
> return;
>
> /* Place the PLL in STANDBY */
> - regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY);
> + regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
> }
>
> static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw,
> @@ -1178,7 +1151,7 @@ static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
> * Due to limited number of bits for fractional rate programming, the
> * rounded up rate could be marginally higher than the requested rate.
> */
> - if (rrate > (rate + FABIA_PLL_RATE_MARGIN) || rrate < rate) {
> + if (rrate > (rate + PLL_RATE_MARGIN) || rrate < rate) {
> pr_err("Call set rate on the PLL with rounded rates!\n");
> return -EINVAL;
> }
> @@ -1227,7 +1200,7 @@ static int alpha_pll_fabia_prepare(struct clk_hw *hw)
> * Due to a limited number of bits for fractional rate programming, the
> * rounded up rate could be marginally higher than the requested rate.
> */
> - if (rrate > (cal_freq + FABIA_PLL_RATE_MARGIN) || rrate < cal_freq)
> + if (rrate > (cal_freq + PLL_RATE_MARGIN) || rrate < cal_freq)
> return -EINVAL;
>
> /* Setup PLL for calibration frequency */
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
On Thu 16 Jan 15:39 PST 2020, Venkata Narendra Kumar Gutta wrote:
> From: Taniya Das <[email protected]>
>
> Add support for RPMH clocks on SM8250.
>
> Signed-off-by: Taniya Das <[email protected]>
> Signed-off-by: Venkata Narendra Kumar Gutta <[email protected]>
> ---
> drivers/clk/qcom/clk-rpmh.c | 25 ++++++++++++++++++++++++-
> 1 file changed, 24 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c
> index 593bfa4..0e45adf 100644
> --- a/drivers/clk/qcom/clk-rpmh.c
> +++ b/drivers/clk/qcom/clk-rpmh.c
> @@ -1,6 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
> - * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
> */
>
> #include <linux/clk-provider.h>
> @@ -404,6 +404,28 @@ static unsigned long clk_rpmh_bcm_recalc_rate(struct clk_hw *hw,
> .num_clks = ARRAY_SIZE(sc7180_rpmh_clocks),
> };
>
> +DEFINE_CLK_RPMH_VRM(sm8250, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 2);
> +
> +static struct clk_hw *sm8250_rpmh_clocks[] = {
> + [RPMH_CXO_CLK] = &sdm845_bi_tcxo.hw,
> + [RPMH_CXO_CLK_A] = &sdm845_bi_tcxo_ao.hw,
> + [RPMH_LN_BB_CLK1] = &sm8250_ln_bb_clk1.hw,
> + [RPMH_LN_BB_CLK1_A] = &sm8250_ln_bb_clk1_ao.hw,
> + [RPMH_LN_BB_CLK2] = &sdm845_ln_bb_clk2.hw,
> + [RPMH_LN_BB_CLK2_A] = &sdm845_ln_bb_clk2_ao.hw,
> + [RPMH_LN_BB_CLK3] = &sdm845_ln_bb_clk3.hw,
> + [RPMH_LN_BB_CLK3_A] = &sdm845_ln_bb_clk3_ao.hw,
> + [RPMH_RF_CLK1] = &sdm845_rf_clk1.hw,
> + [RPMH_RF_CLK1_A] = &sdm845_rf_clk1_ao.hw,
> + [RPMH_RF_CLK3] = &sdm845_rf_clk3.hw,
> + [RPMH_RF_CLK3_A] = &sdm845_rf_clk3_ao.hw,
> +};
> +
> +static const struct clk_rpmh_desc clk_rpmh_sm8250 = {
> + .clks = sm8250_rpmh_clocks,
> + .num_clks = ARRAY_SIZE(sm8250_rpmh_clocks),
> +};
> +
> static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
> void *data)
> {
> @@ -490,6 +512,7 @@ static int clk_rpmh_probe(struct platform_device *pdev)
> { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
> { .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
> { .compatible = "qcom,sc7180-rpmh-clk", .data = &clk_rpmh_sc7180},
> + { .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250},
Double space before .data
Apart from that
Reviewed-by: Bjorn Andersson <[email protected]>
Regards,
Bjorn
> { }
> };
> MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
On Thu 16 Jan 15:39 PST 2020, Venkata Narendra Kumar Gutta wrote:
> From: Taniya Das <[email protected]>
>
> Add device tree bindings for global clock controller on SM8250 SoCs.
>
> Signed-off-by: Taniya Das <[email protected]>
> Signed-off-by: Venkata Narendra Kumar Gutta <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
> ---
> .../devicetree/bindings/clock/qcom,gcc.yaml | 1 +
> include/dt-bindings/clock/qcom,gcc-sm8250.h | 271 +++++++++++++++++++++
> 2 files changed, 272 insertions(+)
> create mode 100644 include/dt-bindings/clock/qcom,gcc-sm8250.h
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
> index 19d0079..e6d586d 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
> @@ -39,6 +39,7 @@ properties:
> - qcom,gcc-sdm660
> - qcom,gcc-sdm845
> - qcom,gcc-sm8150
> + - qcom,gcc-sm8250
>
> clocks:
> oneOf:
> diff --git a/include/dt-bindings/clock/qcom,gcc-sm8250.h b/include/dt-bindings/clock/qcom,gcc-sm8250.h
> new file mode 100644
> index 0000000..287d5dd
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,gcc-sm8250.h
> @@ -0,0 +1,271 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2020, The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8250_H
> +#define _DT_BINDINGS_CLK_QCOM_GCC_SM8250_H
> +
> +/* GCC clocks */
> +#define GPLL0 0
> +#define GPLL0_OUT_EVEN 1
> +#define GPLL4 2
> +#define GPLL9 3
> +#define GCC_AGGRE_NOC_PCIE_TBU_CLK 4
> +#define GCC_AGGRE_UFS_CARD_AXI_CLK 5
> +#define GCC_AGGRE_UFS_PHY_AXI_CLK 6
> +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 7
> +#define GCC_AGGRE_USB3_SEC_AXI_CLK 8
> +#define GCC_BOOT_ROM_AHB_CLK 9
> +#define GCC_CAMERA_AHB_CLK 10
> +#define GCC_CAMERA_HF_AXI_CLK 11
> +#define GCC_CAMERA_SF_AXI_CLK 12
> +#define GCC_CAMERA_XO_CLK 13
> +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 14
> +#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 15
> +#define GCC_CPUSS_AHB_CLK 16
> +#define GCC_CPUSS_AHB_CLK_SRC 17
> +#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 18
> +#define GCC_CPUSS_DVM_BUS_CLK 19
> +#define GCC_CPUSS_RBCPR_CLK 20
> +#define GCC_DDRSS_GPU_AXI_CLK 21
> +#define GCC_DDRSS_PCIE_SF_TBU_CLK 22
> +#define GCC_DISP_AHB_CLK 23
> +#define GCC_DISP_HF_AXI_CLK 24
> +#define GCC_DISP_SF_AXI_CLK 25
> +#define GCC_DISP_XO_CLK 26
> +#define GCC_GP1_CLK 27
> +#define GCC_GP1_CLK_SRC 28
> +#define GCC_GP2_CLK 29
> +#define GCC_GP2_CLK_SRC 30
> +#define GCC_GP3_CLK 31
> +#define GCC_GP3_CLK_SRC 32
> +#define GCC_GPU_CFG_AHB_CLK 33
> +#define GCC_GPU_GPLL0_CLK_SRC 34
> +#define GCC_GPU_GPLL0_DIV_CLK_SRC 35
> +#define GCC_GPU_IREF_EN 36
> +#define GCC_GPU_MEMNOC_GFX_CLK 37
> +#define GCC_GPU_SNOC_DVM_GFX_CLK 38
> +#define GCC_NPU_AXI_CLK 39
> +#define GCC_NPU_BWMON_AXI_CLK 40
> +#define GCC_NPU_BWMON_CFG_AHB_CLK 41
> +#define GCC_NPU_CFG_AHB_CLK 42
> +#define GCC_NPU_DMA_CLK 43
> +#define GCC_NPU_GPLL0_CLK_SRC 44
> +#define GCC_NPU_GPLL0_DIV_CLK_SRC 45
> +#define GCC_PCIE0_PHY_REFGEN_CLK 46
> +#define GCC_PCIE1_PHY_REFGEN_CLK 47
> +#define GCC_PCIE2_PHY_REFGEN_CLK 48
> +#define GCC_PCIE_0_AUX_CLK 49
> +#define GCC_PCIE_0_AUX_CLK_SRC 50
> +#define GCC_PCIE_0_CFG_AHB_CLK 51
> +#define GCC_PCIE_0_MSTR_AXI_CLK 52
> +#define GCC_PCIE_0_PIPE_CLK 53
> +#define GCC_PCIE_0_SLV_AXI_CLK 54
> +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 55
> +#define GCC_PCIE_1_AUX_CLK 56
> +#define GCC_PCIE_1_AUX_CLK_SRC 57
> +#define GCC_PCIE_1_CFG_AHB_CLK 58
> +#define GCC_PCIE_1_MSTR_AXI_CLK 59
> +#define GCC_PCIE_1_PIPE_CLK 60
> +#define GCC_PCIE_1_SLV_AXI_CLK 61
> +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 62
> +#define GCC_PCIE_2_AUX_CLK 63
> +#define GCC_PCIE_2_AUX_CLK_SRC 64
> +#define GCC_PCIE_2_CFG_AHB_CLK 65
> +#define GCC_PCIE_2_MSTR_AXI_CLK 66
> +#define GCC_PCIE_2_PIPE_CLK 67
> +#define GCC_PCIE_2_SLV_AXI_CLK 68
> +#define GCC_PCIE_2_SLV_Q2A_AXI_CLK 69
> +#define GCC_PCIE_MDM_CLKREF_EN 70
> +#define GCC_PCIE_PHY_AUX_CLK 71
> +#define GCC_PCIE_PHY_REFGEN_CLK_SRC 72
> +#define GCC_PCIE_WIFI_CLKREF_EN 73
> +#define GCC_PCIE_WIGIG_CLKREF_EN 74
> +#define GCC_PDM2_CLK 75
> +#define GCC_PDM2_CLK_SRC 76
> +#define GCC_PDM_AHB_CLK 77
> +#define GCC_PDM_XO4_CLK 78
> +#define GCC_PRNG_AHB_CLK 89
> +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 80
> +#define GCC_QMIP_CAMERA_RT_AHB_CLK 81
> +#define GCC_QMIP_DISP_AHB_CLK 82
> +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 83
> +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 84
> +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 85
> +#define GCC_QUPV3_WRAP0_CORE_CLK 86
> +#define GCC_QUPV3_WRAP0_S0_CLK 87
> +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 88
> +#define GCC_QUPV3_WRAP0_S1_CLK 89
> +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 90
> +#define GCC_QUPV3_WRAP0_S2_CLK 91
> +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 92
> +#define GCC_QUPV3_WRAP0_S3_CLK 93
> +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 94
> +#define GCC_QUPV3_WRAP0_S4_CLK 95
> +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 96
> +#define GCC_QUPV3_WRAP0_S5_CLK 97
> +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 98
> +#define GCC_QUPV3_WRAP0_S6_CLK 99
> +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 100
> +#define GCC_QUPV3_WRAP0_S7_CLK 101
> +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 102
> +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 103
> +#define GCC_QUPV3_WRAP1_CORE_CLK 104
> +#define GCC_QUPV3_WRAP1_S0_CLK 105
> +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 106
> +#define GCC_QUPV3_WRAP1_S1_CLK 107
> +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 108
> +#define GCC_QUPV3_WRAP1_S2_CLK 109
> +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 110
> +#define GCC_QUPV3_WRAP1_S3_CLK 111
> +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 112
> +#define GCC_QUPV3_WRAP1_S4_CLK 113
> +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 114
> +#define GCC_QUPV3_WRAP1_S5_CLK 115
> +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 116
> +#define GCC_QUPV3_WRAP2_CORE_2X_CLK 117
> +#define GCC_QUPV3_WRAP2_CORE_CLK 118
> +#define GCC_QUPV3_WRAP2_S0_CLK 119
> +#define GCC_QUPV3_WRAP2_S0_CLK_SRC 120
> +#define GCC_QUPV3_WRAP2_S1_CLK 121
> +#define GCC_QUPV3_WRAP2_S1_CLK_SRC 122
> +#define GCC_QUPV3_WRAP2_S2_CLK 123
> +#define GCC_QUPV3_WRAP2_S2_CLK_SRC 124
> +#define GCC_QUPV3_WRAP2_S3_CLK 125
> +#define GCC_QUPV3_WRAP2_S3_CLK_SRC 126
> +#define GCC_QUPV3_WRAP2_S4_CLK 127
> +#define GCC_QUPV3_WRAP2_S4_CLK_SRC 128
> +#define GCC_QUPV3_WRAP2_S5_CLK 129
> +#define GCC_QUPV3_WRAP2_S5_CLK_SRC 130
> +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 131
> +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 132
> +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 133
> +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 134
> +#define GCC_QUPV3_WRAP_2_M_AHB_CLK 135
> +#define GCC_QUPV3_WRAP_2_S_AHB_CLK 136
> +#define GCC_SDCC2_AHB_CLK 137
> +#define GCC_SDCC2_APPS_CLK 138
> +#define GCC_SDCC2_APPS_CLK_SRC 139
> +#define GCC_SDCC4_AHB_CLK 140
> +#define GCC_SDCC4_APPS_CLK 141
> +#define GCC_SDCC4_APPS_CLK_SRC 142
> +#define GCC_SYS_NOC_CPUSS_AHB_CLK 143
> +#define GCC_TSIF_AHB_CLK 144
> +#define GCC_TSIF_INACTIVITY_TIMERS_CLK 145
> +#define GCC_TSIF_REF_CLK 146
> +#define GCC_TSIF_REF_CLK_SRC 147
> +#define GCC_UFS_1X_CLKREF_EN 148
> +#define GCC_UFS_CARD_AHB_CLK 149
> +#define GCC_UFS_CARD_AXI_CLK 150
> +#define GCC_UFS_CARD_AXI_CLK_SRC 151
> +#define GCC_UFS_CARD_ICE_CORE_CLK 152
> +#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 153
> +#define GCC_UFS_CARD_PHY_AUX_CLK 154
> +#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 155
> +#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 156
> +#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 157
> +#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 158
> +#define GCC_UFS_CARD_UNIPRO_CORE_CLK 159
> +#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 160
> +#define GCC_UFS_PHY_AHB_CLK 161
> +#define GCC_UFS_PHY_AXI_CLK 162
> +#define GCC_UFS_PHY_AXI_CLK_SRC 163
> +#define GCC_UFS_PHY_ICE_CORE_CLK 164
> +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 165
> +#define GCC_UFS_PHY_PHY_AUX_CLK 166
> +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 167
> +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 168
> +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 169
> +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 170
> +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 171
> +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 172
> +#define GCC_USB30_PRIM_MASTER_CLK 173
> +#define GCC_USB30_PRIM_MASTER_CLK_SRC 174
> +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 175
> +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 176
> +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 177
> +#define GCC_USB30_PRIM_SLEEP_CLK 178
> +#define GCC_USB30_SEC_MASTER_CLK 179
> +#define GCC_USB30_SEC_MASTER_CLK_SRC 180
> +#define GCC_USB30_SEC_MOCK_UTMI_CLK 181
> +#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 182
> +#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 183
> +#define GCC_USB30_SEC_SLEEP_CLK 184
> +#define GCC_USB3_PRIM_PHY_AUX_CLK 185
> +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 186
> +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 187
> +#define GCC_USB3_PRIM_PHY_PIPE_CLK 188
> +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 189
> +#define GCC_USB3_SEC_CLKREF_EN 190
> +#define GCC_USB3_SEC_PHY_AUX_CLK 191
> +#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 192
> +#define GCC_USB3_SEC_PHY_COM_AUX_CLK 193
> +#define GCC_USB3_SEC_PHY_PIPE_CLK 194
> +#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 195
> +#define GCC_VIDEO_AHB_CLK 196
> +#define GCC_VIDEO_AXI0_CLK 197
> +#define GCC_VIDEO_AXI1_CLK 198
> +#define GCC_VIDEO_XO_CLK 199
> +
> +/* GCC resets */
> +#define GCC_GPU_BCR 0
> +#define GCC_MMSS_BCR 1
> +#define GCC_NPU_BWMON_BCR 2
> +#define GCC_NPU_BCR 3
> +#define GCC_PCIE_0_BCR 4
> +#define GCC_PCIE_0_LINK_DOWN_BCR 5
> +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6
> +#define GCC_PCIE_0_PHY_BCR 7
> +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8
> +#define GCC_PCIE_1_BCR 9
> +#define GCC_PCIE_1_LINK_DOWN_BCR 10
> +#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 11
> +#define GCC_PCIE_1_PHY_BCR 12
> +#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 13
> +#define GCC_PCIE_2_BCR 14
> +#define GCC_PCIE_2_LINK_DOWN_BCR 15
> +#define GCC_PCIE_2_NOCSR_COM_PHY_BCR 16
> +#define GCC_PCIE_2_PHY_BCR 17
> +#define GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR 18
> +#define GCC_PCIE_PHY_BCR 19
> +#define GCC_PCIE_PHY_CFG_AHB_BCR 20
> +#define GCC_PCIE_PHY_COM_BCR 21
> +#define GCC_PDM_BCR 22
> +#define GCC_PRNG_BCR 23
> +#define GCC_QUPV3_WRAPPER_0_BCR 24
> +#define GCC_QUPV3_WRAPPER_1_BCR 25
> +#define GCC_QUPV3_WRAPPER_2_BCR 26
> +#define GCC_QUSB2PHY_PRIM_BCR 27
> +#define GCC_QUSB2PHY_SEC_BCR 28
> +#define GCC_SDCC2_BCR 29
> +#define GCC_SDCC4_BCR 30
> +#define GCC_TSIF_BCR 31
> +#define GCC_UFS_CARD_BCR 32
> +#define GCC_UFS_PHY_BCR 33
> +#define GCC_USB30_PRIM_BCR 34
> +#define GCC_USB30_SEC_BCR 35
> +#define GCC_USB3_DP_PHY_PRIM_BCR 36
> +#define GCC_USB3_DP_PHY_SEC_BCR 37
> +#define GCC_USB3_PHY_PRIM_BCR 38
> +#define GCC_USB3_PHY_SEC_BCR 39
> +#define GCC_USB3PHY_PHY_PRIM_BCR 40
> +#define GCC_USB3PHY_PHY_SEC_BCR 41
> +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 42
> +#define GCC_VIDEO_AXI0_CLK_ARES 43
> +#define GCC_VIDEO_AXI1_CLK_ARES 44
> +
> +/* GCC power domains */
> +#define PCIE_0_GDSC 0
> +#define PCIE_1_GDSC 1
> +#define PCIE_2_GDSC 2
> +#define UFS_CARD_GDSC 3
> +#define UFS_PHY_GDSC 4
> +#define USB30_PRIM_GDSC 5
> +#define USB30_SEC_GDSC 6
> +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 7
> +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 8
> +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 9
> +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC 10
> +
> +#endif
> --
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