2020-01-21 10:24:09

by Manish Narani

[permalink] [raw]
Subject: [PATCH 0/4] Enhancements and Bug Fixes in ZynqMP SDHCI

This patch series includes:
-> Mark the Tap Delay Node as valid for ioctl calls
-> Add support for DLL reset in firmware driver
-> Add support to reset DLL from Arasan SDHCI driver for ZynqMP platform
-> Fix incorrect base clock reporting issue

Manish Narani (4):
firmware: xilinx: Add ZynqMP Tap Delay setup ioctl to the valid list
firmware: xilinx: Add DLL reset support
mmc: sdhci-of-arasan: Add support for DLL reset for ZynqMP platforms
sdhci: arasan: Remove quirk for broken base clock

drivers/firmware/xilinx/zynqmp.c | 2 +
drivers/mmc/host/sdhci-of-arasan.c | 59 +++++++++++++++++++++++++++-
include/linux/firmware/xlnx-zynqmp.h | 9 ++++-
3 files changed, 68 insertions(+), 2 deletions(-)

--
2.17.1


2020-01-21 10:24:40

by Manish Narani

[permalink] [raw]
Subject: [PATCH 2/4] firmware: xilinx: Add DLL reset support

SD DLL resets are required for some of the operations on ZynqMP platform.
Add DLL reset support in ZynqMP firmware driver for SD DLL reset.

Signed-off-by: Manish Narani <[email protected]>
---
drivers/firmware/xilinx/zynqmp.c | 1 +
include/linux/firmware/xlnx-zynqmp.h | 9 ++++++++-
2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index 89eb198cee5e..165ec0f1e10a 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -469,6 +469,7 @@ static int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
static inline int zynqmp_is_valid_ioctl(u32 ioctl_id)
{
switch (ioctl_id) {
+ case IOCTL_SD_DLL_RESET:
case IOCTL_SET_SD_TAPDELAY:
case IOCTL_SET_PLL_FRAC_MODE:
case IOCTL_GET_PLL_FRAC_MODE:
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index e41ad9e37136..01a6d972b8a8 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -92,7 +92,8 @@ enum pm_ret_status {
};

enum pm_ioctl_id {
- IOCTL_SET_SD_TAPDELAY = 7,
+ IOCTL_SD_DLL_RESET = 6,
+ IOCTL_SET_SD_TAPDELAY,
IOCTL_SET_PLL_FRAC_MODE,
IOCTL_GET_PLL_FRAC_MODE,
IOCTL_SET_PLL_FRAC_DATA,
@@ -262,6 +263,12 @@ enum tap_delay_type {
PM_TAPDELAY_OUTPUT,
};

+enum dll_reset_type {
+ PM_DLL_RESET_ASSERT,
+ PM_DLL_RESET_RELEASE,
+ PM_DLL_RESET_PULSE,
+};
+
/**
* struct zynqmp_pm_query_data - PM query data
* @qid: query ID
--
2.17.1

2020-02-04 11:41:49

by Michal Simek

[permalink] [raw]
Subject: Re: [PATCH 2/4] firmware: xilinx: Add DLL reset support

On 21. 01. 20 11:21, Manish Narani wrote:
> SD DLL resets are required for some of the operations on ZynqMP platform.
> Add DLL reset support in ZynqMP firmware driver for SD DLL reset.
>
> Signed-off-by: Manish Narani <[email protected]>
> ---
> drivers/firmware/xilinx/zynqmp.c | 1 +
> include/linux/firmware/xlnx-zynqmp.h | 9 ++++++++-
> 2 files changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
> index 89eb198cee5e..165ec0f1e10a 100644
> --- a/drivers/firmware/xilinx/zynqmp.c
> +++ b/drivers/firmware/xilinx/zynqmp.c
> @@ -469,6 +469,7 @@ static int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id)
> static inline int zynqmp_is_valid_ioctl(u32 ioctl_id)
> {
> switch (ioctl_id) {
> + case IOCTL_SD_DLL_RESET:
> case IOCTL_SET_SD_TAPDELAY:
> case IOCTL_SET_PLL_FRAC_MODE:
> case IOCTL_GET_PLL_FRAC_MODE:
> diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
> index e41ad9e37136..01a6d972b8a8 100644
> --- a/include/linux/firmware/xlnx-zynqmp.h
> +++ b/include/linux/firmware/xlnx-zynqmp.h
> @@ -92,7 +92,8 @@ enum pm_ret_status {
> };
>
> enum pm_ioctl_id {
> - IOCTL_SET_SD_TAPDELAY = 7,
> + IOCTL_SD_DLL_RESET = 6,
> + IOCTL_SET_SD_TAPDELAY,
> IOCTL_SET_PLL_FRAC_MODE,
> IOCTL_GET_PLL_FRAC_MODE,
> IOCTL_SET_PLL_FRAC_DATA,
> @@ -262,6 +263,12 @@ enum tap_delay_type {
> PM_TAPDELAY_OUTPUT,
> };
>
> +enum dll_reset_type {
> + PM_DLL_RESET_ASSERT,
> + PM_DLL_RESET_RELEASE,
> + PM_DLL_RESET_PULSE,
> +};
> +
> /**
> * struct zynqmp_pm_query_data - PM query data
> * @qid: query ID
>

Acked-by: Michal Simek <[email protected]>

Thanks,
Michal

2020-02-13 13:57:05

by Ulf Hansson

[permalink] [raw]
Subject: Re: [PATCH 0/4] Enhancements and Bug Fixes in ZynqMP SDHCI

On Tue, 21 Jan 2020 at 11:21, Manish Narani <[email protected]> wrote:
>
> This patch series includes:
> -> Mark the Tap Delay Node as valid for ioctl calls
> -> Add support for DLL reset in firmware driver
> -> Add support to reset DLL from Arasan SDHCI driver for ZynqMP platform
> -> Fix incorrect base clock reporting issue
>
> Manish Narani (4):
> firmware: xilinx: Add ZynqMP Tap Delay setup ioctl to the valid list
> firmware: xilinx: Add DLL reset support
> mmc: sdhci-of-arasan: Add support for DLL reset for ZynqMP platforms
> sdhci: arasan: Remove quirk for broken base clock
>
> drivers/firmware/xilinx/zynqmp.c | 2 +
> drivers/mmc/host/sdhci-of-arasan.c | 59 +++++++++++++++++++++++++++-
> include/linux/firmware/xlnx-zynqmp.h | 9 ++++-
> 3 files changed, 68 insertions(+), 2 deletions(-)
>
> --
> 2.17.1
>

Applied for next, thanks!

Kind regards
Uffe

2020-02-14 06:39:59

by Manish Narani

[permalink] [raw]
Subject: RE: [PATCH 0/4] Enhancements and Bug Fixes in ZynqMP SDHCI

Hi Uffe,

> -----Original Message-----
> From: Ulf Hansson <[email protected]>
> Sent: Thursday, February 13, 2020 7:26 PM
> To: Manish Narani <[email protected]>
> Cc: Michal Simek <[email protected]>; Adrian Hunter
> <[email protected]>; Jolly Shah <[email protected]>; Rajan Vaja
> <[email protected]>; Nava kishore Manne <[email protected]>; Tejas
> Patel <[email protected]>; Linux ARM <linux-arm-
> [email protected]>; Linux Kernel Mailing List <linux-
> [email protected]>; [email protected]
> Subject: Re: [PATCH 0/4] Enhancements and Bug Fixes in ZynqMP SDHCI
>
> On Tue, 21 Jan 2020 at 11:21, Manish Narani <[email protected]>
> wrote:
> >
> > This patch series includes:
> > -> Mark the Tap Delay Node as valid for ioctl calls
> > -> Add support for DLL reset in firmware driver
> > -> Add support to reset DLL from Arasan SDHCI driver for ZynqMP platform
> > -> Fix incorrect base clock reporting issue
> >
> > Manish Narani (4):
> > firmware: xilinx: Add ZynqMP Tap Delay setup ioctl to the valid list
> > firmware: xilinx: Add DLL reset support
> > mmc: sdhci-of-arasan: Add support for DLL reset for ZynqMP platforms
> > sdhci: arasan: Remove quirk for broken base clock
> >
> > drivers/firmware/xilinx/zynqmp.c | 2 +
> > drivers/mmc/host/sdhci-of-arasan.c | 59
> +++++++++++++++++++++++++++-
> > include/linux/firmware/xlnx-zynqmp.h | 9 ++++-
> > 3 files changed, 68 insertions(+), 2 deletions(-)
> >
> > --
> > 2.17.1
> >
>
> Applied for next, thanks!
Thanks a lot!

- Manish