2020-02-28 13:45:21

by Dennis-YC Hsieh

Subject: [PATCH v3 00/13] support gce on mt6779 platform

This patch support gce on mt6779 platform.

Change since v2:
- rebase onto 5.6-rc1
- remove unnecessary definition
- add clear parameter in wfe api
- separate assign and write_s api
- add jump api instead of finalize in loop

Change since v1:
- change write_s interface to consistant with read_s
- remove combination function and design write_s_value function
- do not check finalized and export finalize function
- give arg_a name



Dennis YC Hsieh (13):
dt-binding: gce: add gce header file for mt6779
mailbox: cmdq: variablize address shift in platform
mailbox: cmdq: support mt6779 gce platform definition
mailbox: mediatek: cmdq: clear task in channel before shutdown
soc: mediatek: cmdq: return send msg error code
soc: mediatek: cmdq: add assign function
soc: mediatek: cmdq: add write_s function
soc: mediatek: cmdq: add read_s function
soc: mediatek: cmdq: add write_s value function
soc: mediatek: cmdq: export finalize function
soc: mediatek: cmdq: add jump function
soc: mediatek: cmdq: add clear option in cmdq_pkt_wfe api
soc: mediatek: cmdq: add set event function

.../devicetree/bindings/mailbox/mtk-gce.txt | 8 +-
drivers/mailbox/mtk-cmdq-mailbox.c | 97 +++++++-
drivers/soc/mediatek/mtk-cmdq-helper.c | 143 ++++++++++-
include/dt-bindings/gce/mt6779-gce.h | 222 ++++++++++++++++++
include/linux/mailbox/mtk-cmdq-mailbox.h | 10 +-
include/linux/soc/mediatek/mtk-cmdq.h | 94 +++++++-
6 files changed, 543 insertions(+), 31 deletions(-)
create mode 100644 include/dt-bindings/gce/mt6779-gce.h

--
2.18.0

2020-02-28 13:45:32

by Dennis-YC Hsieh

Subject: [PATCH v3 00/13] support gce on mt6779 platform

This patch support gce on mt6779 platform.

Change since v2:
- rebase onto 5.6-rc1
- remove unnecessary definition
- add clear parameter in wfe api
- separate assign and write_s api
- add jump api instead of finalize in loop

Change since v1:
- change write_s interface to consistant with read_s
- remove combination function and design write_s_value function
- do not check finalized and export finalize function
- give arg_a name


Dennis YC Hsieh (13):
dt-binding: gce: add gce header file for mt6779
mailbox: cmdq: variablize address shift in platform
mailbox: cmdq: support mt6779 gce platform definition
mailbox: mediatek: cmdq: clear task in channel before shutdown
soc: mediatek: cmdq: return send msg error code
soc: mediatek: cmdq: add assign function
soc: mediatek: cmdq: add write_s function
soc: mediatek: cmdq: add read_s function
soc: mediatek: cmdq: add write_s value function
soc: mediatek: cmdq: export finalize function
soc: mediatek: cmdq: add jump function
soc: mediatek: cmdq: add clear option in cmdq_pkt_wfe api
soc: mediatek: cmdq: add set event function

.../devicetree/bindings/mailbox/mtk-gce.txt | 8 +-
drivers/mailbox/mtk-cmdq-mailbox.c | 97 +++++++-
drivers/soc/mediatek/mtk-cmdq-helper.c | 143 ++++++++++-
include/dt-bindings/gce/mt6779-gce.h | 222 ++++++++++++++++++
include/linux/mailbox/mtk-cmdq-mailbox.h | 10 +-
include/linux/soc/mediatek/mtk-cmdq.h | 94 +++++++-
6 files changed, 543 insertions(+), 31 deletions(-)
create mode 100644 include/dt-bindings/gce/mt6779-gce.h

--
2.18.0

2020-02-28 13:45:37

by Dennis-YC Hsieh

Subject: [PATCH v3 05/13] soc: mediatek: cmdq: return send msg error code

Return error code to client if send message fail,
so that client has chance to error handling.

Fixes: 576f1b4bc802 ("soc: mediatek: Add Mediatek CMDQ helper")
Signed-off-by: Dennis YC Hsieh <[email protected]>
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
index 2e1bc513569b..0698612de5ad 100644
--- a/drivers/soc/mediatek/mtk-cmdq-helper.c
+++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
@@ -351,11 +351,11 @@ int cmdq_pkt_flush_async(struct cmdq_pkt *pkt, cmdq_async_flush_cb cb,
spin_unlock_irqrestore(&client->lock, flags);
}

- mbox_send_message(client->chan, pkt);
+ err = mbox_send_message(client->chan, pkt);
/* We can send next packet immediately, so just call txdone. */
mbox_client_txdone(client->chan, 0);

- return 0;
+ return err;
}
EXPORT_SYMBOL(cmdq_pkt_flush_async);

--
2.18.0

2020-02-28 13:45:42

by Dennis-YC Hsieh

Subject: [PATCH v3 13/13] soc: mediatek: cmdq: add set event function

Add set event function in cmdq helper functions to set specific event.

Signed-off-by: Dennis YC Hsieh <[email protected]>
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 15 +++++++++++++++
include/linux/mailbox/mtk-cmdq-mailbox.h | 1 +
include/linux/soc/mediatek/mtk-cmdq.h | 9 +++++++++
3 files changed, 25 insertions(+)

diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
index 406e1d34d234..738f83d90b59 100644
--- a/drivers/soc/mediatek/mtk-cmdq-helper.c
+++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
@@ -326,6 +326,21 @@ int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event)
}
EXPORT_SYMBOL(cmdq_pkt_clear_event);

+int cmdq_pkt_set_event(struct cmdq_pkt *pkt, u16 event)
+{
+ struct cmdq_instruction inst = { {0} };
+
+ if (event >= CMDQ_MAX_EVENT)
+ return -EINVAL;
+
+ inst.op = CMDQ_CODE_WFE;
+ inst.value = CMDQ_WFE_UPDATE | CMDQ_WFE_UPDATE_VALUE;
+ inst.event = event;
+
+ return cmdq_pkt_append_command(pkt, inst);
+}
+EXPORT_SYMBOL(cmdq_pkt_set_event);
+
int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys,
u16 offset, u32 value)
{
diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h
index 42d2a30e6a70..ba2d811183a9 100644
--- a/include/linux/mailbox/mtk-cmdq-mailbox.h
+++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
@@ -17,6 +17,7 @@
#define CMDQ_JUMP_PASS CMDQ_INST_SIZE

#define CMDQ_WFE_UPDATE BIT(31)
+#define CMDQ_WFE_UPDATE_VALUE BIT(16)
#define CMDQ_WFE_WAIT BIT(15)
#define CMDQ_WFE_WAIT_VALUE 0x1

diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
index d63749440697..ca70296ae120 100644
--- a/include/linux/soc/mediatek/mtk-cmdq.h
+++ b/include/linux/soc/mediatek/mtk-cmdq.h
@@ -168,6 +168,15 @@ int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event, bool clear);
*/
int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event);

+/**
+ * cmdq_pkt_set_event() - append set event command to the CMDQ packet
+ * @pkt: the CMDQ packet
+ * @event: the desired event to be set
+ *
+ * Return: 0 for success; else the error code is returned
+ */
+int cmdq_pkt_set_event(struct cmdq_pkt *pkt, u16 event);
+
/**
* cmdq_pkt_poll() - Append polling command to the CMDQ packet, ask GCE to
* execute an instruction that wait for a specified
--
2.18.0

2020-02-28 13:45:53

by Dennis-YC Hsieh

Subject: [PATCH v3 04/13] mailbox: mediatek: cmdq: clear task in channel before shutdown

Do success callback in channel when shutdown. For those task not finish,
callback with error code thus client has chance to cleanup or reset.

Signed-off-by: Dennis YC Hsieh <[email protected]>
---
drivers/mailbox/mtk-cmdq-mailbox.c | 38 ++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index 7246b7e21a2e..50dec015593f 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -387,6 +387,12 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)

if (list_empty(&thread->task_busy_list)) {
WARN_ON(clk_enable(cmdq->clock) < 0);
+ /*
+ * The thread reset will clear thread related register to 0,
+ * including pc, end, priority, irq, suspend and enable. Thus
+ * set CMDQ_THR_ENABLED to CMDQ_THR_ENABLE_TASK will enable
+ * thread and make it running.
+ */
WARN_ON(cmdq_thread_reset(cmdq, thread) < 0);

writel(task->pa_base >> cmdq->shift_pa,
@@ -450,6 +456,38 @@ static int cmdq_mbox_startup(struct mbox_chan *chan)

static void cmdq_mbox_shutdown(struct mbox_chan *chan)
{
+ struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
+ struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
+ struct cmdq_task *task, *tmp;
+ unsigned long flags;
+
+ spin_lock_irqsave(&thread->chan->lock, flags);
+ if (list_empty(&thread->task_busy_list))
+ goto done;
+
+ WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
+
+ /* make sure executed tasks have success callback */
+ cmdq_thread_irq_handler(cmdq, thread);
+ if (list_empty(&thread->task_busy_list))
+ goto done;
+
+ list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
+ list_entry) {
+ cmdq_task_exec_done(task, -ECONNABORTED);
+ kfree(task);
+ }
+
+ cmdq_thread_disable(cmdq, thread);
+ clk_disable(cmdq->clock);
+done:
+ /*
+ * The thread->task_busy_list empty means thread already disable. The
+ * cmdq_mbox_send_data() always reset thread which clear disable and
+ * suspend statue when first pkt send to channel, so there is no need
+ * to do any operation here, only unlock and leave.
+ */
+ spin_unlock_irqrestore(&thread->chan->lock, flags);
}

static const struct mbox_chan_ops cmdq_mbox_chan_ops = {
--
2.18.0

2020-02-28 13:46:07

by Dennis-YC Hsieh

Subject: [PATCH v3 08/13] soc: mediatek: cmdq: add read_s function

Add read_s function in cmdq helper functions which support read value from
register or dma physical address into gce internal register.

Signed-off-by: Dennis YC Hsieh <[email protected]>
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 15 +++++++++++++++
include/linux/mailbox/mtk-cmdq-mailbox.h | 1 +
include/linux/soc/mediatek/mtk-cmdq.h | 13 +++++++++++++
3 files changed, 29 insertions(+)

diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
index 68b42c935fe6..428f99288ca6 100644
--- a/drivers/soc/mediatek/mtk-cmdq-helper.c
+++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
@@ -226,6 +226,21 @@ int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,
}
EXPORT_SYMBOL(cmdq_pkt_write_mask);

+int cmdq_pkt_read_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx, u16 addr_low,
+ u16 reg_idx)
+{
+ struct cmdq_instruction inst = { {0} };
+
+ inst.op = CMDQ_CODE_READ_S;
+ inst.dst_t = CMDQ_REG_TYPE;
+ inst.sop = high_addr_reg_idx;
+ inst.reg_dst = reg_idx;
+ inst.src_reg = addr_low;
+
+ return cmdq_pkt_append_command(pkt, inst);
+}
+EXPORT_SYMBOL(cmdq_pkt_read_s);
+
int cmdq_pkt_write_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
u16 addr_low, u16 src_reg_idx, u32 mask)
{
diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h
index 8ef87e1bd03b..3f6bc0dfd5da 100644
--- a/include/linux/mailbox/mtk-cmdq-mailbox.h
+++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
@@ -59,6 +59,7 @@ enum cmdq_code {
CMDQ_CODE_JUMP = 0x10,
CMDQ_CODE_WFE = 0x20,
CMDQ_CODE_EOC = 0x40,
+ CMDQ_CODE_READ_S = 0x80,
CMDQ_CODE_WRITE_S = 0x90,
CMDQ_CODE_WRITE_S_MASK = 0x91,
CMDQ_CODE_LOGIC = 0xa0,
diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
index c72d826d8934..01b4184af310 100644
--- a/include/linux/soc/mediatek/mtk-cmdq.h
+++ b/include/linux/soc/mediatek/mtk-cmdq.h
@@ -104,6 +104,19 @@ int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value);
int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,
u16 offset, u32 value, u32 mask);

+/*
+ * cmdq_pkt_read_s() - append read_s command to the CMDQ packet
+ * @pkt: the CMDQ packet
+ * @high_addr_reg_idx: internal regisger ID which contains high address of pa
+ * @addr_low: low address of pa
+ * @addr: the physical address of register or dma to read
+ * @reg_idx: the CMDQ internal register ID to cache read data
+ *
+ * Return: 0 for success; else the error code is returned
+ */
+int cmdq_pkt_read_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx, u16 addr_low,
+ u16 reg_idx);
+
/**
* cmdq_pkt_write_s() - append write_s command to the CMDQ packet
* @pkt: the CMDQ packet
--
2.18.0

2020-02-28 13:46:08

by Dennis-YC Hsieh

Subject: [PATCH v3 10/13] soc: mediatek: cmdq: export finalize function

Export finalize function to client which helps append eoc and jump
command to pkt.

Signed-off-by: Dennis YC Hsieh <[email protected]>
Reviewed-by: CK Hu <[email protected]>
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 7 ++-----
include/linux/soc/mediatek/mtk-cmdq.h | 8 ++++++++
2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
index 1336523eb7d4..58fec634dcf1 100644
--- a/drivers/soc/mediatek/mtk-cmdq-helper.c
+++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
@@ -372,7 +372,7 @@ int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value)
}
EXPORT_SYMBOL(cmdq_pkt_assign);

-static int cmdq_pkt_finalize(struct cmdq_pkt *pkt)
+int cmdq_pkt_finalize(struct cmdq_pkt *pkt)
{
struct cmdq_instruction inst = { {0} };
int err;
@@ -392,6 +392,7 @@ static int cmdq_pkt_finalize(struct cmdq_pkt *pkt)

return err;
}
+EXPORT_SYMBOL(cmdq_pkt_finalize);

static void cmdq_pkt_flush_async_cb(struct cmdq_cb_data data)
{
@@ -426,10 +427,6 @@ int cmdq_pkt_flush_async(struct cmdq_pkt *pkt, cmdq_async_flush_cb cb,
unsigned long flags = 0;
struct cmdq_client *client = (struct cmdq_client *)pkt->cl;

- err = cmdq_pkt_finalize(pkt);
- if (err < 0)
- return err;
-
pkt->cb.cb = cb;
pkt->cb.data = data;
pkt->async_cb.cb = cmdq_pkt_flush_async_cb;
diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
index fec292aac83c..99e77155f967 100644
--- a/include/linux/soc/mediatek/mtk-cmdq.h
+++ b/include/linux/soc/mediatek/mtk-cmdq.h
@@ -213,6 +213,14 @@ int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys,
*/
int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value);

+/**
+ * cmdq_pkt_finalize() - Append EOC and jump command to pkt.
+ * @pkt: the CMDQ packet
+ *
+ * Return: 0 for success; else the error code is returned
+ */
+int cmdq_pkt_finalize(struct cmdq_pkt *pkt);
+
/**
* cmdq_pkt_flush_async() - trigger CMDQ to asynchronously execute the CMDQ
* packet and call back at the end of done packet
--
2.18.0

2020-02-28 13:46:11

by Dennis-YC Hsieh

Subject: [PATCH v3 06/13] soc: mediatek: cmdq: add assign function

Add assign function in cmdq helper which assign constant value into
internal register by index.

Signed-off-by: Dennis YC Hsieh <[email protected]>
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 24 +++++++++++++++++++++++-
include/linux/mailbox/mtk-cmdq-mailbox.h | 1 +
include/linux/soc/mediatek/mtk-cmdq.h | 14 ++++++++++++++
3 files changed, 38 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
index 0698612de5ad..8342a5c94bc7 100644
--- a/drivers/soc/mediatek/mtk-cmdq-helper.c
+++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
@@ -12,6 +12,7 @@
#define CMDQ_WRITE_ENABLE_MASK BIT(0)
#define CMDQ_POLL_ENABLE_MASK BIT(0)
#define CMDQ_EOC_IRQ_EN BIT(0)
+#define CMDQ_REG_TYPE 1

struct cmdq_instruction {
union {
@@ -21,8 +22,17 @@ struct cmdq_instruction {
union {
u16 offset;
u16 event;
+ u16 reg_dst;
+ };
+ union {
+ u8 subsys;
+ struct {
+ u8 sop:5;
+ u8 arg_c_t:1;
+ u8 arg_b_t:1;
+ u8 dst_t:1;
+ };
};
- u8 subsys;
u8 op;
};

@@ -277,6 +287,18 @@ int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys,
}
EXPORT_SYMBOL(cmdq_pkt_poll_mask);

+int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value)
+{
+ struct cmdq_instruction inst = { {0} };
+
+ inst.op = CMDQ_CODE_LOGIC;
+ inst.dst_t = CMDQ_REG_TYPE;
+ inst.reg_dst = reg_idx;
+ inst.value = value;
+ return cmdq_pkt_append_command(pkt, inst);
+}
+EXPORT_SYMBOL(cmdq_pkt_assign);
+
static int cmdq_pkt_finalize(struct cmdq_pkt *pkt)
{
struct cmdq_instruction inst = { {0} };
diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h
index dfe5b2eb85cc..121c3bb6d3de 100644
--- a/include/linux/mailbox/mtk-cmdq-mailbox.h
+++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
@@ -59,6 +59,7 @@ enum cmdq_code {
CMDQ_CODE_JUMP = 0x10,
CMDQ_CODE_WFE = 0x20,
CMDQ_CODE_EOC = 0x40,
+ CMDQ_CODE_LOGIC = 0xa0,
};

enum cmdq_cb_status {
diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
index a74c1d5acdf3..83340211e1d3 100644
--- a/include/linux/soc/mediatek/mtk-cmdq.h
+++ b/include/linux/soc/mediatek/mtk-cmdq.h
@@ -152,6 +152,20 @@ int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys,
*/
int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys,
u16 offset, u32 value, u32 mask);
+
+/**
+ * cmdq_pkt_assign() - Append logic assign command to the CMDQ packet, ask GCE
+ * to execute an instruction that set a constant value into
+ * internal register and use as value, mask or address in
+ * read/write instruction.
+ * @pkt: the CMDQ packet
+ * @reg_idx: the CMDQ internal register ID
+ * @value: the specified value
+ *
+ * Return: 0 for success; else the error code is returned
+ */
+int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value);
+
/**
* cmdq_pkt_flush_async() - trigger CMDQ to asynchronously execute the CMDQ
* packet and call back at the end of done packet
--
2.18.0

2020-02-28 13:46:13

by Dennis-YC Hsieh

Subject: [PATCH v3 03/13] mailbox: cmdq: support mt6779 gce platform definition

Add gce v4 hardware support with different thread number and shift.

Signed-off-by: Dennis YC Hsieh <[email protected]>
Reviewed-by: CK Hu <[email protected]>
---
drivers/mailbox/mtk-cmdq-mailbox.c | 2 ++
1 file changed, 2 insertions(+)

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index a98f0357dd7d..7246b7e21a2e 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -572,10 +572,12 @@ static const struct dev_pm_ops cmdq_pm_ops = {

static const struct gce_plat gce_plat_v2 = {.thread_nr = 16};
static const struct gce_plat gce_plat_v3 = {.thread_nr = 24};
+static const struct gce_plat gce_plat_v4 = {.thread_nr = 24, .shift = 3};

static const struct of_device_id cmdq_of_ids[] = {
{.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2},
{.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3},
+ {.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_v4},
{}
};

--
2.18.0

2020-02-28 13:46:17

by Dennis-YC Hsieh

Subject: [PATCH v3 01/13] dt-binding: gce: add gce header file for mt6779

Add documentation for the mt6779 gce.

Add gce header file defined the gce hardware event,
subsys number and constant for mt6779.

Signed-off-by: Dennis YC Hsieh <[email protected]>
---
.../devicetree/bindings/mailbox/mtk-gce.txt | 8 +-
include/dt-bindings/gce/mt6779-gce.h | 222 ++++++++++++++++++
2 files changed, 227 insertions(+), 3 deletions(-)
create mode 100644 include/dt-bindings/gce/mt6779-gce.h

diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
index 7b13787ab13d..82c0a83fed09 100644
--- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
+++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
@@ -9,7 +9,8 @@ CMDQ driver uses mailbox framework for communication. Please refer to
mailbox.txt for generic information about mailbox device-tree bindings.

Required properties:
-- compatible: can be "mediatek,mt8173-gce" or "mediatek,mt8183-gce"
+- compatible: can be "mediatek,mt8173-gce", "mediatek,mt8183-gce" or
+ "mediatek,mt6779-gce".
- reg: Address range of the GCE unit
- interrupts: The interrupt signal from the GCE block
- clock: Clocks according to the common clock binding
@@ -36,8 +37,9 @@ Optional properties for a client device:
start_offset: the start offset of register address that GCE can access.
size: the total size of register address that GCE can access.

-Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'
-or 'dt-binding/gce/mt8183-gce.h'. Such as sub-system ids, thread priority, event ids.
+Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h',
+'dt-binding/gce/mt8183-gce.h' or 'dt-bindings/gce/mt6779-gce.h'. Such as
+sub-system ids, thread priority, event ids.

Example:

diff --git a/include/dt-bindings/gce/mt6779-gce.h b/include/dt-bindings/gce/mt6779-gce.h
new file mode 100644
index 000000000000..06101316ace4
--- /dev/null
+++ b/include/dt-bindings/gce/mt6779-gce.h
@@ -0,0 +1,222 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Dennis-YC Hsieh <[email protected]>
+ */
+
+#ifndef _DT_BINDINGS_GCE_MT6779_H
+#define _DT_BINDINGS_GCE_MT6779_H
+
+#define CMDQ_NO_TIMEOUT 0xffffffff
+
+/* GCE HW thread priority */
+#define CMDQ_THR_PRIO_LOWEST 0
+#define CMDQ_THR_PRIO_1 1
+#define CMDQ_THR_PRIO_2 2
+#define CMDQ_THR_PRIO_3 3
+#define CMDQ_THR_PRIO_4 4
+#define CMDQ_THR_PRIO_5 5
+#define CMDQ_THR_PRIO_6 6
+#define CMDQ_THR_PRIO_HIGHEST 7
+
+/* GCE subsys table */
+#define SUBSYS_1300XXXX 0
+#define SUBSYS_1400XXXX 1
+#define SUBSYS_1401XXXX 2
+#define SUBSYS_1402XXXX 3
+#define SUBSYS_1502XXXX 4
+#define SUBSYS_1880XXXX 5
+#define SUBSYS_1881XXXX 6
+#define SUBSYS_1882XXXX 7
+#define SUBSYS_1883XXXX 8
+#define SUBSYS_1884XXXX 9
+#define SUBSYS_1000XXXX 10
+#define SUBSYS_1001XXXX 11
+#define SUBSYS_1002XXXX 12
+#define SUBSYS_1003XXXX 13
+#define SUBSYS_1004XXXX 14
+#define SUBSYS_1005XXXX 15
+#define SUBSYS_1020XXXX 16
+#define SUBSYS_1028XXXX 17
+#define SUBSYS_1700XXXX 18
+#define SUBSYS_1701XXXX 19
+#define SUBSYS_1702XXXX 20
+#define SUBSYS_1703XXXX 21
+#define SUBSYS_1800XXXX 22
+#define SUBSYS_1801XXXX 23
+#define SUBSYS_1802XXXX 24
+#define SUBSYS_1804XXXX 25
+#define SUBSYS_1805XXXX 26
+#define SUBSYS_1808XXXX 27
+#define SUBSYS_180aXXXX 28
+#define SUBSYS_180bXXXX 29
+#define CMDQ_SUBSYS_OFF 32
+
+/* GCE hardware events */
+#define CMDQ_EVENT_DISP_RDMA0_SOF 0
+#define CMDQ_EVENT_DISP_RDMA1_SOF 1
+#define CMDQ_EVENT_MDP_RDMA0_SOF 2
+#define CMDQ_EVENT_MDP_RDMA1_SOF 3
+#define CMDQ_EVENT_MDP_RSZ0_SOF 4
+#define CMDQ_EVENT_MDP_RSZ1_SOF 5
+#define CMDQ_EVENT_MDP_TDSHP_SOF 6
+#define CMDQ_EVENT_MDP_WROT0_SOF 7
+#define CMDQ_EVENT_MDP_WROT1_SOF 8
+#define CMDQ_EVENT_DISP_OVL0_SOF 9
+#define CMDQ_EVENT_DISP_2L_OVL0_SOF 10
+#define CMDQ_EVENT_DISP_2L_OVL1_SOF 11
+#define CMDQ_EVENT_DISP_WDMA0_SOF 12
+#define CMDQ_EVENT_DISP_COLOR0_SOF 13
+#define CMDQ_EVENT_DISP_CCORR0_SOF 14
+#define CMDQ_EVENT_DISP_AAL0_SOF 15
+#define CMDQ_EVENT_DISP_GAMMA0_SOF 16
+#define CMDQ_EVENT_DISP_DITHER0_SOF 17
+#define CMDQ_EVENT_DISP_PWM0_SOF 18
+#define CMDQ_EVENT_DISP_DSI0_SOF 19
+#define CMDQ_EVENT_DISP_DPI0_SOF 20
+#define CMDQ_EVENT_DISP_POSTMASK0_SOF 21
+#define CMDQ_EVENT_DISP_RSZ0_SOF 22
+#define CMDQ_EVENT_MDP_AAL_SOF 23
+#define CMDQ_EVENT_MDP_CCORR_SOF 24
+#define CMDQ_EVENT_DISP_DBI0_SOF 25
+#define CMDQ_EVENT_ISP_RELAY_SOF 26
+#define CMDQ_EVENT_IPU_RELAY_SOF 27
+#define CMDQ_EVENT_DISP_RDMA0_EOF 28
+#define CMDQ_EVENT_DISP_RDMA1_EOF 29
+#define CMDQ_EVENT_MDP_RDMA0_EOF 30
+#define CMDQ_EVENT_MDP_RDMA1_EOF 31
+#define CMDQ_EVENT_MDP_RSZ0_EOF 32
+#define CMDQ_EVENT_MDP_RSZ1_EOF 33
+#define CMDQ_EVENT_MDP_TDSHP_EOF 34
+#define CMDQ_EVENT_MDP_WROT0_W_EOF 35
+#define CMDQ_EVENT_MDP_WROT1_W_EOF 36
+#define CMDQ_EVENT_DISP_OVL0_EOF 37
+#define CMDQ_EVENT_DISP_2L_OVL0_EOF 38
+#define CMDQ_EVENT_DISP_2L_OVL1_EOF 39
+#define CMDQ_EVENT_DISP_WDMA0_EOF 40
+#define CMDQ_EVENT_DISP_COLOR0_EOF 41
+#define CMDQ_EVENT_DISP_CCORR0_EOF 42
+#define CMDQ_EVENT_DISP_AAL0_EOF 43
+#define CMDQ_EVENT_DISP_GAMMA0_EOF 44
+#define CMDQ_EVENT_DISP_DITHER0_EOF 45
+#define CMDQ_EVENT_DISP_DSI0_EOF 46
+#define CMDQ_EVENT_DISP_DPI0_EOF 47
+#define CMDQ_EVENT_DISP_RSZ0_EOF 49
+#define CMDQ_EVENT_MDP_AAL_FRAME_DONE 50
+#define CMDQ_EVENT_MDP_CCORR_FRAME_DONE 51
+#define CMDQ_EVENT_DISP_POSTMASK0_FRAME_DONE 52
+#define CMDQ_EVENT_MUTEX0_STREAM_EOF 130
+#define CMDQ_EVENT_MUTEX1_STREAM_EOF 131
+#define CMDQ_EVENT_MUTEX2_STREAM_EOF 132
+#define CMDQ_EVENT_MUTEX3_STREAM_EOF 133
+#define CMDQ_EVENT_MUTEX4_STREAM_EOF 134
+#define CMDQ_EVENT_MUTEX5_STREAM_EOF 135
+#define CMDQ_EVENT_MUTEX6_STREAM_EOF 136
+#define CMDQ_EVENT_MUTEX7_STREAM_EOF 137
+#define CMDQ_EVENT_MUTEX8_STREAM_EOF 138
+#define CMDQ_EVENT_MUTEX9_STREAM_EOF 139
+#define CMDQ_EVENT_MUTEX10_STREAM_EOF 140
+#define CMDQ_EVENT_MUTEX11_STREAM_EOF 141
+#define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 142
+#define CMDQ_EVENT_DISP_RDMA1_UNDERRUN 143
+#define CMDQ_EVENT_DISP_RDMA2_UNDERRUN 144
+#define CMDQ_EVENT_DISP_RDMA3_UNDERRUN 145
+#define CMDQ_EVENT_DSI0_TE 146
+#define CMDQ_EVENT_DSI0_IRQ_EVENT 147
+#define CMDQ_EVENT_DSI0_DONE_EVENT 148
+#define CMDQ_EVENT_DISP_POSTMASK0_RST_DONE 150
+#define CMDQ_EVENT_DISP_WDMA0_RST_DONE 151
+#define CMDQ_EVENT_MDP_WROT0_RST_DONE 153
+#define CMDQ_EVENT_MDP_RDMA0_RST_DONE 154
+#define CMDQ_EVENT_DISP_OVL0_RST_DONE 155
+#define CMDQ_EVENT_DISP_OVL0_2L_RST_DONE 156
+#define CMDQ_EVENT_DISP_OVL1_2L_RST_DONE 157
+#define CMDQ_EVENT_DIP_CQ_THREAD0_EOF 257
+#define CMDQ_EVENT_DIP_CQ_THREAD1_EOF 258
+#define CMDQ_EVENT_DIP_CQ_THREAD2_EOF 259
+#define CMDQ_EVENT_DIP_CQ_THREAD3_EOF 260
+#define CMDQ_EVENT_DIP_CQ_THREAD4_EOF 261
+#define CMDQ_EVENT_DIP_CQ_THREAD5_EOF 262
+#define CMDQ_EVENT_DIP_CQ_THREAD6_EOF 263
+#define CMDQ_EVENT_DIP_CQ_THREAD7_EOF 264
+#define CMDQ_EVENT_DIP_CQ_THREAD8_EOF 265
+#define CMDQ_EVENT_DIP_CQ_THREAD9_EOF 266
+#define CMDQ_EVENT_DIP_CQ_THREAD10_EOF 267
+#define CMDQ_EVENT_DIP_CQ_THREAD11_EOF 268
+#define CMDQ_EVENT_DIP_CQ_THREAD12_EOF 269
+#define CMDQ_EVENT_DIP_CQ_THREAD13_EOF 270
+#define CMDQ_EVENT_DIP_CQ_THREAD14_EOF 271
+#define CMDQ_EVENT_DIP_CQ_THREAD15_EOF 272
+#define CMDQ_EVENT_DIP_CQ_THREAD16_EOF 273
+#define CMDQ_EVENT_DIP_CQ_THREAD17_EOF 274
+#define CMDQ_EVENT_DIP_CQ_THREAD18_EOF 275
+#define CMDQ_EVENT_DIP_DMA_ERR_EVENT 276
+#define CMDQ_EVENT_AMD_FRAME_DONE 277
+#define CMDQ_EVENT_MFB_DONE 278
+#define CMDQ_EVENT_WPE_A_EOF 279
+#define CMDQ_EVENT_VENC_EOF 289
+#define CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE 290
+#define CMDQ_EVENT_JPEG_ENC_EOF 291
+#define CMDQ_EVENT_VENC_MB_DONE 292
+#define CMDQ_EVENT_VENC_128BYTE_CNT_DONE 293
+#define CMDQ_EVENT_ISP_FRAME_DONE_A 321
+#define CMDQ_EVENT_ISP_FRAME_DONE_B 322
+#define CMDQ_EVENT_ISP_FRAME_DONE_C 323
+#define CMDQ_EVENT_ISP_CAMSV_0_PASS1_DONE 324
+#define CMDQ_EVENT_ISP_CAMSV_0_2_PASS1_DONE 325
+#define CMDQ_EVENT_ISP_CAMSV_1_PASS1_DONE 326
+#define CMDQ_EVENT_ISP_CAMSV_2_PASS1_DONE 327
+#define CMDQ_EVENT_ISP_CAMSV_3_PASS1_DONE 328
+#define CMDQ_EVENT_ISP_TSF_DONE 329
+#define CMDQ_EVENT_SENINF_0_FIFO_FULL 330
+#define CMDQ_EVENT_SENINF_1_FIFO_FULL 331
+#define CMDQ_EVENT_SENINF_2_FIFO_FULL 332
+#define CMDQ_EVENT_SENINF_3_FIFO_FULL 333
+#define CMDQ_EVENT_SENINF_4_FIFO_FULL 334
+#define CMDQ_EVENT_SENINF_5_FIFO_FULL 335
+#define CMDQ_EVENT_SENINF_6_FIFO_FULL 336
+#define CMDQ_EVENT_SENINF_7_FIFO_FULL 337
+#define CMDQ_EVENT_TG_OVRUN_A_INT_DLY 338
+#define CMDQ_EVENT_TG_OVRUN_B_INT_DLY 339
+#define CMDQ_EVENT_TG_OVRUN_C_INT 340
+#define CMDQ_EVENT_TG_GRABERR_A_INT_DLY 341
+#define CMDQ_EVENT_TG_GRABERR_B_INT_DLY 342
+#define CMDQ_EVENT_TG_GRABERR_C_INT 343
+#define CMDQ_EVENT_CQ_VR_SNAP_A_INT_DLY 344
+#define CMDQ_EVENT_CQ_VR_SNAP_B_INT_DLY 345
+#define CMDQ_EVENT_CQ_VR_SNAP_C_INT 346
+#define CMDQ_EVENT_DMA_R1_ERROR_A_INT_DLY 347
+#define CMDQ_EVENT_DMA_R1_ERROR_B_INT_DLY 348
+#define CMDQ_EVENT_DMA_R1_ERROR_C_INT 349
+#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_0 353
+#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_1 354
+#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_2 355
+#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_3 356
+#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_0 385
+#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_1 386
+#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_2 387
+#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_3 388
+#define CMDQ_EVENT_VDEC_EVENT_0 416
+#define CMDQ_EVENT_VDEC_EVENT_1 417
+#define CMDQ_EVENT_VDEC_EVENT_2 418
+#define CMDQ_EVENT_VDEC_EVENT_3 419
+#define CMDQ_EVENT_VDEC_EVENT_4 420
+#define CMDQ_EVENT_VDEC_EVENT_5 421
+#define CMDQ_EVENT_VDEC_EVENT_6 422
+#define CMDQ_EVENT_VDEC_EVENT_7 423
+#define CMDQ_EVENT_VDEC_EVENT_8 424
+#define CMDQ_EVENT_VDEC_EVENT_9 425
+#define CMDQ_EVENT_VDEC_EVENT_10 426
+#define CMDQ_EVENT_VDEC_EVENT_11 427
+#define CMDQ_EVENT_VDEC_EVENT_12 428
+#define CMDQ_EVENT_VDEC_EVENT_13 429
+#define CMDQ_EVENT_VDEC_EVENT_14 430
+#define CMDQ_EVENT_VDEC_EVENT_15 431
+#define CMDQ_EVENT_FDVT_DONE 449
+#define CMDQ_EVENT_FE_DONE 450
+#define CMDQ_EVENT_RSC_EOF 451
+#define CMDQ_EVENT_DVS_DONE_ASYNC_SHOT 452
+#define CMDQ_EVENT_DVP_DONE_ASYNC_SHOT 453
+#define CMDQ_EVENT_DSI0_TE_INFRA 898
+
+#endif
--
2.18.0

2020-02-28 13:46:29

by Dennis-YC Hsieh

Subject: [PATCH v3 02/13] mailbox: cmdq: variablize address shift in platform

Some gce hardware shift pc and end address in register to support
large dram addressing.
Implement gce address shift when write or read pc and end register.
And add shift bit in platform definition.

Signed-off-by: Dennis YC Hsieh <[email protected]>
---
drivers/mailbox/mtk-cmdq-mailbox.c | 57 ++++++++++++++++++------
drivers/soc/mediatek/mtk-cmdq-helper.c | 3 +-
include/linux/mailbox/mtk-cmdq-mailbox.h | 2 +
3 files changed, 48 insertions(+), 14 deletions(-)

diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index 9a6ce9f5a7db..a98f0357dd7d 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -76,8 +76,22 @@ struct cmdq {
struct cmdq_thread *thread;
struct clk *clock;
bool suspended;
+ u8 shift_pa;
};

+struct gce_plat {
+ u32 thread_nr;
+ u8 shift;
+};
+
+u8 cmdq_mbox_shift(struct mbox_chan *chan)
+{
+ struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox);
+
+ return cmdq->shift_pa;
+}
+EXPORT_SYMBOL(cmdq_mbox_shift);
+
static int cmdq_thread_suspend(struct cmdq *cmdq, struct cmdq_thread *thread)
{
u32 status;
@@ -183,7 +197,7 @@ static void cmdq_task_remove_wfe(struct cmdq_task *task)
for (i = 0; i < CMDQ_NUM_CMD(task->pkt); i++)
if (cmdq_command_is_wfe(base[i]))
base[i] = (u64)CMDQ_JUMP_BY_OFFSET << 32 |
- CMDQ_JUMP_PASS;
+ CMDQ_JUMP_PASS >> task->cmdq->shift_pa;
dma_sync_single_for_device(dev, task->pa_base, task->pkt->cmd_buf_size,
DMA_TO_DEVICE);
}
@@ -221,13 +235,15 @@ static void cmdq_task_handle_error(struct cmdq_task *task)
{
struct cmdq_thread *thread = task->thread;
struct cmdq_task *next_task;
+ struct cmdq *cmdq = task->cmdq;

dev_err(task->cmdq->mbox.dev, "task 0x%p error\n", task);
WARN_ON(cmdq_thread_suspend(task->cmdq, thread) < 0);
next_task = list_first_entry_or_null(&thread->task_busy_list,
struct cmdq_task, list_entry);
if (next_task)
- writel(next_task->pa_base, thread->base + CMDQ_THR_CURR_ADDR);
+ writel(next_task->pa_base >> cmdq->shift_pa,
+ thread->base + CMDQ_THR_CURR_ADDR);
cmdq_thread_resume(thread);
}

@@ -257,7 +273,7 @@ static void cmdq_thread_irq_handler(struct cmdq *cmdq,
else
return;

- curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR);
+ curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) << cmdq->shift_pa;

list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
list_entry) {
@@ -373,16 +389,20 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
WARN_ON(clk_enable(cmdq->clock) < 0);
WARN_ON(cmdq_thread_reset(cmdq, thread) < 0);

- writel(task->pa_base, thread->base + CMDQ_THR_CURR_ADDR);
- writel(task->pa_base + pkt->cmd_buf_size,
+ writel(task->pa_base >> cmdq->shift_pa,
+ thread->base + CMDQ_THR_CURR_ADDR);
+ writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa,
thread->base + CMDQ_THR_END_ADDR);
+
writel(thread->priority, thread->base + CMDQ_THR_PRIORITY);
writel(CMDQ_THR_IRQ_EN, thread->base + CMDQ_THR_IRQ_ENABLE);
writel(CMDQ_THR_ENABLED, thread->base + CMDQ_THR_ENABLE_TASK);
} else {
WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
- curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR);
- end_pa = readl(thread->base + CMDQ_THR_END_ADDR);
+ curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) <<
+ cmdq->shift_pa;
+ end_pa = readl(thread->base + CMDQ_THR_END_ADDR) <<
+ cmdq->shift_pa;

/*
* Atomic execution should remove the following wfe, i.e. only
@@ -395,7 +415,7 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
cmdq_thread_wait_end(thread, end_pa);
WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
/* set to this task directly */
- writel(task->pa_base,
+ writel(task->pa_base >> cmdq->shift_pa,
thread->base + CMDQ_THR_CURR_ADDR);
} else {
cmdq_task_insert_into_thread(task);
@@ -407,14 +427,14 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
if (curr_pa == end_pa - CMDQ_INST_SIZE ||
curr_pa == end_pa) {
/* set to this task directly */
- writel(task->pa_base,
+ writel(task->pa_base >> cmdq->shift_pa,
thread->base + CMDQ_THR_CURR_ADDR);
} else {
cmdq_task_insert_into_thread(task);
smp_mb(); /* modify jump before enable thread */
}
}
- writel(task->pa_base + pkt->cmd_buf_size,
+ writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa,
thread->base + CMDQ_THR_END_ADDR);
cmdq_thread_resume(thread);
}
@@ -461,6 +481,7 @@ static int cmdq_probe(struct platform_device *pdev)
struct resource *res;
struct cmdq *cmdq;
int err, i;
+ struct gce_plat *plat_data;

cmdq = devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL);
if (!cmdq)
@@ -479,7 +500,14 @@ static int cmdq_probe(struct platform_device *pdev)
return -EINVAL;
}

- cmdq->thread_nr = (u32)(unsigned long)of_device_get_match_data(dev);
+ plat_data = (struct gce_plat *)of_device_get_match_data(dev);
+ if (!plat_data) {
+ dev_err(dev, "failed to get match data\n");
+ return -EINVAL;
+ }
+
+ cmdq->thread_nr = plat_data->thread_nr;
+ cmdq->shift_pa = plat_data->shift;
cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
"mtk_cmdq", cmdq);
@@ -542,9 +570,12 @@ static const struct dev_pm_ops cmdq_pm_ops = {
.resume = cmdq_resume,
};

+static const struct gce_plat gce_plat_v2 = {.thread_nr = 16};
+static const struct gce_plat gce_plat_v3 = {.thread_nr = 24};
+
static const struct of_device_id cmdq_of_ids[] = {
- {.compatible = "mediatek,mt8173-gce", .data = (void *)16},
- {.compatible = "mediatek,mt8183-gce", .data = (void *)24},
+ {.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2},
+ {.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3},
{}
};

diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
index de20e6cba83b..2e1bc513569b 100644
--- a/drivers/soc/mediatek/mtk-cmdq-helper.c
+++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
@@ -291,7 +291,8 @@ static int cmdq_pkt_finalize(struct cmdq_pkt *pkt)

/* JUMP to end */
inst.op = CMDQ_CODE_JUMP;
- inst.value = CMDQ_JUMP_PASS;
+ inst.value = CMDQ_JUMP_PASS >>
+ cmdq_mbox_shift(((struct cmdq_client *)pkt->cl)->chan);
err = cmdq_pkt_append_command(pkt, inst);

return err;
diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h
index a4dc45fbec0a..dfe5b2eb85cc 100644
--- a/include/linux/mailbox/mtk-cmdq-mailbox.h
+++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
@@ -88,4 +88,6 @@ struct cmdq_pkt {
void *cl;
};

+u8 cmdq_mbox_shift(struct mbox_chan *chan);
+
#endif /* __MTK_CMDQ_MAILBOX_H__ */
--
2.18.0

2020-02-28 13:47:07

by Dennis-YC Hsieh

Subject: [PATCH v3 12/13] soc: mediatek: cmdq: add clear option in cmdq_pkt_wfe api

Add clear parameter to let client decide if
event should be clear to 0 after GCE receive it.

Signed-off-by: Dennis YC Hsieh <[email protected]>
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 5 +++--
include/linux/mailbox/mtk-cmdq-mailbox.h | 3 +--
include/linux/soc/mediatek/mtk-cmdq.h | 5 +++--
3 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
index bbc68a7c81e9..406e1d34d234 100644
--- a/drivers/soc/mediatek/mtk-cmdq-helper.c
+++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
@@ -295,15 +295,16 @@ int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
}
EXPORT_SYMBOL(cmdq_pkt_write_s_value);

-int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event)
+int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event, bool clear)
{
struct cmdq_instruction inst = { {0} };
+ u32 clear_option = clear ? CMDQ_WFE_UPDATE : 0;

if (event >= CMDQ_MAX_EVENT)
return -EINVAL;

inst.op = CMDQ_CODE_WFE;
- inst.value = CMDQ_WFE_OPTION;
+ inst.value = CMDQ_WFE_OPTION | clear_option;
inst.event = event;

return cmdq_pkt_append_command(pkt, inst);
diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h
index 3f6bc0dfd5da..42d2a30e6a70 100644
--- a/include/linux/mailbox/mtk-cmdq-mailbox.h
+++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
@@ -27,8 +27,7 @@
* bit 16-27: update value
* bit 31: 1 - update, 0 - no update
*/
-#define CMDQ_WFE_OPTION (CMDQ_WFE_UPDATE | CMDQ_WFE_WAIT | \
- CMDQ_WFE_WAIT_VALUE)
+#define CMDQ_WFE_OPTION (CMDQ_WFE_WAIT | CMDQ_WFE_WAIT_VALUE)

/** cmdq event maximum */
#define CMDQ_MAX_EVENT 0x3ff
diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
index 1a6c56f3bec1..d63749440697 100644
--- a/include/linux/soc/mediatek/mtk-cmdq.h
+++ b/include/linux/soc/mediatek/mtk-cmdq.h
@@ -152,11 +152,12 @@ int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
/**
* cmdq_pkt_wfe() - append wait for event command to the CMDQ packet
* @pkt: the CMDQ packet
- * @event: the desired event type to "wait and CLEAR"
+ * @event: the desired event type to wait
+ * @clear: clear event or not after event arrive
*
* Return: 0 for success; else the error code is returned
*/
-int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event);
+int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event, bool clear);

/**
* cmdq_pkt_clear_event() - append clear event command to the CMDQ packet
--
2.18.0

2020-02-28 13:47:17

by Dennis-YC Hsieh

Subject: [PATCH v3 09/13] soc: mediatek: cmdq: add write_s value function

add write_s function in cmdq helper functions which
writes a constant value to address with large dma
access support.

Signed-off-by: Dennis YC Hsieh <[email protected]>
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 26 ++++++++++++++++++++++++++
include/linux/soc/mediatek/mtk-cmdq.h | 14 ++++++++++++++
2 files changed, 40 insertions(+)

diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
index 428f99288ca6..1336523eb7d4 100644
--- a/drivers/soc/mediatek/mtk-cmdq-helper.c
+++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
@@ -269,6 +269,32 @@ int cmdq_pkt_write_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
}
EXPORT_SYMBOL(cmdq_pkt_write_s);

+int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
+ u16 addr_low, u32 value, u32 mask)
+{
+ struct cmdq_instruction inst = { {0} };
+ int err;
+
+ if (mask != U32_MAX) {
+ inst.op = CMDQ_CODE_MASK;
+ inst.mask = ~mask;
+ err = cmdq_pkt_append_command(pkt, inst);
+ if (err < 0)
+ return err;
+
+ inst.op = CMDQ_CODE_WRITE_S_MASK;
+ } else {
+ inst.op = CMDQ_CODE_WRITE_S;
+ }
+
+ inst.sop = high_addr_reg_idx;
+ inst.offset = addr_low;
+ inst.value = value;
+
+ return cmdq_pkt_append_command(pkt, inst);
+}
+EXPORT_SYMBOL(cmdq_pkt_write_s_value);
+
int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event)
{
struct cmdq_instruction inst = { {0} };
diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
index 01b4184af310..fec292aac83c 100644
--- a/include/linux/soc/mediatek/mtk-cmdq.h
+++ b/include/linux/soc/mediatek/mtk-cmdq.h
@@ -135,6 +135,20 @@ int cmdq_pkt_read_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx, u16 addr_low,
int cmdq_pkt_write_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
u16 addr_low, u16 src_reg_idx, u32 mask);

+/**
+ * cmdq_pkt_write_s_value() - append write_s command with mask to the CMDQ
+ * packet which write value to a physical address
+ * @pkt: the CMDQ packet
+ * @high_addr_reg_idx: internal regisger ID which contains high address of pa
+ * @addr_low: low address of pa
+ * @value: the specified target value
+ * @mask: the specified target mask
+ *
+ * Return: 0 for success; else the error code is returned
+ */
+int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
+ u16 addr_low, u32 value, u32 mask);
+
/**
* cmdq_pkt_wfe() - append wait for event command to the CMDQ packet
* @pkt: the CMDQ packet
--
2.18.0

2020-02-28 13:47:35

by Dennis-YC Hsieh

Subject: [PATCH v3 11/13] soc: mediatek: cmdq: add jump function

Add jump function so that client can jump to any address which
contains instruction.

Signed-off-by: Dennis YC Hsieh <[email protected]>
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 12 ++++++++++++
include/linux/soc/mediatek/mtk-cmdq.h | 11 +++++++++++
2 files changed, 23 insertions(+)

diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
index 58fec634dcf1..bbc68a7c81e9 100644
--- a/drivers/soc/mediatek/mtk-cmdq-helper.c
+++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
@@ -372,6 +372,18 @@ int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value)
}
EXPORT_SYMBOL(cmdq_pkt_assign);

+int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr)
+{
+ struct cmdq_client *cl = pkt->cl;
+ struct cmdq_instruction inst = { {0} };
+
+ inst.op = CMDQ_CODE_JUMP;
+ inst.offset = 1;
+ inst.value = addr >> cmdq_mbox_shift(cl->chan);
+ return cmdq_pkt_append_command(pkt, inst);
+}
+EXPORT_SYMBOL(cmdq_pkt_jump);
+
int cmdq_pkt_finalize(struct cmdq_pkt *pkt)
{
struct cmdq_instruction inst = { {0} };
diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
index 99e77155f967..1a6c56f3bec1 100644
--- a/include/linux/soc/mediatek/mtk-cmdq.h
+++ b/include/linux/soc/mediatek/mtk-cmdq.h
@@ -213,6 +213,17 @@ int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys,
*/
int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value);

+/**
+ * cmdq_pkt_jump() - Append jump command to the CMDQ packet, ask GCE
+ * to execute an instruction that change current thread PC to
+ * a physical address which should contains more instruction.
+ * @pkt: the CMDQ packet
+ * @addr: physical address of target instruction buffer
+ *
+ * Return: 0 for success; else the error code is returned
+ */
+int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr);
+
/**
* cmdq_pkt_finalize() - Append EOC and jump command to pkt.
* @pkt: the CMDQ packet
--
2.18.0

2020-02-28 13:47:35

by Dennis-YC Hsieh

Subject: [PATCH v3 07/13] soc: mediatek: cmdq: add write_s function

add write_s function in cmdq helper functions which
writes value contains in internal register to address
with large dma access support.

Signed-off-by: Dennis YC Hsieh <[email protected]>
---
drivers/soc/mediatek/mtk-cmdq-helper.c | 34 +++++++++++++++++++++++-
include/linux/mailbox/mtk-cmdq-mailbox.h | 2 ++
include/linux/soc/mediatek/mtk-cmdq.h | 20 ++++++++++++++
3 files changed, 55 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
index 8342a5c94bc7..68b42c935fe6 100644
--- a/drivers/soc/mediatek/mtk-cmdq-helper.c
+++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
@@ -18,6 +18,10 @@ struct cmdq_instruction {
union {
u32 value;
u32 mask;
+ struct {
+ u16 arg_c;
+ u16 src_reg;
+ };
};
union {
u16 offset;
@@ -29,7 +33,7 @@ struct cmdq_instruction {
struct {
u8 sop:5;
u8 arg_c_t:1;
- u8 arg_b_t:1;
+ u8 src_t:1;
u8 dst_t:1;
};
};
@@ -222,6 +226,34 @@ int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,
}
EXPORT_SYMBOL(cmdq_pkt_write_mask);

+int cmdq_pkt_write_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
+ u16 addr_low, u16 src_reg_idx, u32 mask)
+{
+ struct cmdq_instruction inst = { {0} };
+ int err;
+
+ if (mask != U32_MAX) {
+ inst.op = CMDQ_CODE_MASK;
+ inst.mask = ~mask;
+ err = cmdq_pkt_append_command(pkt, inst);
+ if (err < 0)
+ return err;
+
+ inst.mask = 0;
+ inst.op = CMDQ_CODE_WRITE_S_MASK;
+ } else {
+ inst.op = CMDQ_CODE_WRITE_S;
+ }
+
+ inst.src_t = CMDQ_REG_TYPE;
+ inst.sop = high_addr_reg_idx;
+ inst.offset = addr_low;
+ inst.src_reg = src_reg_idx;
+
+ return cmdq_pkt_append_command(pkt, inst);
+}
+EXPORT_SYMBOL(cmdq_pkt_write_s);
+
int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event)
{
struct cmdq_instruction inst = { {0} };
diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h
index 121c3bb6d3de..8ef87e1bd03b 100644
--- a/include/linux/mailbox/mtk-cmdq-mailbox.h
+++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
@@ -59,6 +59,8 @@ enum cmdq_code {
CMDQ_CODE_JUMP = 0x10,
CMDQ_CODE_WFE = 0x20,
CMDQ_CODE_EOC = 0x40,
+ CMDQ_CODE_WRITE_S = 0x90,
+ CMDQ_CODE_WRITE_S_MASK = 0x91,
CMDQ_CODE_LOGIC = 0xa0,
};

diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
index 83340211e1d3..c72d826d8934 100644
--- a/include/linux/soc/mediatek/mtk-cmdq.h
+++ b/include/linux/soc/mediatek/mtk-cmdq.h
@@ -12,6 +12,8 @@
#include <linux/timer.h>

#define CMDQ_NO_TIMEOUT 0xffffffffu
+#define CMDQ_ADDR_HIGH(addr) ((u32)(((addr) >> 16) & GENMASK(31, 0)))
+#define CMDQ_ADDR_LOW(addr) ((u16)(addr) | BIT(1))

struct cmdq_pkt;

@@ -102,6 +104,24 @@ int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value);
int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,
u16 offset, u32 value, u32 mask);

+/**
+ * cmdq_pkt_write_s() - append write_s command to the CMDQ packet
+ * @pkt: the CMDQ packet
+ * @high_addr_reg_idx: internal regisger ID which contains high address of pa
+ * @addr_low: low address of pa
+ * @src_reg_idx: the CMDQ internal register ID which cache source value
+ * @mask: the specified target address mask, use U32_MAX if no need
+ *
+ * Return: 0 for success; else the error code is returned
+ *
+ * Support write value to physical address without subsys. Use CMDQ_ADDR_HIGH()
+ * to get high addrees and call cmdq_pkt_assign() to assign value into internal
+ * reg. Also use CMDQ_ADDR_LOW() to get low address for addr_low parameterwhen
+ * call to this function.
+ */
+int cmdq_pkt_write_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
+ u16 addr_low, u16 src_reg_idx, u32 mask);
+
/**
* cmdq_pkt_wfe() - append wait for event command to the CMDQ packet
* @pkt: the CMDQ packet
--
2.18.0

2020-02-28 14:33:55

by CK Hu (胡俊光)

Subject: Re: [PATCH v3 12/13] soc: mediatek: cmdq: add clear option in cmdq_pkt_wfe api

Hi, Dennis:

On Fri, 2020-02-28 at 21:44 +0800, Dennis YC Hsieh wrote:
> Add clear parameter to let client decide if
> event should be clear to 0 after GCE receive it.
>
> Signed-off-by: Dennis YC Hsieh <[email protected]>
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 5 +++--
> include/linux/mailbox/mtk-cmdq-mailbox.h | 3 +--
> include/linux/soc/mediatek/mtk-cmdq.h | 5 +++--
> 3 files changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index bbc68a7c81e9..406e1d34d234 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -295,15 +295,16 @@ int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
> }
> EXPORT_SYMBOL(cmdq_pkt_write_s_value);
>
> -int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event)
> +int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event, bool clear)
> {
> struct cmdq_instruction inst = { {0} };
> + u32 clear_option = clear ? CMDQ_WFE_UPDATE : 0;
>
> if (event >= CMDQ_MAX_EVENT)
> return -EINVAL;
>
> inst.op = CMDQ_CODE_WFE;
> - inst.value = CMDQ_WFE_OPTION;
> + inst.value = CMDQ_WFE_OPTION | clear_option;
> inst.event = event;
>
> return cmdq_pkt_append_command(pkt, inst);
> diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h
> index 3f6bc0dfd5da..42d2a30e6a70 100644
> --- a/include/linux/mailbox/mtk-cmdq-mailbox.h
> +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
> @@ -27,8 +27,7 @@
> * bit 16-27: update value
> * bit 31: 1 - update, 0 - no update
> */
> -#define CMDQ_WFE_OPTION (CMDQ_WFE_UPDATE | CMDQ_WFE_WAIT | \
> - CMDQ_WFE_WAIT_VALUE)
> +#define CMDQ_WFE_OPTION (CMDQ_WFE_WAIT | CMDQ_WFE_WAIT_VALUE)
>
> /** cmdq event maximum */
> #define CMDQ_MAX_EVENT 0x3ff
> diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
> index 1a6c56f3bec1..d63749440697 100644
> --- a/include/linux/soc/mediatek/mtk-cmdq.h
> +++ b/include/linux/soc/mediatek/mtk-cmdq.h
> @@ -152,11 +152,12 @@ int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
> /**
> * cmdq_pkt_wfe() - append wait for event command to the CMDQ packet
> * @pkt: the CMDQ packet
> - * @event: the desired event type to "wait and CLEAR"
> + * @event: the desired event type to wait
> + * @clear: clear event or not after event arrive
> *
> * Return: 0 for success; else the error code is returned
> */
> -int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event);
> +int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event, bool clear);

I think you should modify client driver [1] as well in this patch.
Change it to

cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false);

[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/mediatek/mtk_drm_crtc.c?h=v5.6-rc3#n491

Regards,
CK

>
> /**
> * cmdq_pkt_clear_event() - append clear event command to the CMDQ packet

2020-02-28 14:45:44

by CK Hu (胡俊光)

Subject: Re: [PATCH v3 06/13] soc: mediatek: cmdq: add assign function

Hi, Dennis:

On Fri, 2020-02-28 at 21:44 +0800, Dennis YC Hsieh wrote:
> Add assign function in cmdq helper which assign constant value into
> internal register by index.
>

Reviewed-by: CK Hu <[email protected]>

> Signed-off-by: Dennis YC Hsieh <[email protected]>
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 24 +++++++++++++++++++++++-
> include/linux/mailbox/mtk-cmdq-mailbox.h | 1 +
> include/linux/soc/mediatek/mtk-cmdq.h | 14 ++++++++++++++
> 3 files changed, 38 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index 0698612de5ad..8342a5c94bc7 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -12,6 +12,7 @@
> #define CMDQ_WRITE_ENABLE_MASK BIT(0)
> #define CMDQ_POLL_ENABLE_MASK BIT(0)
> #define CMDQ_EOC_IRQ_EN BIT(0)
> +#define CMDQ_REG_TYPE 1
>
> struct cmdq_instruction {
> union {
> @@ -21,8 +22,17 @@ struct cmdq_instruction {
> union {
> u16 offset;
> u16 event;
> + u16 reg_dst;
> + };
> + union {
> + u8 subsys;
> + struct {
> + u8 sop:5;
> + u8 arg_c_t:1;
> + u8 arg_b_t:1;
> + u8 dst_t:1;
> + };
> };
> - u8 subsys;
> u8 op;
> };
>
> @@ -277,6 +287,18 @@ int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys,
> }
> EXPORT_SYMBOL(cmdq_pkt_poll_mask);
>
> +int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value)
> +{
> + struct cmdq_instruction inst = { {0} };
> +
> + inst.op = CMDQ_CODE_LOGIC;
> + inst.dst_t = CMDQ_REG_TYPE;
> + inst.reg_dst = reg_idx;
> + inst.value = value;
> + return cmdq_pkt_append_command(pkt, inst);
> +}
> +EXPORT_SYMBOL(cmdq_pkt_assign);
> +
> static int cmdq_pkt_finalize(struct cmdq_pkt *pkt)
> {
> struct cmdq_instruction inst = { {0} };
> diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h
> index dfe5b2eb85cc..121c3bb6d3de 100644
> --- a/include/linux/mailbox/mtk-cmdq-mailbox.h
> +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
> @@ -59,6 +59,7 @@ enum cmdq_code {
> CMDQ_CODE_JUMP = 0x10,
> CMDQ_CODE_WFE = 0x20,
> CMDQ_CODE_EOC = 0x40,
> + CMDQ_CODE_LOGIC = 0xa0,
> };
>
> enum cmdq_cb_status {
> diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
> index a74c1d5acdf3..83340211e1d3 100644
> --- a/include/linux/soc/mediatek/mtk-cmdq.h
> +++ b/include/linux/soc/mediatek/mtk-cmdq.h
> @@ -152,6 +152,20 @@ int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys,
> */
> int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys,
> u16 offset, u32 value, u32 mask);
> +
> +/**
> + * cmdq_pkt_assign() - Append logic assign command to the CMDQ packet, ask GCE
> + * to execute an instruction that set a constant value into
> + * internal register and use as value, mask or address in
> + * read/write instruction.
> + * @pkt: the CMDQ packet
> + * @reg_idx: the CMDQ internal register ID
> + * @value: the specified value
> + *
> + * Return: 0 for success; else the error code is returned
> + */
> +int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value);
> +
> /**
> * cmdq_pkt_flush_async() - trigger CMDQ to asynchronously execute the CMDQ
> * packet and call back at the end of done packet

2020-02-28 14:49:25

by CK Hu (胡俊光)

Subject: Re: [PATCH v3 07/13] soc: mediatek: cmdq: add write_s function

Hi, Dennis:

On Fri, 2020-02-28 at 21:44 +0800, Dennis YC Hsieh wrote:
> add write_s function in cmdq helper functions which
> writes value contains in internal register to address
> with large dma access support.
>

Reviewed-by: CK Hu <[email protected]>

> Signed-off-by: Dennis YC Hsieh <[email protected]>
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 34 +++++++++++++++++++++++-
> include/linux/mailbox/mtk-cmdq-mailbox.h | 2 ++
> include/linux/soc/mediatek/mtk-cmdq.h | 20 ++++++++++++++
> 3 files changed, 55 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index 8342a5c94bc7..68b42c935fe6 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -18,6 +18,10 @@ struct cmdq_instruction {
> union {
> u32 value;
> u32 mask;
> + struct {
> + u16 arg_c;
> + u16 src_reg;
> + };
> };
> union {
> u16 offset;
> @@ -29,7 +33,7 @@ struct cmdq_instruction {
> struct {
> u8 sop:5;
> u8 arg_c_t:1;
> - u8 arg_b_t:1;
> + u8 src_t:1;
> u8 dst_t:1;
> };
> };
> @@ -222,6 +226,34 @@ int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,
> }
> EXPORT_SYMBOL(cmdq_pkt_write_mask);
>
> +int cmdq_pkt_write_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
> + u16 addr_low, u16 src_reg_idx, u32 mask)
> +{
> + struct cmdq_instruction inst = { {0} };
> + int err;
> +
> + if (mask != U32_MAX) {
> + inst.op = CMDQ_CODE_MASK;
> + inst.mask = ~mask;
> + err = cmdq_pkt_append_command(pkt, inst);
> + if (err < 0)
> + return err;
> +
> + inst.mask = 0;
> + inst.op = CMDQ_CODE_WRITE_S_MASK;
> + } else {
> + inst.op = CMDQ_CODE_WRITE_S;
> + }
> +
> + inst.src_t = CMDQ_REG_TYPE;
> + inst.sop = high_addr_reg_idx;
> + inst.offset = addr_low;
> + inst.src_reg = src_reg_idx;
> +
> + return cmdq_pkt_append_command(pkt, inst);
> +}
> +EXPORT_SYMBOL(cmdq_pkt_write_s);
> +
> int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event)
> {
> struct cmdq_instruction inst = { {0} };
> diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h
> index 121c3bb6d3de..8ef87e1bd03b 100644
> --- a/include/linux/mailbox/mtk-cmdq-mailbox.h
> +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
> @@ -59,6 +59,8 @@ enum cmdq_code {
> CMDQ_CODE_JUMP = 0x10,
> CMDQ_CODE_WFE = 0x20,
> CMDQ_CODE_EOC = 0x40,
> + CMDQ_CODE_WRITE_S = 0x90,
> + CMDQ_CODE_WRITE_S_MASK = 0x91,
> CMDQ_CODE_LOGIC = 0xa0,
> };
>
> diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
> index 83340211e1d3..c72d826d8934 100644
> --- a/include/linux/soc/mediatek/mtk-cmdq.h
> +++ b/include/linux/soc/mediatek/mtk-cmdq.h
> @@ -12,6 +12,8 @@
> #include <linux/timer.h>
>
> #define CMDQ_NO_TIMEOUT 0xffffffffu
> +#define CMDQ_ADDR_HIGH(addr) ((u32)(((addr) >> 16) & GENMASK(31, 0)))
> +#define CMDQ_ADDR_LOW(addr) ((u16)(addr) | BIT(1))
>
> struct cmdq_pkt;
>
> @@ -102,6 +104,24 @@ int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value);
> int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,
> u16 offset, u32 value, u32 mask);
>
> +/**
> + * cmdq_pkt_write_s() - append write_s command to the CMDQ packet
> + * @pkt: the CMDQ packet
> + * @high_addr_reg_idx: internal regisger ID which contains high address of pa
> + * @addr_low: low address of pa
> + * @src_reg_idx: the CMDQ internal register ID which cache source value
> + * @mask: the specified target address mask, use U32_MAX if no need
> + *
> + * Return: 0 for success; else the error code is returned
> + *
> + * Support write value to physical address without subsys. Use CMDQ_ADDR_HIGH()
> + * to get high addrees and call cmdq_pkt_assign() to assign value into internal
> + * reg. Also use CMDQ_ADDR_LOW() to get low address for addr_low parameterwhen
> + * call to this function.
> + */
> +int cmdq_pkt_write_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
> + u16 addr_low, u16 src_reg_idx, u32 mask);
> +
> /**
> * cmdq_pkt_wfe() - append wait for event command to the CMDQ packet
> * @pkt: the CMDQ packet

2020-02-28 14:51:01

by CK Hu (胡俊光)

Subject: Re: [PATCH v3 08/13] soc: mediatek: cmdq: add read_s function

Hi, Dennis:

On Fri, 2020-02-28 at 21:44 +0800, Dennis YC Hsieh wrote:
> Add read_s function in cmdq helper functions which support read value from
> register or dma physical address into gce internal register.
>

Reviewed-by: CK Hu <[email protected]>

> Signed-off-by: Dennis YC Hsieh <[email protected]>
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 15 +++++++++++++++
> include/linux/mailbox/mtk-cmdq-mailbox.h | 1 +
> include/linux/soc/mediatek/mtk-cmdq.h | 13 +++++++++++++
> 3 files changed, 29 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index 68b42c935fe6..428f99288ca6 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -226,6 +226,21 @@ int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,
> }
> EXPORT_SYMBOL(cmdq_pkt_write_mask);
>
> +int cmdq_pkt_read_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx, u16 addr_low,
> + u16 reg_idx)
> +{
> + struct cmdq_instruction inst = { {0} };
> +
> + inst.op = CMDQ_CODE_READ_S;
> + inst.dst_t = CMDQ_REG_TYPE;
> + inst.sop = high_addr_reg_idx;
> + inst.reg_dst = reg_idx;
> + inst.src_reg = addr_low;
> +
> + return cmdq_pkt_append_command(pkt, inst);
> +}
> +EXPORT_SYMBOL(cmdq_pkt_read_s);
> +
> int cmdq_pkt_write_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
> u16 addr_low, u16 src_reg_idx, u32 mask)
> {
> diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h
> index 8ef87e1bd03b..3f6bc0dfd5da 100644
> --- a/include/linux/mailbox/mtk-cmdq-mailbox.h
> +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
> @@ -59,6 +59,7 @@ enum cmdq_code {
> CMDQ_CODE_JUMP = 0x10,
> CMDQ_CODE_WFE = 0x20,
> CMDQ_CODE_EOC = 0x40,
> + CMDQ_CODE_READ_S = 0x80,
> CMDQ_CODE_WRITE_S = 0x90,
> CMDQ_CODE_WRITE_S_MASK = 0x91,
> CMDQ_CODE_LOGIC = 0xa0,
> diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
> index c72d826d8934..01b4184af310 100644
> --- a/include/linux/soc/mediatek/mtk-cmdq.h
> +++ b/include/linux/soc/mediatek/mtk-cmdq.h
> @@ -104,6 +104,19 @@ int cmdq_pkt_write(struct cmdq_pkt *pkt, u8 subsys, u16 offset, u32 value);
> int cmdq_pkt_write_mask(struct cmdq_pkt *pkt, u8 subsys,
> u16 offset, u32 value, u32 mask);
>
> +/*
> + * cmdq_pkt_read_s() - append read_s command to the CMDQ packet
> + * @pkt: the CMDQ packet
> + * @high_addr_reg_idx: internal regisger ID which contains high address of pa
> + * @addr_low: low address of pa
> + * @addr: the physical address of register or dma to read
> + * @reg_idx: the CMDQ internal register ID to cache read data
> + *
> + * Return: 0 for success; else the error code is returned
> + */
> +int cmdq_pkt_read_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx, u16 addr_low,
> + u16 reg_idx);
> +
> /**
> * cmdq_pkt_write_s() - append write_s command to the CMDQ packet
> * @pkt: the CMDQ packet

2020-02-28 14:57:04

by CK Hu (胡俊光)

Subject: Re: [PATCH v3 09/13] soc: mediatek: cmdq: add write_s value function

Hi, Dennis:

On Fri, 2020-02-28 at 21:44 +0800, Dennis YC Hsieh wrote:
> add write_s function in cmdq helper functions which
> writes a constant value to address with large dma
> access support.
>

Reviewed-by: CK Hu <[email protected]>

> Signed-off-by: Dennis YC Hsieh <[email protected]>
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 26 ++++++++++++++++++++++++++
> include/linux/soc/mediatek/mtk-cmdq.h | 14 ++++++++++++++
> 2 files changed, 40 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index 428f99288ca6..1336523eb7d4 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -269,6 +269,32 @@ int cmdq_pkt_write_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
> }
> EXPORT_SYMBOL(cmdq_pkt_write_s);
>
> +int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
> + u16 addr_low, u32 value, u32 mask)
> +{
> + struct cmdq_instruction inst = { {0} };
> + int err;
> +
> + if (mask != U32_MAX) {
> + inst.op = CMDQ_CODE_MASK;
> + inst.mask = ~mask;
> + err = cmdq_pkt_append_command(pkt, inst);
> + if (err < 0)
> + return err;
> +
> + inst.op = CMDQ_CODE_WRITE_S_MASK;
> + } else {
> + inst.op = CMDQ_CODE_WRITE_S;
> + }
> +
> + inst.sop = high_addr_reg_idx;
> + inst.offset = addr_low;
> + inst.value = value;
> +
> + return cmdq_pkt_append_command(pkt, inst);
> +}
> +EXPORT_SYMBOL(cmdq_pkt_write_s_value);
> +
> int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event)
> {
> struct cmdq_instruction inst = { {0} };
> diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
> index 01b4184af310..fec292aac83c 100644
> --- a/include/linux/soc/mediatek/mtk-cmdq.h
> +++ b/include/linux/soc/mediatek/mtk-cmdq.h
> @@ -135,6 +135,20 @@ int cmdq_pkt_read_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx, u16 addr_low,
> int cmdq_pkt_write_s(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
> u16 addr_low, u16 src_reg_idx, u32 mask);
>
> +/**
> + * cmdq_pkt_write_s_value() - append write_s command with mask to the CMDQ
> + * packet which write value to a physical address
> + * @pkt: the CMDQ packet
> + * @high_addr_reg_idx: internal regisger ID which contains high address of pa
> + * @addr_low: low address of pa
> + * @value: the specified target value
> + * @mask: the specified target mask
> + *
> + * Return: 0 for success; else the error code is returned
> + */
> +int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
> + u16 addr_low, u32 value, u32 mask);
> +
> /**
> * cmdq_pkt_wfe() - append wait for event command to the CMDQ packet
> * @pkt: the CMDQ packet

2020-02-28 15:00:14

by CK Hu (胡俊光)

Subject: Re: [PATCH v3 11/13] soc: mediatek: cmdq: add jump function

Hi, Dennis:

On Fri, 2020-02-28 at 21:44 +0800, Dennis YC Hsieh wrote:
> Add jump function so that client can jump to any address which
> contains instruction.
>
> Signed-off-by: Dennis YC Hsieh <[email protected]>
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 12 ++++++++++++
> include/linux/soc/mediatek/mtk-cmdq.h | 11 +++++++++++
> 2 files changed, 23 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index 58fec634dcf1..bbc68a7c81e9 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -372,6 +372,18 @@ int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value)
> }
> EXPORT_SYMBOL(cmdq_pkt_assign);
>
> +int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr)
> +{
> + struct cmdq_client *cl = pkt->cl;
> + struct cmdq_instruction inst = { {0} };
> +
> + inst.op = CMDQ_CODE_JUMP;
> + inst.offset = 1;

Symbolize the value '1'.

> + inst.value = addr >> cmdq_mbox_shift(cl->chan);

If you write as 'cmdq_mbox_shift(pkt->cl->chan)', you could drop local
variable 'cl'.

Regards,
CK

> + return cmdq_pkt_append_command(pkt, inst);
> +}
> +EXPORT_SYMBOL(cmdq_pkt_jump);
> +
> int cmdq_pkt_finalize(struct cmdq_pkt *pkt)
> {
> struct cmdq_instruction inst = { {0} };
> diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
> index 99e77155f967..1a6c56f3bec1 100644
> --- a/include/linux/soc/mediatek/mtk-cmdq.h
> +++ b/include/linux/soc/mediatek/mtk-cmdq.h
> @@ -213,6 +213,17 @@ int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys,
> */
> int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value);
>
> +/**
> + * cmdq_pkt_jump() - Append jump command to the CMDQ packet, ask GCE
> + * to execute an instruction that change current thread PC to
> + * a physical address which should contains more instruction.
> + * @pkt: the CMDQ packet
> + * @addr: physical address of target instruction buffer
> + *
> + * Return: 0 for success; else the error code is returned
> + */
> +int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr);
> +
> /**
> * cmdq_pkt_finalize() - Append EOC and jump command to pkt.
> * @pkt: the CMDQ packet

2020-02-28 15:07:48

by CK Hu (胡俊光)

Subject: Re: [PATCH v3 13/13] soc: mediatek: cmdq: add set event function

Hi, Dennis:

On Fri, 2020-02-28 at 21:44 +0800, Dennis YC Hsieh wrote:
> Add set event function in cmdq helper functions to set specific event.
>

Reviewed-by: CK Hu <[email protected]>

> Signed-off-by: Dennis YC Hsieh <[email protected]>
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 15 +++++++++++++++
> include/linux/mailbox/mtk-cmdq-mailbox.h | 1 +
> include/linux/soc/mediatek/mtk-cmdq.h | 9 +++++++++
> 3 files changed, 25 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index 406e1d34d234..738f83d90b59 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -326,6 +326,21 @@ int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event)
> }
> EXPORT_SYMBOL(cmdq_pkt_clear_event);
>
> +int cmdq_pkt_set_event(struct cmdq_pkt *pkt, u16 event)
> +{
> + struct cmdq_instruction inst = { {0} };
> +
> + if (event >= CMDQ_MAX_EVENT)
> + return -EINVAL;
> +
> + inst.op = CMDQ_CODE_WFE;
> + inst.value = CMDQ_WFE_UPDATE | CMDQ_WFE_UPDATE_VALUE;
> + inst.event = event;
> +
> + return cmdq_pkt_append_command(pkt, inst);
> +}
> +EXPORT_SYMBOL(cmdq_pkt_set_event);
> +
> int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys,
> u16 offset, u32 value)
> {
> diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h
> index 42d2a30e6a70..ba2d811183a9 100644
> --- a/include/linux/mailbox/mtk-cmdq-mailbox.h
> +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
> @@ -17,6 +17,7 @@
> #define CMDQ_JUMP_PASS CMDQ_INST_SIZE
>
> #define CMDQ_WFE_UPDATE BIT(31)
> +#define CMDQ_WFE_UPDATE_VALUE BIT(16)
> #define CMDQ_WFE_WAIT BIT(15)
> #define CMDQ_WFE_WAIT_VALUE 0x1
>
> diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
> index d63749440697..ca70296ae120 100644
> --- a/include/linux/soc/mediatek/mtk-cmdq.h
> +++ b/include/linux/soc/mediatek/mtk-cmdq.h
> @@ -168,6 +168,15 @@ int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event, bool clear);
> */
> int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event);
>
> +/**
> + * cmdq_pkt_set_event() - append set event command to the CMDQ packet
> + * @pkt: the CMDQ packet
> + * @event: the desired event to be set
> + *
> + * Return: 0 for success; else the error code is returned
> + */
> +int cmdq_pkt_set_event(struct cmdq_pkt *pkt, u16 event);
> +
> /**
> * cmdq_pkt_poll() - Append polling command to the CMDQ packet, ask GCE to
> * execute an instruction that wait for a specified

2020-02-28 15:23:37

by CK Hu (胡俊光)

Subject: Re: [PATCH v3 02/13] mailbox: cmdq: variablize address shift in platform

Hi, Dennis:

On Fri, 2020-02-28 at 21:44 +0800, Dennis YC Hsieh wrote:
> Some gce hardware shift pc and end address in register to support
> large dram addressing.
> Implement gce address shift when write or read pc and end register.
> And add shift bit in platform definition.
>
> Signed-off-by: Dennis YC Hsieh <[email protected]>
> ---
> drivers/mailbox/mtk-cmdq-mailbox.c | 57 ++++++++++++++++++------
> drivers/soc/mediatek/mtk-cmdq-helper.c | 3 +-
> include/linux/mailbox/mtk-cmdq-mailbox.h | 2 +
> 3 files changed, 48 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
> index 9a6ce9f5a7db..a98f0357dd7d 100644
> --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> @@ -76,8 +76,22 @@ struct cmdq {
> struct cmdq_thread *thread;
> struct clk *clock;
> bool suspended;
> + u8 shift_pa;
> };
>
> +struct gce_plat {
> + u32 thread_nr;
> + u8 shift;
> +};
> +
> +u8 cmdq_mbox_shift(struct mbox_chan *chan)
> +{
> + struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox);
> +
> + return cmdq->shift_pa;
> +}
> +EXPORT_SYMBOL(cmdq_mbox_shift);
> +
> static int cmdq_thread_suspend(struct cmdq *cmdq, struct cmdq_thread *thread)
> {
> u32 status;
> @@ -183,7 +197,7 @@ static void cmdq_task_remove_wfe(struct cmdq_task *task)
> for (i = 0; i < CMDQ_NUM_CMD(task->pkt); i++)
> if (cmdq_command_is_wfe(base[i]))
> base[i] = (u64)CMDQ_JUMP_BY_OFFSET << 32 |
> - CMDQ_JUMP_PASS;
> + CMDQ_JUMP_PASS >> task->cmdq->shift_pa;
> dma_sync_single_for_device(dev, task->pa_base, task->pkt->cmd_buf_size,
> DMA_TO_DEVICE);
> }
> @@ -221,13 +235,15 @@ static void cmdq_task_handle_error(struct cmdq_task *task)
> {
> struct cmdq_thread *thread = task->thread;
> struct cmdq_task *next_task;
> + struct cmdq *cmdq = task->cmdq;
>
> dev_err(task->cmdq->mbox.dev, "task 0x%p error\n", task);
> WARN_ON(cmdq_thread_suspend(task->cmdq, thread) < 0);

If you invent local variable 'cmdq', I think you could replace all
task->cmdq with cmdq in this function.

> next_task = list_first_entry_or_null(&thread->task_busy_list,
> struct cmdq_task, list_entry);
> if (next_task)
> - writel(next_task->pa_base, thread->base + CMDQ_THR_CURR_ADDR);
> + writel(next_task->pa_base >> cmdq->shift_pa,
> + thread->base + CMDQ_THR_CURR_ADDR);
> cmdq_thread_resume(thread);
> }
>
> @@ -257,7 +273,7 @@ static void cmdq_thread_irq_handler(struct cmdq *cmdq,
> else
> return;
>
> - curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR);
> + curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) << cmdq->shift_pa;
>
> list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
> list_entry) {
> @@ -373,16 +389,20 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
> WARN_ON(clk_enable(cmdq->clock) < 0);
> WARN_ON(cmdq_thread_reset(cmdq, thread) < 0);
>
> - writel(task->pa_base, thread->base + CMDQ_THR_CURR_ADDR);
> - writel(task->pa_base + pkt->cmd_buf_size,
> + writel(task->pa_base >> cmdq->shift_pa,
> + thread->base + CMDQ_THR_CURR_ADDR);
> + writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa,
> thread->base + CMDQ_THR_END_ADDR);
> +
> writel(thread->priority, thread->base + CMDQ_THR_PRIORITY);
> writel(CMDQ_THR_IRQ_EN, thread->base + CMDQ_THR_IRQ_ENABLE);
> writel(CMDQ_THR_ENABLED, thread->base + CMDQ_THR_ENABLE_TASK);
> } else {
> WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
> - curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR);
> - end_pa = readl(thread->base + CMDQ_THR_END_ADDR);
> + curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) <<
> + cmdq->shift_pa;
> + end_pa = readl(thread->base + CMDQ_THR_END_ADDR) <<
> + cmdq->shift_pa;
>
> /*
> * Atomic execution should remove the following wfe, i.e. only
> @@ -395,7 +415,7 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
> cmdq_thread_wait_end(thread, end_pa);
> WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
> /* set to this task directly */
> - writel(task->pa_base,
> + writel(task->pa_base >> cmdq->shift_pa,
> thread->base + CMDQ_THR_CURR_ADDR);
> } else {
> cmdq_task_insert_into_thread(task);
> @@ -407,14 +427,14 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
> if (curr_pa == end_pa - CMDQ_INST_SIZE ||
> curr_pa == end_pa) {
> /* set to this task directly */
> - writel(task->pa_base,
> + writel(task->pa_base >> cmdq->shift_pa,
> thread->base + CMDQ_THR_CURR_ADDR);
> } else {
> cmdq_task_insert_into_thread(task);
> smp_mb(); /* modify jump before enable thread */
> }
> }
> - writel(task->pa_base + pkt->cmd_buf_size,
> + writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa,
> thread->base + CMDQ_THR_END_ADDR);
> cmdq_thread_resume(thread);
> }
> @@ -461,6 +481,7 @@ static int cmdq_probe(struct platform_device *pdev)
> struct resource *res;
> struct cmdq *cmdq;
> int err, i;
> + struct gce_plat *plat_data;
>
> cmdq = devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL);
> if (!cmdq)
> @@ -479,7 +500,14 @@ static int cmdq_probe(struct platform_device *pdev)
> return -EINVAL;
> }
>
> - cmdq->thread_nr = (u32)(unsigned long)of_device_get_match_data(dev);
> + plat_data = (struct gce_plat *)of_device_get_match_data(dev);
> + if (!plat_data) {
> + dev_err(dev, "failed to get match data\n");
> + return -EINVAL;
> + }
> +
> + cmdq->thread_nr = plat_data->thread_nr;
> + cmdq->shift_pa = plat_data->shift;
> cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
> err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
> "mtk_cmdq", cmdq);
> @@ -542,9 +570,12 @@ static const struct dev_pm_ops cmdq_pm_ops = {
> .resume = cmdq_resume,
> };
>
> +static const struct gce_plat gce_plat_v2 = {.thread_nr = 16};
> +static const struct gce_plat gce_plat_v3 = {.thread_nr = 24};
> +
> static const struct of_device_id cmdq_of_ids[] = {
> - {.compatible = "mediatek,mt8173-gce", .data = (void *)16},
> - {.compatible = "mediatek,mt8183-gce", .data = (void *)24},
> + {.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2},
> + {.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3},
> {}
> };
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index de20e6cba83b..2e1bc513569b 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -291,7 +291,8 @@ static int cmdq_pkt_finalize(struct cmdq_pkt *pkt)
>
> /* JUMP to end */
> inst.op = CMDQ_CODE_JUMP;
> - inst.value = CMDQ_JUMP_PASS;
> + inst.value = CMDQ_JUMP_PASS >>
> + cmdq_mbox_shift(((struct cmdq_client *)pkt->cl)->chan);

Why not just cmdq_mbox_shift(pkt->cl->chan) ?

Regards,
CK

> err = cmdq_pkt_append_command(pkt, inst);
>
> return err;
> diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h
> index a4dc45fbec0a..dfe5b2eb85cc 100644
> --- a/include/linux/mailbox/mtk-cmdq-mailbox.h
> +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
> @@ -88,4 +88,6 @@ struct cmdq_pkt {
> void *cl;
> };
>
> +u8 cmdq_mbox_shift(struct mbox_chan *chan);
> +
> #endif /* __MTK_CMDQ_MAILBOX_H__ */

2020-02-28 15:27:38

by CK Hu (胡俊光)

Subject: Re: [PATCH v3 01/13] dt-binding: gce: add gce header file for mt6779

Hi, Dennis:

On Fri, 2020-02-28 at 21:44 +0800, Dennis YC Hsieh wrote:
> Add documentation for the mt6779 gce.
>
> Add gce header file defined the gce hardware event,
> subsys number and constant for mt6779.
>

Reviewed-by: CK Hu <[email protected]>

> Signed-off-by: Dennis YC Hsieh <[email protected]>
> ---
> .../devicetree/bindings/mailbox/mtk-gce.txt | 8 +-
> include/dt-bindings/gce/mt6779-gce.h | 222 ++++++++++++++++++
> 2 files changed, 227 insertions(+), 3 deletions(-)
> create mode 100644 include/dt-bindings/gce/mt6779-gce.h
>
> diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
> index 7b13787ab13d..82c0a83fed09 100644
> --- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
> +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt
> @@ -9,7 +9,8 @@ CMDQ driver uses mailbox framework for communication. Please refer to
> mailbox.txt for generic information about mailbox device-tree bindings.
>
> Required properties:
> -- compatible: can be "mediatek,mt8173-gce" or "mediatek,mt8183-gce"
> +- compatible: can be "mediatek,mt8173-gce", "mediatek,mt8183-gce" or
> + "mediatek,mt6779-gce".
> - reg: Address range of the GCE unit
> - interrupts: The interrupt signal from the GCE block
> - clock: Clocks according to the common clock binding
> @@ -36,8 +37,9 @@ Optional properties for a client device:
> start_offset: the start offset of register address that GCE can access.
> size: the total size of register address that GCE can access.
>
> -Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'
> -or 'dt-binding/gce/mt8183-gce.h'. Such as sub-system ids, thread priority, event ids.
> +Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h',
> +'dt-binding/gce/mt8183-gce.h' or 'dt-bindings/gce/mt6779-gce.h'. Such as
> +sub-system ids, thread priority, event ids.
>
> Example:
>
> diff --git a/include/dt-bindings/gce/mt6779-gce.h b/include/dt-bindings/gce/mt6779-gce.h
> new file mode 100644
> index 000000000000..06101316ace4
> --- /dev/null
> +++ b/include/dt-bindings/gce/mt6779-gce.h
> @@ -0,0 +1,222 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2019 MediaTek Inc.
> + * Author: Dennis-YC Hsieh <[email protected]>
> + */
> +
> +#ifndef _DT_BINDINGS_GCE_MT6779_H
> +#define _DT_BINDINGS_GCE_MT6779_H
> +
> +#define CMDQ_NO_TIMEOUT 0xffffffff
> +
> +/* GCE HW thread priority */
> +#define CMDQ_THR_PRIO_LOWEST 0
> +#define CMDQ_THR_PRIO_1 1
> +#define CMDQ_THR_PRIO_2 2
> +#define CMDQ_THR_PRIO_3 3
> +#define CMDQ_THR_PRIO_4 4
> +#define CMDQ_THR_PRIO_5 5
> +#define CMDQ_THR_PRIO_6 6
> +#define CMDQ_THR_PRIO_HIGHEST 7
> +
> +/* GCE subsys table */
> +#define SUBSYS_1300XXXX 0
> +#define SUBSYS_1400XXXX 1
> +#define SUBSYS_1401XXXX 2
> +#define SUBSYS_1402XXXX 3
> +#define SUBSYS_1502XXXX 4
> +#define SUBSYS_1880XXXX 5
> +#define SUBSYS_1881XXXX 6
> +#define SUBSYS_1882XXXX 7
> +#define SUBSYS_1883XXXX 8
> +#define SUBSYS_1884XXXX 9
> +#define SUBSYS_1000XXXX 10
> +#define SUBSYS_1001XXXX 11
> +#define SUBSYS_1002XXXX 12
> +#define SUBSYS_1003XXXX 13
> +#define SUBSYS_1004XXXX 14
> +#define SUBSYS_1005XXXX 15
> +#define SUBSYS_1020XXXX 16
> +#define SUBSYS_1028XXXX 17
> +#define SUBSYS_1700XXXX 18
> +#define SUBSYS_1701XXXX 19
> +#define SUBSYS_1702XXXX 20
> +#define SUBSYS_1703XXXX 21
> +#define SUBSYS_1800XXXX 22
> +#define SUBSYS_1801XXXX 23
> +#define SUBSYS_1802XXXX 24
> +#define SUBSYS_1804XXXX 25
> +#define SUBSYS_1805XXXX 26
> +#define SUBSYS_1808XXXX 27
> +#define SUBSYS_180aXXXX 28
> +#define SUBSYS_180bXXXX 29
> +#define CMDQ_SUBSYS_OFF 32
> +
> +/* GCE hardware events */
> +#define CMDQ_EVENT_DISP_RDMA0_SOF 0
> +#define CMDQ_EVENT_DISP_RDMA1_SOF 1
> +#define CMDQ_EVENT_MDP_RDMA0_SOF 2
> +#define CMDQ_EVENT_MDP_RDMA1_SOF 3
> +#define CMDQ_EVENT_MDP_RSZ0_SOF 4
> +#define CMDQ_EVENT_MDP_RSZ1_SOF 5
> +#define CMDQ_EVENT_MDP_TDSHP_SOF 6
> +#define CMDQ_EVENT_MDP_WROT0_SOF 7
> +#define CMDQ_EVENT_MDP_WROT1_SOF 8
> +#define CMDQ_EVENT_DISP_OVL0_SOF 9
> +#define CMDQ_EVENT_DISP_2L_OVL0_SOF 10
> +#define CMDQ_EVENT_DISP_2L_OVL1_SOF 11
> +#define CMDQ_EVENT_DISP_WDMA0_SOF 12
> +#define CMDQ_EVENT_DISP_COLOR0_SOF 13
> +#define CMDQ_EVENT_DISP_CCORR0_SOF 14
> +#define CMDQ_EVENT_DISP_AAL0_SOF 15
> +#define CMDQ_EVENT_DISP_GAMMA0_SOF 16
> +#define CMDQ_EVENT_DISP_DITHER0_SOF 17
> +#define CMDQ_EVENT_DISP_PWM0_SOF 18
> +#define CMDQ_EVENT_DISP_DSI0_SOF 19
> +#define CMDQ_EVENT_DISP_DPI0_SOF 20
> +#define CMDQ_EVENT_DISP_POSTMASK0_SOF 21
> +#define CMDQ_EVENT_DISP_RSZ0_SOF 22
> +#define CMDQ_EVENT_MDP_AAL_SOF 23
> +#define CMDQ_EVENT_MDP_CCORR_SOF 24
> +#define CMDQ_EVENT_DISP_DBI0_SOF 25
> +#define CMDQ_EVENT_ISP_RELAY_SOF 26
> +#define CMDQ_EVENT_IPU_RELAY_SOF 27
> +#define CMDQ_EVENT_DISP_RDMA0_EOF 28
> +#define CMDQ_EVENT_DISP_RDMA1_EOF 29
> +#define CMDQ_EVENT_MDP_RDMA0_EOF 30
> +#define CMDQ_EVENT_MDP_RDMA1_EOF 31
> +#define CMDQ_EVENT_MDP_RSZ0_EOF 32
> +#define CMDQ_EVENT_MDP_RSZ1_EOF 33
> +#define CMDQ_EVENT_MDP_TDSHP_EOF 34
> +#define CMDQ_EVENT_MDP_WROT0_W_EOF 35
> +#define CMDQ_EVENT_MDP_WROT1_W_EOF 36
> +#define CMDQ_EVENT_DISP_OVL0_EOF 37
> +#define CMDQ_EVENT_DISP_2L_OVL0_EOF 38
> +#define CMDQ_EVENT_DISP_2L_OVL1_EOF 39
> +#define CMDQ_EVENT_DISP_WDMA0_EOF 40
> +#define CMDQ_EVENT_DISP_COLOR0_EOF 41
> +#define CMDQ_EVENT_DISP_CCORR0_EOF 42
> +#define CMDQ_EVENT_DISP_AAL0_EOF 43
> +#define CMDQ_EVENT_DISP_GAMMA0_EOF 44
> +#define CMDQ_EVENT_DISP_DITHER0_EOF 45
> +#define CMDQ_EVENT_DISP_DSI0_EOF 46
> +#define CMDQ_EVENT_DISP_DPI0_EOF 47
> +#define CMDQ_EVENT_DISP_RSZ0_EOF 49
> +#define CMDQ_EVENT_MDP_AAL_FRAME_DONE 50
> +#define CMDQ_EVENT_MDP_CCORR_FRAME_DONE 51
> +#define CMDQ_EVENT_DISP_POSTMASK0_FRAME_DONE 52
> +#define CMDQ_EVENT_MUTEX0_STREAM_EOF 130
> +#define CMDQ_EVENT_MUTEX1_STREAM_EOF 131
> +#define CMDQ_EVENT_MUTEX2_STREAM_EOF 132
> +#define CMDQ_EVENT_MUTEX3_STREAM_EOF 133
> +#define CMDQ_EVENT_MUTEX4_STREAM_EOF 134
> +#define CMDQ_EVENT_MUTEX5_STREAM_EOF 135
> +#define CMDQ_EVENT_MUTEX6_STREAM_EOF 136
> +#define CMDQ_EVENT_MUTEX7_STREAM_EOF 137
> +#define CMDQ_EVENT_MUTEX8_STREAM_EOF 138
> +#define CMDQ_EVENT_MUTEX9_STREAM_EOF 139
> +#define CMDQ_EVENT_MUTEX10_STREAM_EOF 140
> +#define CMDQ_EVENT_MUTEX11_STREAM_EOF 141
> +#define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 142
> +#define CMDQ_EVENT_DISP_RDMA1_UNDERRUN 143
> +#define CMDQ_EVENT_DISP_RDMA2_UNDERRUN 144
> +#define CMDQ_EVENT_DISP_RDMA3_UNDERRUN 145
> +#define CMDQ_EVENT_DSI0_TE 146
> +#define CMDQ_EVENT_DSI0_IRQ_EVENT 147
> +#define CMDQ_EVENT_DSI0_DONE_EVENT 148
> +#define CMDQ_EVENT_DISP_POSTMASK0_RST_DONE 150
> +#define CMDQ_EVENT_DISP_WDMA0_RST_DONE 151
> +#define CMDQ_EVENT_MDP_WROT0_RST_DONE 153
> +#define CMDQ_EVENT_MDP_RDMA0_RST_DONE 154
> +#define CMDQ_EVENT_DISP_OVL0_RST_DONE 155
> +#define CMDQ_EVENT_DISP_OVL0_2L_RST_DONE 156
> +#define CMDQ_EVENT_DISP_OVL1_2L_RST_DONE 157
> +#define CMDQ_EVENT_DIP_CQ_THREAD0_EOF 257
> +#define CMDQ_EVENT_DIP_CQ_THREAD1_EOF 258
> +#define CMDQ_EVENT_DIP_CQ_THREAD2_EOF 259
> +#define CMDQ_EVENT_DIP_CQ_THREAD3_EOF 260
> +#define CMDQ_EVENT_DIP_CQ_THREAD4_EOF 261
> +#define CMDQ_EVENT_DIP_CQ_THREAD5_EOF 262
> +#define CMDQ_EVENT_DIP_CQ_THREAD6_EOF 263
> +#define CMDQ_EVENT_DIP_CQ_THREAD7_EOF 264
> +#define CMDQ_EVENT_DIP_CQ_THREAD8_EOF 265
> +#define CMDQ_EVENT_DIP_CQ_THREAD9_EOF 266
> +#define CMDQ_EVENT_DIP_CQ_THREAD10_EOF 267
> +#define CMDQ_EVENT_DIP_CQ_THREAD11_EOF 268
> +#define CMDQ_EVENT_DIP_CQ_THREAD12_EOF 269
> +#define CMDQ_EVENT_DIP_CQ_THREAD13_EOF 270
> +#define CMDQ_EVENT_DIP_CQ_THREAD14_EOF 271
> +#define CMDQ_EVENT_DIP_CQ_THREAD15_EOF 272
> +#define CMDQ_EVENT_DIP_CQ_THREAD16_EOF 273
> +#define CMDQ_EVENT_DIP_CQ_THREAD17_EOF 274
> +#define CMDQ_EVENT_DIP_CQ_THREAD18_EOF 275
> +#define CMDQ_EVENT_DIP_DMA_ERR_EVENT 276
> +#define CMDQ_EVENT_AMD_FRAME_DONE 277
> +#define CMDQ_EVENT_MFB_DONE 278
> +#define CMDQ_EVENT_WPE_A_EOF 279
> +#define CMDQ_EVENT_VENC_EOF 289
> +#define CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE 290
> +#define CMDQ_EVENT_JPEG_ENC_EOF 291
> +#define CMDQ_EVENT_VENC_MB_DONE 292
> +#define CMDQ_EVENT_VENC_128BYTE_CNT_DONE 293
> +#define CMDQ_EVENT_ISP_FRAME_DONE_A 321
> +#define CMDQ_EVENT_ISP_FRAME_DONE_B 322
> +#define CMDQ_EVENT_ISP_FRAME_DONE_C 323
> +#define CMDQ_EVENT_ISP_CAMSV_0_PASS1_DONE 324
> +#define CMDQ_EVENT_ISP_CAMSV_0_2_PASS1_DONE 325
> +#define CMDQ_EVENT_ISP_CAMSV_1_PASS1_DONE 326
> +#define CMDQ_EVENT_ISP_CAMSV_2_PASS1_DONE 327
> +#define CMDQ_EVENT_ISP_CAMSV_3_PASS1_DONE 328
> +#define CMDQ_EVENT_ISP_TSF_DONE 329
> +#define CMDQ_EVENT_SENINF_0_FIFO_FULL 330
> +#define CMDQ_EVENT_SENINF_1_FIFO_FULL 331
> +#define CMDQ_EVENT_SENINF_2_FIFO_FULL 332
> +#define CMDQ_EVENT_SENINF_3_FIFO_FULL 333
> +#define CMDQ_EVENT_SENINF_4_FIFO_FULL 334
> +#define CMDQ_EVENT_SENINF_5_FIFO_FULL 335
> +#define CMDQ_EVENT_SENINF_6_FIFO_FULL 336
> +#define CMDQ_EVENT_SENINF_7_FIFO_FULL 337
> +#define CMDQ_EVENT_TG_OVRUN_A_INT_DLY 338
> +#define CMDQ_EVENT_TG_OVRUN_B_INT_DLY 339
> +#define CMDQ_EVENT_TG_OVRUN_C_INT 340
> +#define CMDQ_EVENT_TG_GRABERR_A_INT_DLY 341
> +#define CMDQ_EVENT_TG_GRABERR_B_INT_DLY 342
> +#define CMDQ_EVENT_TG_GRABERR_C_INT 343
> +#define CMDQ_EVENT_CQ_VR_SNAP_A_INT_DLY 344
> +#define CMDQ_EVENT_CQ_VR_SNAP_B_INT_DLY 345
> +#define CMDQ_EVENT_CQ_VR_SNAP_C_INT 346
> +#define CMDQ_EVENT_DMA_R1_ERROR_A_INT_DLY 347
> +#define CMDQ_EVENT_DMA_R1_ERROR_B_INT_DLY 348
> +#define CMDQ_EVENT_DMA_R1_ERROR_C_INT 349
> +#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_0 353
> +#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_1 354
> +#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_2 355
> +#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_3 356
> +#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_0 385
> +#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_1 386
> +#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_2 387
> +#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_3 388
> +#define CMDQ_EVENT_VDEC_EVENT_0 416
> +#define CMDQ_EVENT_VDEC_EVENT_1 417
> +#define CMDQ_EVENT_VDEC_EVENT_2 418
> +#define CMDQ_EVENT_VDEC_EVENT_3 419
> +#define CMDQ_EVENT_VDEC_EVENT_4 420
> +#define CMDQ_EVENT_VDEC_EVENT_5 421
> +#define CMDQ_EVENT_VDEC_EVENT_6 422
> +#define CMDQ_EVENT_VDEC_EVENT_7 423
> +#define CMDQ_EVENT_VDEC_EVENT_8 424
> +#define CMDQ_EVENT_VDEC_EVENT_9 425
> +#define CMDQ_EVENT_VDEC_EVENT_10 426
> +#define CMDQ_EVENT_VDEC_EVENT_11 427
> +#define CMDQ_EVENT_VDEC_EVENT_12 428
> +#define CMDQ_EVENT_VDEC_EVENT_13 429
> +#define CMDQ_EVENT_VDEC_EVENT_14 430
> +#define CMDQ_EVENT_VDEC_EVENT_15 431
> +#define CMDQ_EVENT_FDVT_DONE 449
> +#define CMDQ_EVENT_FE_DONE 450
> +#define CMDQ_EVENT_RSC_EOF 451
> +#define CMDQ_EVENT_DVS_DONE_ASYNC_SHOT 452
> +#define CMDQ_EVENT_DVP_DONE_ASYNC_SHOT 453
> +#define CMDQ_EVENT_DSI0_TE_INFRA 898
> +
> +#endif

2020-02-28 15:39:56

by CK Hu (胡俊光)

Subject: Re: [PATCH v3 05/13] soc: mediatek: cmdq: return send msg error code

Hi, Dennis:

On Fri, 2020-02-28 at 21:44 +0800, Dennis YC Hsieh wrote:
> Return error code to client if send message fail,
> so that client has chance to error handling.
>
> Fixes: 576f1b4bc802 ("soc: mediatek: Add Mediatek CMDQ helper")
> Signed-off-by: Dennis YC Hsieh <[email protected]>
> ---
> drivers/soc/mediatek/mtk-cmdq-helper.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
> index 2e1bc513569b..0698612de5ad 100644
> --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> @@ -351,11 +351,11 @@ int cmdq_pkt_flush_async(struct cmdq_pkt *pkt, cmdq_async_flush_cb cb,
> spin_unlock_irqrestore(&client->lock, flags);
> }
>
> - mbox_send_message(client->chan, pkt);
> + err = mbox_send_message(client->chan, pkt);
> /* We can send next packet immediately, so just call txdone. */
> mbox_client_txdone(client->chan, 0);

If error happen, why tx is done? I think you should return immediately
when error happen.

Regards,
CK

>
> - return 0;
> + return err;
> }
> EXPORT_SYMBOL(cmdq_pkt_flush_async);
>

2020-02-28 15:57:27

by CK Hu (胡俊光)

Subject: Re: [PATCH v3 04/13] mailbox: mediatek: cmdq: clear task in channel before shutdown

Hi, Dennis:

On Fri, 2020-02-28 at 21:44 +0800, Dennis YC Hsieh wrote:
> Do success callback in channel when shutdown. For those task not finish,
> callback with error code thus client has chance to cleanup or reset.
>
> Signed-off-by: Dennis YC Hsieh <[email protected]>
> ---
> drivers/mailbox/mtk-cmdq-mailbox.c | 38 ++++++++++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
> diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
> index 7246b7e21a2e..50dec015593f 100644
> --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> @@ -387,6 +387,12 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
>
> if (list_empty(&thread->task_busy_list)) {
> WARN_ON(clk_enable(cmdq->clock) < 0);
> + /*
> + * The thread reset will clear thread related register to 0,
> + * including pc, end, priority, irq, suspend and enable. Thus
> + * set CMDQ_THR_ENABLED to CMDQ_THR_ENABLE_TASK will enable
> + * thread and make it running.
> + */
> WARN_ON(cmdq_thread_reset(cmdq, thread) < 0);
>
> writel(task->pa_base >> cmdq->shift_pa,
> @@ -450,6 +456,38 @@ static int cmdq_mbox_startup(struct mbox_chan *chan)
>
> static void cmdq_mbox_shutdown(struct mbox_chan *chan)
> {
> + struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
> + struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
> + struct cmdq_task *task, *tmp;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&thread->chan->lock, flags);
> + if (list_empty(&thread->task_busy_list))
> + goto done;
> +
> + WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
> +
> + /* make sure executed tasks have success callback */
> + cmdq_thread_irq_handler(cmdq, thread);
> + if (list_empty(&thread->task_busy_list))
> + goto done;
> +
> + list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
> + list_entry) {
> + cmdq_task_exec_done(task, -ECONNABORTED);

cmdq_task_exec_done(task, CMDQ_CB_ERROR) ? However, I've like to use the
standard error as you write here.

Regards,
CK

> + kfree(task);
> + }
> +
> + cmdq_thread_disable(cmdq, thread);
> + clk_disable(cmdq->clock);
> +done:
> + /*
> + * The thread->task_busy_list empty means thread already disable. The
> + * cmdq_mbox_send_data() always reset thread which clear disable and
> + * suspend statue when first pkt send to channel, so there is no need
> + * to do any operation here, only unlock and leave.
> + */
> + spin_unlock_irqrestore(&thread->chan->lock, flags);
> }
>
> static const struct mbox_chan_ops cmdq_mbox_chan_ops = {

2020-02-29 13:37:03

by Dennis-YC Hsieh

Subject: Re: [PATCH v3 02/13] mailbox: cmdq: variablize address shift in platform

Hi CK,

Thanks for your comment.

On Fri, 2020-02-28 at 23:22 +0800, CK Hu wrote:
> Hi, Dennis:
>
> On Fri, 2020-02-28 at 21:44 +0800, Dennis YC Hsieh wrote:
> > Some gce hardware shift pc and end address in register to support
> > large dram addressing.
> > Implement gce address shift when write or read pc and end register.
> > And add shift bit in platform definition.
> >
> > Signed-off-by: Dennis YC Hsieh <[email protected]>
> > ---
> > drivers/mailbox/mtk-cmdq-mailbox.c | 57 ++++++++++++++++++------
> > drivers/soc/mediatek/mtk-cmdq-helper.c | 3 +-
> > include/linux/mailbox/mtk-cmdq-mailbox.h | 2 +
> > 3 files changed, 48 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
> > index 9a6ce9f5a7db..a98f0357dd7d 100644
> > --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> > +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> > @@ -76,8 +76,22 @@ struct cmdq {
> > struct cmdq_thread *thread;
> > struct clk *clock;
> > bool suspended;
> > + u8 shift_pa;
> > };
> >
> > +struct gce_plat {
> > + u32 thread_nr;
> > + u8 shift;
> > +};
> > +
> > +u8 cmdq_mbox_shift(struct mbox_chan *chan)
> > +{
> > + struct cmdq *cmdq = container_of(chan->mbox, struct cmdq, mbox);
> > +
> > + return cmdq->shift_pa;
> > +}
> > +EXPORT_SYMBOL(cmdq_mbox_shift);
> > +
> > static int cmdq_thread_suspend(struct cmdq *cmdq, struct cmdq_thread *thread)
> > {
> > u32 status;
> > @@ -183,7 +197,7 @@ static void cmdq_task_remove_wfe(struct cmdq_task *task)
> > for (i = 0; i < CMDQ_NUM_CMD(task->pkt); i++)
> > if (cmdq_command_is_wfe(base[i]))
> > base[i] = (u64)CMDQ_JUMP_BY_OFFSET << 32 |
> > - CMDQ_JUMP_PASS;
> > + CMDQ_JUMP_PASS >> task->cmdq->shift_pa;
> > dma_sync_single_for_device(dev, task->pa_base, task->pkt->cmd_buf_size,
> > DMA_TO_DEVICE);
> > }
> > @@ -221,13 +235,15 @@ static void cmdq_task_handle_error(struct cmdq_task *task)
> > {
> > struct cmdq_thread *thread = task->thread;
> > struct cmdq_task *next_task;
> > + struct cmdq *cmdq = task->cmdq;
> >
> > dev_err(task->cmdq->mbox.dev, "task 0x%p error\n", task);
> > WARN_ON(cmdq_thread_suspend(task->cmdq, thread) < 0);
>
> If you invent local variable 'cmdq', I think you could replace all
> task->cmdq with cmdq in this function.
>

Ok, will do.


> > next_task = list_first_entry_or_null(&thread->task_busy_list,
> > struct cmdq_task, list_entry);
> > if (next_task)
> > - writel(next_task->pa_base, thread->base + CMDQ_THR_CURR_ADDR);
> > + writel(next_task->pa_base >> cmdq->shift_pa,
> > + thread->base + CMDQ_THR_CURR_ADDR);
> > cmdq_thread_resume(thread);
> > }
> >
> > @@ -257,7 +273,7 @@ static void cmdq_thread_irq_handler(struct cmdq *cmdq,
> > else
> > return;
> >
> > - curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR);
> > + curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) << cmdq->shift_pa;
> >
> > list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
> > list_entry) {
> > @@ -373,16 +389,20 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
> > WARN_ON(clk_enable(cmdq->clock) < 0);
> > WARN_ON(cmdq_thread_reset(cmdq, thread) < 0);
> >
> > - writel(task->pa_base, thread->base + CMDQ_THR_CURR_ADDR);
> > - writel(task->pa_base + pkt->cmd_buf_size,
> > + writel(task->pa_base >> cmdq->shift_pa,
> > + thread->base + CMDQ_THR_CURR_ADDR);
> > + writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa,
> > thread->base + CMDQ_THR_END_ADDR);
> > +
> > writel(thread->priority, thread->base + CMDQ_THR_PRIORITY);
> > writel(CMDQ_THR_IRQ_EN, thread->base + CMDQ_THR_IRQ_ENABLE);
> > writel(CMDQ_THR_ENABLED, thread->base + CMDQ_THR_ENABLE_TASK);
> > } else {
> > WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
> > - curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR);
> > - end_pa = readl(thread->base + CMDQ_THR_END_ADDR);
> > + curr_pa = readl(thread->base + CMDQ_THR_CURR_ADDR) <<
> > + cmdq->shift_pa;
> > + end_pa = readl(thread->base + CMDQ_THR_END_ADDR) <<
> > + cmdq->shift_pa;
> >
> > /*
> > * Atomic execution should remove the following wfe, i.e. only
> > @@ -395,7 +415,7 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
> > cmdq_thread_wait_end(thread, end_pa);
> > WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
> > /* set to this task directly */
> > - writel(task->pa_base,
> > + writel(task->pa_base >> cmdq->shift_pa,
> > thread->base + CMDQ_THR_CURR_ADDR);
> > } else {
> > cmdq_task_insert_into_thread(task);
> > @@ -407,14 +427,14 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
> > if (curr_pa == end_pa - CMDQ_INST_SIZE ||
> > curr_pa == end_pa) {
> > /* set to this task directly */
> > - writel(task->pa_base,
> > + writel(task->pa_base >> cmdq->shift_pa,
> > thread->base + CMDQ_THR_CURR_ADDR);
> > } else {
> > cmdq_task_insert_into_thread(task);
> > smp_mb(); /* modify jump before enable thread */
> > }
> > }
> > - writel(task->pa_base + pkt->cmd_buf_size,
> > + writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->shift_pa,
> > thread->base + CMDQ_THR_END_ADDR);
> > cmdq_thread_resume(thread);
> > }
> > @@ -461,6 +481,7 @@ static int cmdq_probe(struct platform_device *pdev)
> > struct resource *res;
> > struct cmdq *cmdq;
> > int err, i;
> > + struct gce_plat *plat_data;
> >
> > cmdq = devm_kzalloc(dev, sizeof(*cmdq), GFP_KERNEL);
> > if (!cmdq)
> > @@ -479,7 +500,14 @@ static int cmdq_probe(struct platform_device *pdev)
> > return -EINVAL;
> > }
> >
> > - cmdq->thread_nr = (u32)(unsigned long)of_device_get_match_data(dev);
> > + plat_data = (struct gce_plat *)of_device_get_match_data(dev);
> > + if (!plat_data) {
> > + dev_err(dev, "failed to get match data\n");
> > + return -EINVAL;
> > + }
> > +
> > + cmdq->thread_nr = plat_data->thread_nr;
> > + cmdq->shift_pa = plat_data->shift;
> > cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0);
> > err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED,
> > "mtk_cmdq", cmdq);
> > @@ -542,9 +570,12 @@ static const struct dev_pm_ops cmdq_pm_ops = {
> > .resume = cmdq_resume,
> > };
> >
> > +static const struct gce_plat gce_plat_v2 = {.thread_nr = 16};
> > +static const struct gce_plat gce_plat_v3 = {.thread_nr = 24};
> > +
> > static const struct of_device_id cmdq_of_ids[] = {
> > - {.compatible = "mediatek,mt8173-gce", .data = (void *)16},
> > - {.compatible = "mediatek,mt8183-gce", .data = (void *)24},
> > + {.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2},
> > + {.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3},
> > {}
> > };
> >
> > diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
> > index de20e6cba83b..2e1bc513569b 100644
> > --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> > +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> > @@ -291,7 +291,8 @@ static int cmdq_pkt_finalize(struct cmdq_pkt *pkt)
> >
> > /* JUMP to end */
> > inst.op = CMDQ_CODE_JUMP;
> > - inst.value = CMDQ_JUMP_PASS;
> > + inst.value = CMDQ_JUMP_PASS >>
> > + cmdq_mbox_shift(((struct cmdq_client *)pkt->cl)->chan);
>
> Why not just cmdq_mbox_shift(pkt->cl->chan) ?

Ok, will do.


Regards,
Dennis


>
> Regards,
> CK
>
> > err = cmdq_pkt_append_command(pkt, inst);
> >
> > return err;
> > diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h
> > index a4dc45fbec0a..dfe5b2eb85cc 100644
> > --- a/include/linux/mailbox/mtk-cmdq-mailbox.h
> > +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
> > @@ -88,4 +88,6 @@ struct cmdq_pkt {
> > void *cl;
> > };
> >
> > +u8 cmdq_mbox_shift(struct mbox_chan *chan);
> > +
> > #endif /* __MTK_CMDQ_MAILBOX_H__ */
>
>

2020-02-29 13:40:54

by Dennis-YC Hsieh

Subject: Re: [PATCH v3 04/13] mailbox: mediatek: cmdq: clear task in channel before shutdown

Hi CK,

Thanks for your comment.

On Fri, 2020-02-28 at 23:57 +0800, CK Hu wrote:
> Hi, Dennis:
>
> On Fri, 2020-02-28 at 21:44 +0800, Dennis YC Hsieh wrote:
> > Do success callback in channel when shutdown. For those task not finish,
> > callback with error code thus client has chance to cleanup or reset.
> >
> > Signed-off-by: Dennis YC Hsieh <[email protected]>
> > ---
> > drivers/mailbox/mtk-cmdq-mailbox.c | 38 ++++++++++++++++++++++++++++++
> > 1 file changed, 38 insertions(+)
> >
> > diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
> > index 7246b7e21a2e..50dec015593f 100644
> > --- a/drivers/mailbox/mtk-cmdq-mailbox.c
> > +++ b/drivers/mailbox/mtk-cmdq-mailbox.c
> > @@ -387,6 +387,12 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
> >
> > if (list_empty(&thread->task_busy_list)) {
> > WARN_ON(clk_enable(cmdq->clock) < 0);
> > + /*
> > + * The thread reset will clear thread related register to 0,
> > + * including pc, end, priority, irq, suspend and enable. Thus
> > + * set CMDQ_THR_ENABLED to CMDQ_THR_ENABLE_TASK will enable
> > + * thread and make it running.
> > + */
> > WARN_ON(cmdq_thread_reset(cmdq, thread) < 0);
> >
> > writel(task->pa_base >> cmdq->shift_pa,
> > @@ -450,6 +456,38 @@ static int cmdq_mbox_startup(struct mbox_chan *chan)
> >
> > static void cmdq_mbox_shutdown(struct mbox_chan *chan)
> > {
> > + struct cmdq_thread *thread = (struct cmdq_thread *)chan->con_priv;
> > + struct cmdq *cmdq = dev_get_drvdata(chan->mbox->dev);
> > + struct cmdq_task *task, *tmp;
> > + unsigned long flags;
> > +
> > + spin_lock_irqsave(&thread->chan->lock, flags);
> > + if (list_empty(&thread->task_busy_list))
> > + goto done;
> > +
> > + WARN_ON(cmdq_thread_suspend(cmdq, thread) < 0);
> > +
> > + /* make sure executed tasks have success callback */
> > + cmdq_thread_irq_handler(cmdq, thread);
> > + if (list_empty(&thread->task_busy_list))
> > + goto done;
> > +
> > + list_for_each_entry_safe(task, tmp, &thread->task_busy_list,
> > + list_entry) {
> > + cmdq_task_exec_done(task, -ECONNABORTED);
>
> cmdq_task_exec_done(task, CMDQ_CB_ERROR) ? However, I've like to use the
> standard error as you write here.
>

Ok, for consistent with current design, I will change to CMDQ_CB_ERROR.
And send another patch to change all cmdq error definition to standard
error next time.


Regards,
Dennis


> Regards,
> CK
>
> > + kfree(task);
> > + }
> > +
> > + cmdq_thread_disable(cmdq, thread);
> > + clk_disable(cmdq->clock);
> > +done:
> > + /*
> > + * The thread->task_busy_list empty means thread already disable. The
> > + * cmdq_mbox_send_data() always reset thread which clear disable and
> > + * suspend statue when first pkt send to channel, so there is no need
> > + * to do any operation here, only unlock and leave.
> > + */
> > + spin_unlock_irqrestore(&thread->chan->lock, flags);
> > }
> >
> > static const struct mbox_chan_ops cmdq_mbox_chan_ops = {
>
>

2020-02-29 13:42:16

by Dennis-YC Hsieh

Subject: Re: [PATCH v3 05/13] soc: mediatek: cmdq: return send msg error code

Hi CK,

Thanks for your comment.

On Fri, 2020-02-28 at 23:39 +0800, CK Hu wrote:
> Hi, Dennis:
>
> On Fri, 2020-02-28 at 21:44 +0800, Dennis YC Hsieh wrote:
> > Return error code to client if send message fail,
> > so that client has chance to error handling.
> >
> > Fixes: 576f1b4bc802 ("soc: mediatek: Add Mediatek CMDQ helper")
> > Signed-off-by: Dennis YC Hsieh <[email protected]>
> > ---
> > drivers/soc/mediatek/mtk-cmdq-helper.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
> > index 2e1bc513569b..0698612de5ad 100644
> > --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> > +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> > @@ -351,11 +351,11 @@ int cmdq_pkt_flush_async(struct cmdq_pkt *pkt, cmdq_async_flush_cb cb,
> > spin_unlock_irqrestore(&client->lock, flags);
> > }
> >
> > - mbox_send_message(client->chan, pkt);
> > + err = mbox_send_message(client->chan, pkt);
> > /* We can send next packet immediately, so just call txdone. */
> > mbox_client_txdone(client->chan, 0);
>
> If error happen, why tx is done? I think you should return immediately
> when error happen.

ok, I will return error code directly.


Regards,
Dennis

>
> Regards,
> CK
>
> >
> > - return 0;
> > + return err;
> > }
> > EXPORT_SYMBOL(cmdq_pkt_flush_async);
> >
>
>

2020-02-29 13:43:52

by Dennis-YC Hsieh

Subject: Re: [PATCH v3 11/13] soc: mediatek: cmdq: add jump function

Hi CK,

Thanks for your comment.

On Fri, 2020-02-28 at 22:59 +0800, CK Hu wrote:
> Hi, Dennis:
>
> On Fri, 2020-02-28 at 21:44 +0800, Dennis YC Hsieh wrote:
> > Add jump function so that client can jump to any address which
> > contains instruction.
> >
> > Signed-off-by: Dennis YC Hsieh <[email protected]>
> > ---
> > drivers/soc/mediatek/mtk-cmdq-helper.c | 12 ++++++++++++
> > include/linux/soc/mediatek/mtk-cmdq.h | 11 +++++++++++
> > 2 files changed, 23 insertions(+)
> >
> > diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
> > index 58fec634dcf1..bbc68a7c81e9 100644
> > --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> > +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> > @@ -372,6 +372,18 @@ int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value)
> > }
> > EXPORT_SYMBOL(cmdq_pkt_assign);
> >
> > +int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr)
> > +{
> > + struct cmdq_client *cl = pkt->cl;
> > + struct cmdq_instruction inst = { {0} };
> > +
> > + inst.op = CMDQ_CODE_JUMP;
> > + inst.offset = 1;
>
> Symbolize the value '1'.
>
> > + inst.value = addr >> cmdq_mbox_shift(cl->chan);
>
> If you write as 'cmdq_mbox_shift(pkt->cl->chan)', you could drop local
> variable 'cl'.

Ok, will do.


Regards,
Dennis

>
> Regards,
> CK
>
> > + return cmdq_pkt_append_command(pkt, inst);
> > +}
> > +EXPORT_SYMBOL(cmdq_pkt_jump);
> > +
> > int cmdq_pkt_finalize(struct cmdq_pkt *pkt)
> > {
> > struct cmdq_instruction inst = { {0} };
> > diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
> > index 99e77155f967..1a6c56f3bec1 100644
> > --- a/include/linux/soc/mediatek/mtk-cmdq.h
> > +++ b/include/linux/soc/mediatek/mtk-cmdq.h
> > @@ -213,6 +213,17 @@ int cmdq_pkt_poll_mask(struct cmdq_pkt *pkt, u8 subsys,
> > */
> > int cmdq_pkt_assign(struct cmdq_pkt *pkt, u16 reg_idx, u32 value);
> >
> > +/**
> > + * cmdq_pkt_jump() - Append jump command to the CMDQ packet, ask GCE
> > + * to execute an instruction that change current thread PC to
> > + * a physical address which should contains more instruction.
> > + * @pkt: the CMDQ packet
> > + * @addr: physical address of target instruction buffer
> > + *
> > + * Return: 0 for success; else the error code is returned
> > + */
> > +int cmdq_pkt_jump(struct cmdq_pkt *pkt, dma_addr_t addr);
> > +
> > /**
> > * cmdq_pkt_finalize() - Append EOC and jump command to pkt.
> > * @pkt: the CMDQ packet
>
>

2020-02-29 14:39:28

by Dennis-YC Hsieh

Subject: Re: [PATCH v3 12/13] soc: mediatek: cmdq: add clear option in cmdq_pkt_wfe api

Hi CK,

Thanks for you comment.

On Fri, 2020-02-28 at 22:32 +0800, CK Hu wrote:
> Hi, Dennis:
>
> On Fri, 2020-02-28 at 21:44 +0800, Dennis YC Hsieh wrote:
> > Add clear parameter to let client decide if
> > event should be clear to 0 after GCE receive it.
> >
> > Signed-off-by: Dennis YC Hsieh <[email protected]>
> > ---
> > drivers/soc/mediatek/mtk-cmdq-helper.c | 5 +++--
> > include/linux/mailbox/mtk-cmdq-mailbox.h | 3 +--
> > include/linux/soc/mediatek/mtk-cmdq.h | 5 +++--
> > 3 files changed, 7 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c
> > index bbc68a7c81e9..406e1d34d234 100644
> > --- a/drivers/soc/mediatek/mtk-cmdq-helper.c
> > +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c
> > @@ -295,15 +295,16 @@ int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
> > }
> > EXPORT_SYMBOL(cmdq_pkt_write_s_value);
> >
> > -int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event)
> > +int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event, bool clear)
> > {
> > struct cmdq_instruction inst = { {0} };
> > + u32 clear_option = clear ? CMDQ_WFE_UPDATE : 0;
> >
> > if (event >= CMDQ_MAX_EVENT)
> > return -EINVAL;
> >
> > inst.op = CMDQ_CODE_WFE;
> > - inst.value = CMDQ_WFE_OPTION;
> > + inst.value = CMDQ_WFE_OPTION | clear_option;
> > inst.event = event;
> >
> > return cmdq_pkt_append_command(pkt, inst);
> > diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h
> > index 3f6bc0dfd5da..42d2a30e6a70 100644
> > --- a/include/linux/mailbox/mtk-cmdq-mailbox.h
> > +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h
> > @@ -27,8 +27,7 @@
> > * bit 16-27: update value
> > * bit 31: 1 - update, 0 - no update
> > */
> > -#define CMDQ_WFE_OPTION (CMDQ_WFE_UPDATE | CMDQ_WFE_WAIT | \
> > - CMDQ_WFE_WAIT_VALUE)
> > +#define CMDQ_WFE_OPTION (CMDQ_WFE_WAIT | CMDQ_WFE_WAIT_VALUE)
> >
> > /** cmdq event maximum */
> > #define CMDQ_MAX_EVENT 0x3ff
> > diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h
> > index 1a6c56f3bec1..d63749440697 100644
> > --- a/include/linux/soc/mediatek/mtk-cmdq.h
> > +++ b/include/linux/soc/mediatek/mtk-cmdq.h
> > @@ -152,11 +152,12 @@ int cmdq_pkt_write_s_value(struct cmdq_pkt *pkt, u16 high_addr_reg_idx,
> > /**
> > * cmdq_pkt_wfe() - append wait for event command to the CMDQ packet
> > * @pkt: the CMDQ packet
> > - * @event: the desired event type to "wait and CLEAR"
> > + * @event: the desired event type to wait
> > + * @clear: clear event or not after event arrive
> > *
> > * Return: 0 for success; else the error code is returned
> > */
> > -int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event);
> > +int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event, bool clear);
>
> I think you should modify client driver [1] as well in this patch.
> Change it to
>
> cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false);
>
> [1]
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/mediatek/mtk_drm_crtc.c?h=v5.6-rc3#n491
>
> Regards,
> CK

ok, will do


Regards,
Dennis


>
> >
> > /**
> > * cmdq_pkt_clear_event() - append clear event command to the CMDQ packet
>
>

2020-03-02 20:16:14

by Rob Herring (Arm)

Subject: Re: [PATCH v3 01/13] dt-binding: gce: add gce header file for mt6779

On Fri, 28 Feb 2020 21:44:09 +0800, Dennis YC Hsieh wrote:
> Add documentation for the mt6779 gce.
>
> Add gce header file defined the gce hardware event,
> subsys number and constant for mt6779.
>
> Signed-off-by: Dennis YC Hsieh <[email protected]>
> ---
> .../devicetree/bindings/mailbox/mtk-gce.txt | 8 +-
> include/dt-bindings/gce/mt6779-gce.h | 222 ++++++++++++++++++
> 2 files changed, 227 insertions(+), 3 deletions(-)
> create mode 100644 include/dt-bindings/gce/mt6779-gce.h
>

Please add Acked-by/Reviewed-by tags when posting new versions. However,
there's no need to repost patches *only* to add the tags. The upstream
maintainer will do that for acks received on the version they apply.

If a tag was not added on purpose, please state why and what changed.