2020-03-02 21:51:24

by Jolly Shah

Subject: [PATCH v2 1/4] drivers: clk: zynqmp: Limit bestdiv with maxdiv

From: Rajan Vaja <[email protected]>

Clock divider value should not be greater than maximum divider value.
So use minimum of best divider or maximum divider value.

Signed-off-by: Rajan Vaja <[email protected]>
Signed-off-by: Jolly Shah <[email protected]>
---
drivers/clk/zynqmp/divider.c | 2 ++
1 file changed, 2 insertions(+)

diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
index 973cdf0..7d2cb61 100644
--- a/drivers/clk/zynqmp/divider.c
+++ b/drivers/clk/zynqmp/divider.c
@@ -198,6 +198,8 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw,

if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac)
bestdiv = rate % *prate ? 1 : bestdiv;
+
+ bestdiv = min_t(u32, bestdiv, divider->max_div);
*prate = rate * bestdiv;

return rate;
--
2.7.4

2020-05-27 09:27:17

by Stephen Boyd

Subject: Re: [PATCH v2 1/4] drivers: clk: zynqmp: Limit bestdiv with maxdiv

Quoting Jolly Shah (2020-03-02 13:50:40)
> From: Rajan Vaja <[email protected]>
>
> Clock divider value should not be greater than maximum divider value.
> So use minimum of best divider or maximum divider value.
>
> Signed-off-by: Rajan Vaja <[email protected]>
> Signed-off-by: Jolly Shah <[email protected]>
> ---

Applied to clk-next