Change since v4:
1. fix format of pinctrl bindings
Change since v3:
1. add bindings for "mediatek,mt6779-pinctrl"
2. add some comments into the code (e.g. virtual gpio ...) 3. add Acked-by tags 4. add pmu node into dts 5. support ppi partition and fix base address in gic node of dts
[note]
[1] need bindings for "arm,cortex-a75" in patch 6
> Already in Rob's tree here:
Change since v2:
1. add Reviewed-by tags
2. fix checkpatch warnings with strict level
Change since v1:
first patchset
Andy Teng (1):
dt-bindings: pinctrl: add bindings for MediaTek MT6779 SoC
Hanks Chen (5):
pinctrl: mediatek: update pinmux definitions for mt6779
pinctrl: mediatek: avoid virtual gpio trying to set reg
pinctrl: mediatek: add pinctrl support for MT6779 SoC
pinctrl: mediatek: add mt6779 eint support
arm64: dts: add dts nodes for MT6779
.../bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 208 ++
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 +
arch/arm64/boot/dts/mediatek/mt6779.dtsi | 265 +++
drivers/pinctrl/mediatek/Kconfig | 7 +
drivers/pinctrl/mediatek/Makefile | 1 +
drivers/pinctrl/mediatek/pinctrl-mt6779.c | 783 ++++++++
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 28 +
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h | 1 +
drivers/pinctrl/mediatek/pinctrl-mtk-mt6779.h | 2085 ++++++++++++++++++++
drivers/pinctrl/mediatek/pinctrl-paris.c | 7 +
include/dt-bindings/pinctrl/mt6779-pinfunc.h | 1242 ++++++++++++
12 files changed, 4659 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt6779.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt6779.h
create mode 100644 include/dt-bindings/pinctrl/mt6779-pinfunc.h
for virtual gpios, they should not do reg setting and
should behave as expected for eint function.
Change-Id: I913501f21c841c2cb981530cd387395648f83984
Signed-off-by: Hanks Chen <[email protected]>
Signed-off-by: Mars Cheng <[email protected]>
---
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 28 ++++++++++++++++++++++
drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h | 1 +
drivers/pinctrl/mediatek/pinctrl-paris.c | 7 ++++++
3 files changed, 36 insertions(+)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
index 20e1c89..087d233 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
@@ -226,6 +226,31 @@ static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw, unsigned long eint_n)
return EINT_NA;
}
+/*
+ * Virtual GPIO only used inside SOC and not being exported to outside SOC.
+ * Some modules use virtual GPIO as eint (e.g. pmif or usb).
+ * In MTK platform, external interrupt (EINT) and GPIO is 1-1 mapping
+ * and we can set GPIO as eint.
+ * But some modules use specific eint which doesn't have real GPIO pin.
+ * So we use virtual GPIO to map it.
+ */
+
+bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n)
+{
+ const struct mtk_pin_desc *desc;
+ bool virt_gpio = false;
+
+ if (gpio_n >= hw->soc->npins)
+ return virt_gpio;
+
+ desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
+
+ if (desc->funcs && !desc->funcs[desc->eint.eint_m].name)
+ virt_gpio = true;
+
+ return virt_gpio;
+}
+
static int mtk_xt_get_gpio_n(void *data, unsigned long eint_n,
unsigned int *gpio_n,
struct gpio_chip **gpio_chip)
@@ -278,6 +303,9 @@ static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n)
if (err)
return err;
+ if (mtk_is_virt_gpio(hw, gpio_n))
+ return 0;
+
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
index 1b7da42..cda1c7a0 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h
@@ -299,4 +299,5 @@ int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw,
int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw,
const struct mtk_pin_desc *desc, u32 *val);
+bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n);
#endif /* __PINCTRL_MTK_COMMON_V2_H */
diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c
index 923264d..7fba76d 100644
--- a/drivers/pinctrl/mediatek/pinctrl-paris.c
+++ b/drivers/pinctrl/mediatek/pinctrl-paris.c
@@ -693,6 +693,13 @@ static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
const struct mtk_pin_desc *desc;
int value, err;
+ /*
+ * "Virtual" GPIOs are always and only used for interrupts
+ * Since they are only used for interrupts, they are always inputs
+ */
+ if (mtk_is_virt_gpio(hw, gpio))
+ return 1;
+
desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &value);
--
1.7.9.5
this adds initial MT6779 dts settings fo board support,
including cpu, gic, timer, ccf, pinctrl, uart...etc.
Change-Id: Iad282ca66c8a5692760924929e1946eb99918665
Signed-off-by: Hanks Chen <[email protected]>
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 ++++
arch/arm64/boot/dts/mediatek/mt6779.dtsi | 265 +++++++++++++++++++++++++++
3 files changed, 297 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 458bbc4..53f1c61 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt6779-evb.dts b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
new file mode 100644
index 0000000..164f5cb
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6779-evb.dts
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Mars.C <[email protected]>
+ *
+ */
+
+/dts-v1/;
+#include "mt6779.dtsi"
+
+/ {
+ model = "MediaTek MT6779 EVB";
+ compatible = "mediatek,mt6779-evb", "mediatek,mt6779";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x1e800000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
new file mode 100644
index 0000000..422ff5f
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
@@ -0,0 +1,265 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Mars.C <[email protected]>
+ *
+ */
+
+#include <dt-bindings/clock/mt6779-clk.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/mt6779-pinfunc.h>
+
+/ {
+ compatible = "mediatek,mt6779";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x000>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x100>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x200>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x300>;
+ };
+
+ cpu4: cpu@4 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x400>;
+ };
+
+ cpu5: cpu@5 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ enable-method = "psci";
+ reg = <0x500>;
+ };
+
+ cpu6: cpu@6 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a75";
+ enable-method = "psci";
+ reg = <0x600>;
+ };
+
+ cpu7: cpu@7 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a75";
+ enable-method = "psci";
+ reg = <0x700>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW 0>;
+ };
+
+ clk26m: oscillator@0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
+ };
+
+ clk32k: oscillator@1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "clk32k";
+ };
+
+ uart_clk: dummy26m {
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+ #clock-cells = <0>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ gic: interrupt-controller@0c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <4>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x0c000000 0 0x40000>, /* GICD */
+ <0 0x0c040000 0 0x200000>; /* GICR */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ ppi-partitions {
+ ppi_cluster0: interrupt-partition-0 {
+ affinity = <&cpu0 &cpu1 \
+ &cpu2 &cpu3 &cpu4 &cpu5>;
+ };
+ ppi_cluster1: interrupt-partition-1 {
+ affinity = <&cpu6 &cpu7>;
+ };
+ };
+
+ };
+
+ sysirq: intpol-controller@0c53a650 {
+ compatible = "mediatek,mt6779-sysirq",
+ "mediatek,mt6577-sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0 0x0c53a650 0 0x50>;
+ };
+
+ topckgen: clock-controller@10000000 {
+ compatible = "mediatek,mt6779-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg_ao: clock-controller@10001000 {
+ compatible = "mediatek,mt6779-infracfg_ao", "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pio: pinctrl@10005000 {
+ compatible = "mediatek,mt6779-pinctrl", "syscon";
+ reg = <0 0x10005000 0 0x1000>,
+ <0 0x11c20000 0 0x1000>,
+ <0 0x11d10000 0 0x1000>,
+ <0 0x11e20000 0 0x1000>,
+ <0 0x11e70000 0 0x1000>,
+ <0 0x11ea0000 0 0x1000>,
+ <0 0x11f20000 0 0x1000>,
+ <0 0x11f30000 0 0x1000>,
+ <0 0x1000b000 0 0x1000>;
+ reg-names = "gpio", "iocfg_rm",
+ "iocfg_br", "iocfg_lm",
+ "iocfg_lb", "iocfg_rt",
+ "iocfg_lt", "iocfg_tl",
+ "eint";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pio 0 0 210>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ apmixed: clock-controller@1000c000 {
+ compatible = "mediatek,mt6779-apmixed", "syscon";
+ reg = <0 0x1000c000 0 0xe00>;
+ #clock-cells = <1>;
+ };
+
+ uart0: serial@11002000 {
+ compatible = "mediatek,mt6779-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11002000 0 0x400>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&uart_clk>;
+ status = "disabled";
+ };
+
+ uart1: serial@11003000 {
+ compatible = "mediatek,mt6779-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11003000 0 0x400>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&uart_clk>;
+ status = "disabled";
+ };
+
+ audio: clock-controller@11210000 {
+ compatible = "mediatek,mt6779-audio", "syscon";
+ reg = <0 0x11210000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mfgcfg: clock-controller@13fbf000 {
+ compatible = "mediatek,mt6779-mfgcfg", "syscon";
+ reg = <0 0x13fbf000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mmsys: clock-controller@14000000 {
+ compatible = "mediatek,mt6779-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys: clock-controller@15020000 {
+ compatible = "mediatek,mt6779-imgsys", "syscon";
+ reg = <0 0x15020000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys: clock-controller@16000000 {
+ compatible = "mediatek,mt6779-vdecsys", "syscon";
+ reg = <0 0x16000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vencsys: clock-controller@17000000 {
+ compatible = "mediatek,mt6779-vencsys", "syscon";
+ reg = <0 0x17000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys: clock-controller@1a000000 {
+ compatible = "mediatek,mt6779-camsys", "syscon";
+ reg = <0 0x1a000000 0 0x10000>;
+ #clock-cells = <1>;
+ };
+
+ ipesys: clock-controller@1b000000 {
+ compatible = "mediatek,mt6779-ipesys", "syscon";
+ reg = <0 0x1b000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ };
+};
--
1.7.9.5
From: Andy Teng <[email protected]>
Add devicetree bindings for MediaTek MT6779 pinctrl driver.
Change-Id: I92586369564948f2628f70421bcd70668f132c4f
Signed-off-by: Andy Teng <[email protected]>
---
.../bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 208 ++++++++++++++++++++
1 file changed, 208 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
new file mode 100644
index 0000000..5f9bbf1
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
@@ -0,0 +1,208 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek MT6779 Pin Controller Device Tree Bindings
+
+maintainers:
+ - Andy Teng <[email protected]>
+
+description: |+
+ The pin controller node should be the child of a syscon node with the
+ required property:
+ - compatible: "syscon"
+
+properties:
+ compatible:
+ const: mediatek,mt6779-pinctrl
+
+ reg:
+ minItems: 9
+ maxItems: 9
+ description: |
+ physical address base for gpio-related control registers.
+
+ reg-names:
+ description: |
+ GPIO base register names.
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ const: 2
+ description: |
+ Number of cells in GPIO specifier. Since the generic GPIO
+ binding is used, the amount of cells must be specified as 2. See the below
+ mentioned gpio binding representation for description of particular cells.
+
+ gpio-ranges:
+ minItems: 1
+ maxItems: 5
+ description: |
+ GPIO valid number range.
+
+ interrupt-controller: true
+
+ interrupts:
+ minItems: 1
+ maxItems: 4
+ description: |
+ The interrupt outputs to sysirq.
+
+ "#interrupt-cells":
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - gpio-controller
+ - "#gpio-cells"
+ - gpio-ranges
+ - interrupt-controller
+ - interrupts
+ - "#interrupt-cells"
+
+patternProperties:
+ '^pins*$':
+ type: object
+ description: |
+ A pinctrl node should contain at least one subnodes representing the
+ pinctrl groups available on the machine. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to muxer
+ configuration, pullups, drive strength, input enable/disable and input schmitt.
+
+ properties:
+ pinmux:
+ description:
+ integer array, represents gpio pin number and mux setting.
+ Supported pin number and mux varies for different SoCs, and are defined
+ as macros in boot/dts/<soc>-pinfunc.h directly.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
+ bias-disable:
+ type: boolean
+
+ bias-pull-up:
+ oneOf:
+ - type: boolean
+ - $ref: /schemas/types.yaml#/definitions/uint32
+
+ bias-pull-down:
+ oneOf:
+ - type: boolean
+ - $ref: /schemas/types.yaml#/definitions/uint32
+
+ input-enable:
+ type: boolean
+
+ input-disable:
+ type: boolean
+
+ output-low:
+ type: boolean
+
+ output-high:
+ type: boolean
+
+ input-schmitt-enable:
+ type: boolean
+
+ input-schmitt-disable:
+ type: boolean
+
+ mediatek,pull-up-adv:
+ description: |
+ Pull up setings for 2 pull resistors, R0 and R1. User can
+ configure those special pins. Valid arguments are described as below:
+ 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disable.
+ 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
+ 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
+ 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [0, 1, 2, 3]
+
+ mediatek,pull-down-adv:
+ description: |
+ Pull down settings for 2 pull resistors, R0 and R1. User can
+ configure those special pins. Valid arguments are described as below:
+ 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disable.
+ 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
+ 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
+ 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [0, 1, 2, 3]
+
+ drive-strength:
+ description: |
+ Selects the drive strength for the specified pins in mA.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [2, 4, 6, 8, 10, 12, 14, 16]
+
+ required:
+ - pinmux
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/pinctrl/mt6779-pinfunc.h>
+
+ pio: pinctrl@10005000 {
+ compatible = "mediatek,mt6779-pinctrl";
+ reg = <0 0x10005000 0 0x1000>,
+ <0 0x11c20000 0 0x1000>,
+ <0 0x11d10000 0 0x1000>,
+ <0 0x11e20000 0 0x1000>,
+ <0 0x11e70000 0 0x1000>,
+ <0 0x11ea0000 0 0x1000>,
+ <0 0x11f20000 0 0x1000>,
+ <0 0x11f30000 0 0x1000>,
+ <0 0x1000b000 0 0x1000>;
+ reg-names = "gpio", "iocfg_rm",
+ "iocfg_br", "iocfg_lm",
+ "iocfg_lb", "iocfg_rt",
+ "iocfg_lt", "iocfg_tl",
+ "eint";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pio 0 0 210>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
+
+ mmc0_pins_default: mmc0default {
+ pins_cmd_dat {
+ pinmux = <PINMUX_GPIO168__FUNC_MSDC0_DAT0>,
+ <PINMUX_GPIO172__FUNC_MSDC0_DAT1>,
+ <PINMUX_GPIO169__FUNC_MSDC0_DAT2>,
+ <PINMUX_GPIO177__FUNC_MSDC0_DAT3>,
+ <PINMUX_GPIO170__FUNC_MSDC0_DAT4>,
+ <PINMUX_GPIO173__FUNC_MSDC0_DAT5>,
+ <PINMUX_GPIO171__FUNC_MSDC0_DAT6>,
+ <PINMUX_GPIO174__FUNC_MSDC0_DAT7>,
+ <PINMUX_GPIO167__FUNC_MSDC0_CMD>;
+ input-enable;
+ mediatek,pull-up-adv = <1>;
+ };
+ pins_clk {
+ pinmux = <PINMUX_GPIO176__FUNC_MSDC0_CLK>;
+ mediatek,pull-down-adv = <2>;
+ };
+ pins_rst {
+ pinmux = <PINMUX_GPIO178__FUNC_MSDC0_RSTB>;
+ mediatek,pull-up-adv = <0>;
+ };
+ };
+
+ mmc0 {
+ pinctrl-0 = <&mmc0_pins_default>;
+ pinctrl-names = "default";
+ };
+ };
+
--
1.7.9.5
add driver setting to support mt6779 eint
Change-Id: I7aa1e64112cb2e43813328d9971fd644629edf0a
Signed-off-by: Hanks Chen <[email protected]>
Signed-off-by: Mars Cheng <[email protected]>
---
drivers/pinctrl/mediatek/pinctrl-mt6779.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6779.c b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
index 145bf22..3282260 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt6779.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt6779.c
@@ -731,11 +731,19 @@
"iocfg_rt", "iocfg_lt", "iocfg_tl",
};
+static const struct mtk_eint_hw mt6779_eint_hw = {
+ .port_mask = 7,
+ .ports = 6,
+ .ap_num = 195,
+ .db_cnt = 13,
+};
+
static const struct mtk_pin_soc mt6779_data = {
.reg_cal = mt6779_reg_cals,
.pins = mtk_pins_mt6779,
.npins = ARRAY_SIZE(mtk_pins_mt6779),
.ngrps = ARRAY_SIZE(mtk_pins_mt6779),
+ .eint_hw = &mt6779_eint_hw,
.gpio_m = 0,
.ies_present = true,
.base_names = mt6779_pinctrl_register_base_names,
--
1.7.9.5
On Wed, 2020-03-25 at 16:12 +0800, Hanks Chen wrote:
> for virtual gpios, they should not do reg setting and
> should behave as expected for eint function.
>
> Change-Id: I913501f21c841c2cb981530cd387395648f83984
Please remove Change-Id:
> Signed-off-by: Hanks Chen <[email protected]>
> Signed-off-by: Mars Cheng <[email protected]>
> ---
> drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 28 ++++++++++++++++++++++
> drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.h | 1 +
> drivers/pinctrl/mediatek/pinctrl-paris.c | 7 ++++++
> 3 files changed, 36 insertions(+)
>
> diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
> index 20e1c89..087d233 100644
> --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
> +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c
> @@ -226,6 +226,31 @@ static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw, unsigned long eint_n)
> return EINT_NA;
> }
>
> +/*
> + * Virtual GPIO only used inside SOC and not being exported to outside SOC.
> + * Some modules use virtual GPIO as eint (e.g. pmif or usb).
> + * In MTK platform, external interrupt (EINT) and GPIO is 1-1 mapping
> + * and we can set GPIO as eint.
> + * But some modules use specific eint which doesn't have real GPIO pin.
> + * So we use virtual GPIO to map it.
> + */
> +
> +bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n)
> +{
> + const struct mtk_pin_desc *desc;
> + bool virt_gpio = false;
> +
> + if (gpio_n >= hw->soc->npins)
> + return virt_gpio;
> +
> + desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio_n];
> +
> + if (desc->funcs && !desc->funcs[desc->eint.eint_m].name)
> + virt_gpio = true;
I think removing virt_gpio and just return true/false for this function
will make it easier to read.
Joe.C
> +
> + return virt_gpio;
> +}