From: René van Dorst <[email protected]>
Moving mt7623 logic out off mt7530, is required to make hardware setting
consistent after we introduce phylink to mtk driver.
Fixes: ca366d6c889b ("net: dsa: mt7530: Convert to PHYLINK API")
Reviewed-by: Sean Wang <[email protected]>
Tested-by: Sean Wang <[email protected]>
Signed-off-by: René van Dorst <[email protected]>
---
drivers/net/dsa/mt7530.c | 85 ----------------------------------------
drivers/net/dsa/mt7530.h | 10 -----
2 files changed, 95 deletions(-)
diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c
index 970d44354f4c..3ab0a3eae68b 100644
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
@@ -66,58 +66,6 @@ static const struct mt7530_mib_desc mt7530_mib[] = {
MIB_DESC(1, 0xb8, "RxArlDrop"),
};
-static int
-mt7623_trgmii_write(struct mt7530_priv *priv, u32 reg, u32 val)
-{
- int ret;
-
- ret = regmap_write(priv->ethernet, TRGMII_BASE(reg), val);
- if (ret < 0)
- dev_err(priv->dev,
- "failed to priv write register\n");
- return ret;
-}
-
-static u32
-mt7623_trgmii_read(struct mt7530_priv *priv, u32 reg)
-{
- int ret;
- u32 val;
-
- ret = regmap_read(priv->ethernet, TRGMII_BASE(reg), &val);
- if (ret < 0) {
- dev_err(priv->dev,
- "failed to priv read register\n");
- return ret;
- }
-
- return val;
-}
-
-static void
-mt7623_trgmii_rmw(struct mt7530_priv *priv, u32 reg,
- u32 mask, u32 set)
-{
- u32 val;
-
- val = mt7623_trgmii_read(priv, reg);
- val &= ~mask;
- val |= set;
- mt7623_trgmii_write(priv, reg, val);
-}
-
-static void
-mt7623_trgmii_set(struct mt7530_priv *priv, u32 reg, u32 val)
-{
- mt7623_trgmii_rmw(priv, reg, 0, val);
-}
-
-static void
-mt7623_trgmii_clear(struct mt7530_priv *priv, u32 reg, u32 val)
-{
- mt7623_trgmii_rmw(priv, reg, val, 0);
-}
-
static int
core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
{
@@ -538,27 +486,6 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, int mode)
for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
mt7530_rmw(priv, MT7530_TRGMII_RD(i),
RD_TAP_MASK, RD_TAP(16));
- else
- if (priv->id != ID_MT7621)
- mt7623_trgmii_set(priv, GSW_INTF_MODE,
- INTF_MODE_TRGMII);
-
- return 0;
-}
-
-static int
-mt7623_pad_clk_setup(struct dsa_switch *ds)
-{
- struct mt7530_priv *priv = ds->priv;
- int i;
-
- for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
- mt7623_trgmii_write(priv, GSW_TRGMII_TD_ODT(i),
- TD_DM_DRVP(8) | TD_DM_DRVN(8));
-
- mt7623_trgmii_set(priv, GSW_TRGMII_RCK_CTRL, RX_RST | RXC_DQSISEL);
- mt7623_trgmii_clear(priv, GSW_TRGMII_RCK_CTRL, RX_RST);
-
return 0;
}
@@ -1311,10 +1238,6 @@ mt7530_setup(struct dsa_switch *ds)
dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent;
if (priv->id == ID_MT7530) {
- priv->ethernet = syscon_node_to_regmap(dn);
- if (IS_ERR(priv->ethernet))
- return PTR_ERR(priv->ethernet);
-
regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
ret = regulator_enable(priv->core_pwr);
if (ret < 0) {
@@ -1473,14 +1396,6 @@ static void mt7530_phylink_mac_config(struct dsa_switch *ds, int port,
/* Setup TX circuit incluing relevant PAD and driving */
mt7530_pad_clk_setup(ds, state->interface);
- if (priv->id == ID_MT7530) {
- /* Setup RX circuit, relevant PAD and driving on the
- * host which must be placed after the setup on the
- * device side is all finished.
- */
- mt7623_pad_clk_setup(ds);
- }
-
priv->p6_interface = state->interface;
break;
default:
diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h
index ef9b52f3152b..4aef6024441b 100644
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
@@ -277,7 +277,6 @@ enum mt7530_vlan_port_attr {
/* Registers for TRGMII on the both side */
#define MT7530_TRGMII_RCK_CTRL 0x7a00
-#define GSW_TRGMII_RCK_CTRL 0x300
#define RX_RST BIT(31)
#define RXC_DQSISEL BIT(30)
#define DQSI1_TAP_MASK (0x7f << 8)
@@ -286,31 +285,24 @@ enum mt7530_vlan_port_attr {
#define DQSI0_TAP(x) ((x) & 0x7f)
#define MT7530_TRGMII_RCK_RTT 0x7a04
-#define GSW_TRGMII_RCK_RTT 0x304
#define DQS1_GATE BIT(31)
#define DQS0_GATE BIT(30)
#define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8)
-#define GSW_TRGMII_RD(x) (0x310 + (x) * 8)
#define BSLIP_EN BIT(31)
#define EDGE_CHK BIT(30)
#define RD_TAP_MASK 0x7f
#define RD_TAP(x) ((x) & 0x7f)
-#define GSW_TRGMII_TXCTRL 0x340
#define MT7530_TRGMII_TXCTRL 0x7a40
#define TRAIN_TXEN BIT(31)
#define TXC_INV BIT(30)
#define TX_RST BIT(28)
#define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i))
-#define GSW_TRGMII_TD_ODT(i) (0x354 + 8 * (i))
#define TD_DM_DRVP(x) ((x) & 0xf)
#define TD_DM_DRVN(x) (((x) & 0xf) << 4)
-#define GSW_INTF_MODE 0x390
-#define INTF_MODE_TRGMII BIT(1)
-
#define MT7530_TRGMII_TCK_CTRL 0x7a78
#define TCK_TAP(x) (((x) & 0xf) << 8)
@@ -443,7 +435,6 @@ static const char *p5_intf_modes(unsigned int p5_interface)
* @ds: The pointer to the dsa core structure
* @bus: The bus used for the device and built-in PHY
* @rstc: The pointer to reset control used by MCM
- * @ethernet: The regmap used for access TRGMII-based registers
* @core_pwr: The power supplied into the core
* @io_pwr: The power supplied into the I/O
* @reset: The descriptor for GPIO line tied to its reset pin
@@ -460,7 +451,6 @@ struct mt7530_priv {
struct dsa_switch *ds;
struct mii_bus *bus;
struct reset_control *rstc;
- struct regmap *ethernet;
struct regulator *core_pwr;
struct regulator *io_pwr;
struct gpio_desc *reset;
--
2.25.1
From: René van Dorst <[email protected]>
Moving mt7623 logic out off mt7530, is required to make hardware setting
consistent after we introduce phylink to mtk driver.
Fixes: b8fc9f30821e ("net: ethernet: mediatek: Add basic PHYLINK support")
Reviewed-by: Sean Wang <[email protected]>
Tested-by: Sean Wang <[email protected]>
Signed-off-by: René van Dorst <[email protected]>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 43 ++++++++++++++++++---
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 8 ++++
2 files changed, 45 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 8d28f90acfe7..14da599664e6 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -65,6 +65,17 @@ u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
return __raw_readl(eth->base + reg);
}
+u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg)
+{
+ u32 val;
+
+ val = mtk_r32(eth, reg);
+ val &= ~mask;
+ val |= set;
+ mtk_w32(eth, val, reg);
+ return reg;
+}
+
static int mtk_mdio_busy_wait(struct mtk_eth *eth)
{
unsigned long t_start = jiffies;
@@ -160,11 +171,21 @@ static int mt7621_gmac0_rgmii_adjust(struct mtk_eth *eth,
return 0;
}
-static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed)
+static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth,
+ phy_interface_t interface, int speed)
{
u32 val;
int ret;
+ if (interface == PHY_INTERFACE_MODE_TRGMII) {
+ mtk_w32(eth, TRGMII_MODE, INTF_MODE);
+ val = 500000000;
+ ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val);
+ if (ret)
+ dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
+ return;
+ }
+
val = (speed == SPEED_1000) ?
INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100;
mtk_w32(eth, val, INTF_MODE);
@@ -193,7 +214,7 @@ static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
struct mtk_mac *mac = container_of(config, struct mtk_mac,
phylink_config);
struct mtk_eth *eth = mac->hw;
- u32 mcr_cur, mcr_new, sid;
+ u32 mcr_cur, mcr_new, sid, i;
int val, ge_mode, err;
/* MT76x8 has no hardware settings between for the MAC */
@@ -251,10 +272,20 @@ static void mtk_mac_config(struct phylink_config *config, unsigned int mode,
state->interface))
goto err_phy;
} else {
- if (state->interface !=
- PHY_INTERFACE_MODE_TRGMII)
- mtk_gmac0_rgmii_adjust(mac->hw,
- state->speed);
+ mtk_gmac0_rgmii_adjust(mac->hw,
+ state->interface,
+ state->speed);
+
+ /* mt7623_pad_clk_setup */
+ for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
+ mtk_w32(mac->hw,
+ TD_DM_DRVP(8) | TD_DM_DRVN(8),
+ TRGMII_TD_ODT(i));
+
+ /* Assert/release MT7623 RXC reset */
+ mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL,
+ TRGMII_RCK_CTRL);
+ mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL);
}
}
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 85830fe14a1b..454cfcd465fd 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -352,10 +352,13 @@
#define DQSI0(x) ((x << 0) & GENMASK(6, 0))
#define DQSI1(x) ((x << 8) & GENMASK(14, 8))
#define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16))
+#define RXC_RST BIT(31)
#define RXC_DQSISEL BIT(30)
#define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16))
#define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2)
+#define NUM_TRGMII_CTRL 5
+
/* TRGMII RXC control register */
#define TRGMII_TCK_CTRL 0x10340
#define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16))
@@ -363,6 +366,11 @@
#define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2)
#define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2))
+/* TRGMII TX Drive Strength */
+#define TRGMII_TD_ODT(i) (0x10354 + 8 * (i))
+#define TD_DM_DRVP(x) ((x) & 0xf)
+#define TD_DM_DRVN(x) (((x) & 0xf) << 4)
+
/* TRGMII Interface mode register */
#define INTF_MODE 0x10390
#define TRGMII_INTF_DIS BIT(0)
--
2.25.1
Hi Sean,
See comments below.
Quoting [email protected]:
> From: René van Dorst <[email protected]>
>
> Moving mt7623 logic out off mt7530, is required to make hardware setting
> consistent after we introduce phylink to mtk driver.
>
> Fixes: b8fc9f30821e ("net: ethernet: mediatek: Add basic PHYLINK support")
> Reviewed-by: Sean Wang <[email protected]>
> Tested-by: Sean Wang <[email protected]>
> Signed-off-by: René van Dorst <[email protected]>
> ---
> drivers/net/ethernet/mediatek/mtk_eth_soc.c | 43 ++++++++++++++++++---
> drivers/net/ethernet/mediatek/mtk_eth_soc.h | 8 ++++
> 2 files changed, 45 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
> b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
> index 8d28f90acfe7..14da599664e6 100644
> --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
> +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
> @@ -65,6 +65,17 @@ u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
> return __raw_readl(eth->base + reg);
> }
>
> +u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg)
> +{
> + u32 val;
> +
> + val = mtk_r32(eth, reg);
> + val &= ~mask;
> + val |= set;
> + mtk_w32(eth, val, reg);
> + return reg;
> +}
> +
> static int mtk_mdio_busy_wait(struct mtk_eth *eth)
> {
> unsigned long t_start = jiffies;
> @@ -160,11 +171,21 @@ static int mt7621_gmac0_rgmii_adjust(struct
> mtk_eth *eth,
> return 0;
> }
>
> -static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed)
> +static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth,
> + phy_interface_t interface, int speed)
> {
> u32 val;
> int ret;
>
> + if (interface == PHY_INTERFACE_MODE_TRGMII) {
> + mtk_w32(eth, TRGMII_MODE, INTF_MODE);
> + val = 500000000;
> + ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val);
> + if (ret)
> + dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
> + return;
> + }
> +
> val = (speed == SPEED_1000) ?
> INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100;
> mtk_w32(eth, val, INTF_MODE);
> @@ -193,7 +214,7 @@ static void mtk_mac_config(struct phylink_config
> *config, unsigned int mode,
> struct mtk_mac *mac = container_of(config, struct mtk_mac,
> phylink_config);
> struct mtk_eth *eth = mac->hw;
> - u32 mcr_cur, mcr_new, sid;
> + u32 mcr_cur, mcr_new, sid, i;
> int val, ge_mode, err;
>
> /* MT76x8 has no hardware settings between for the MAC */
> @@ -251,10 +272,20 @@ static void mtk_mac_config(struct
> phylink_config *config, unsigned int mode,
> state->interface))
> goto err_phy;
> } else {
> - if (state->interface !=
> - PHY_INTERFACE_MODE_TRGMII)
> - mtk_gmac0_rgmii_adjust(mac->hw,
> - state->speed);
> + mtk_gmac0_rgmii_adjust(mac->hw,
> + state->interface,
> + state->speed);
> +
As I tried to explain in my email of 27 March.
mtk_gmac0_rgmii_adjust() needs to be modified or split-up!
Russell King pointed out that mtk_gmac0_rgmii_adjust() is using state->speed
variable. This variable may has not the right value so it should not be used
here. Also mtk_gmac0_rgmii_adjust() is only called on a
state->interface change
not state->speed change.
So can we make this function only dependend on the state->interface and how?
I think in both cases, remove mtk_gmac0_rgmii_adjust() changes in this
patch and
create a separet patch to fix mtk_gmac0_rgmii_adjust() issue. Would be
great if
that also complies to the latest PHYLINK api [1]. So that functions that using
state->speed and other related parameters move to mac_link_up(). Similair also
on the mt7530 switch driver [2].
Greats,
René
[1]:
https://lore.kernel.org/linux-arm-kernel/[email protected]/
[2]:
https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=1d01145fd659f9f96ede1c34e3bea0ccb558a293
> + /* mt7623_pad_clk_setup */
> + for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
> + mtk_w32(mac->hw,
> + TD_DM_DRVP(8) | TD_DM_DRVN(8),
> + TRGMII_TD_ODT(i));
> +
> + /* Assert/release MT7623 RXC reset */
> + mtk_m32(mac->hw, 0, RXC_RST | RXC_DQSISEL,
> + TRGMII_RCK_CTRL);
> + mtk_m32(mac->hw, RXC_RST, 0, TRGMII_RCK_CTRL);
> }
> }
>
> diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> index 85830fe14a1b..454cfcd465fd 100644
> --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
> @@ -352,10 +352,13 @@
> #define DQSI0(x) ((x << 0) & GENMASK(6, 0))
> #define DQSI1(x) ((x << 8) & GENMASK(14, 8))
> #define RXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16))
> +#define RXC_RST BIT(31)
> #define RXC_DQSISEL BIT(30)
> #define RCK_CTRL_RGMII_1000 (RXC_DQSISEL | RXCTL_DMWTLAT(2) | DQSI1(16))
> #define RCK_CTRL_RGMII_10_100 RXCTL_DMWTLAT(2)
>
> +#define NUM_TRGMII_CTRL 5
> +
> /* TRGMII RXC control register */
> #define TRGMII_TCK_CTRL 0x10340
> #define TXCTL_DMWTLAT(x) ((x << 16) & GENMASK(18, 16))
> @@ -363,6 +366,11 @@
> #define TCK_CTRL_RGMII_1000 TXCTL_DMWTLAT(2)
> #define TCK_CTRL_RGMII_10_100 (TXC_INV | TXCTL_DMWTLAT(2))
>
> +/* TRGMII TX Drive Strength */
> +#define TRGMII_TD_ODT(i) (0x10354 + 8 * (i))
> +#define TD_DM_DRVP(x) ((x) & 0xf)
> +#define TD_DM_DRVN(x) (((x) & 0xf) << 4)
> +
> /* TRGMII Interface mode register */
> #define INTF_MODE 0x10390
> #define TRGMII_INTF_DIS BIT(0)
> --
> 2.25.1