2020-04-12 16:02:22

by Veerabhadrarao Badiganti

Subject: [PATCH V1 0/4] Minor fixes to sdhci-msm

Enable a couple of CAPS that qcom sd host controller supports.
Set a quirk for enabling support for auto cmd12.
And enable adma length mismatch error interrupt.

Veerabhadrarao Badiganti (4):
mmc: sdhci-msm: Enable MMC_CAP_WAIT_WHILE_BUSY host capability
mmc: sdhci-msm: Enable MMC_CAP_NEED_RSP_BUSY host capability
mmc: sdhci-msm: Set SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 quirk
mmc: sdhci-msm: Enable ADMA length mismatch error interrupt

drivers/mmc/host/sdhci-msm.c | 17 +++++++++++------
1 file changed, 11 insertions(+), 6 deletions(-)

--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project

2020-04-12 16:02:59

by Veerabhadrarao Badiganti

Subject: [PATCH V1 3/4] mmc: sdhci-msm: Set SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 quirk

sdhci-msm can support auto cmd12.
So enable SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 quirk.

Signed-off-by: Veerabhadrarao Badiganti <[email protected]>
---
drivers/mmc/host/sdhci-msm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index d826e9b..482045b 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -1882,7 +1882,9 @@ static void sdhci_msm_reset(struct sdhci_host *host, u8 mask)
static const struct sdhci_pltfm_data sdhci_msm_pdata = {
.quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
SDHCI_QUIRK_SINGLE_POWER_WRITE |
- SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
+ SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
+ SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
+
.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
.ops = &sdhci_msm_ops,
};
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project

2020-04-12 16:06:20

by Veerabhadrarao Badiganti

Subject: [PATCH V1 4/4] mmc: sdhci-msm: Enable ADMA length mismatch error interrupt

ADMA_ERR_SIZE_EN bit of VENDOR_SPECIFIC_FUNC register controls
ADMA length mismatch error interrupt. Enable it by default.

And update all bit shift defines with BIT macro.

Signed-off-by: Veerabhadrarao Badiganti <[email protected]>
---
drivers/mmc/host/sdhci-msm.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index 482045b..660e1bc 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -56,19 +56,19 @@
#define CORE_FLL_CYCLE_CNT BIT(18)
#define CORE_DLL_CLOCK_DISABLE BIT(21)

-#define CORE_VENDOR_SPEC_POR_VAL 0xa1c
+#define CORE_VENDOR_SPEC_POR_VAL 0xa3c
#define CORE_CLK_PWRSAVE BIT(1)
#define CORE_HC_MCLK_SEL_DFLT (2 << 8)
#define CORE_HC_MCLK_SEL_HS400 (3 << 8)
#define CORE_HC_MCLK_SEL_MASK (3 << 8)
-#define CORE_IO_PAD_PWR_SWITCH_EN (1 << 15)
-#define CORE_IO_PAD_PWR_SWITCH (1 << 16)
+#define CORE_IO_PAD_PWR_SWITCH_EN BIT(15)
+#define CORE_IO_PAD_PWR_SWITCH BIT(16)
#define CORE_HC_SELECT_IN_EN BIT(18)
#define CORE_HC_SELECT_IN_HS400 (6 << 19)
#define CORE_HC_SELECT_IN_MASK (7 << 19)

-#define CORE_3_0V_SUPPORT (1 << 25)
-#define CORE_1_8V_SUPPORT (1 << 26)
+#define CORE_3_0V_SUPPORT BIT(25)
+#define CORE_1_8V_SUPPORT BIT(26)
#define CORE_VOLT_SUPPORT (CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT)

#define CORE_CSR_CDC_CTLR_CFG0 0x130
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project

2020-04-12 17:10:57

by Veerabhadrarao Badiganti

Subject: Re: [PATCH V1 4/4] mmc: sdhci-msm: Enable ADMA length mismatch error interrupt

On 4/12/2020 9:23 PM, Veerabhadrarao Badiganti wrote:
> ADMA_ERR_SIZE_EN bit of VENDOR_SPECIFIC_FUNC register controls
> ADMA length mismatch error interrupt. Enable it by default.
>
> And update all bit shift defines with BIT macro.
>
> Signed-off-by: Veerabhadrarao Badiganti <[email protected]>
> ---
> drivers/mmc/host/sdhci-msm.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
> index 482045b..660e1bc 100644
> --- a/drivers/mmc/host/sdhci-msm.c
> +++ b/drivers/mmc/host/sdhci-msm.c
> @@ -56,19 +56,19 @@
> #define CORE_FLL_CYCLE_CNT BIT(18)
> #define CORE_DLL_CLOCK_DISABLE BIT(21)
>
> -#define CORE_VENDOR_SPEC_POR_VAL 0xa1c
> +#define CORE_VENDOR_SPEC_POR_VAL 0xa3c
Sorry . This should be 0xa9c, not 0xa3c. Correcting it.
> #define CORE_CLK_PWRSAVE BIT(1)
> #define CORE_HC_MCLK_SEL_DFLT (2 << 8)
> #define CORE_HC_MCLK_SEL_HS400 (3 << 8)
> #define CORE_HC_MCLK_SEL_MASK (3 << 8)
> -#define CORE_IO_PAD_PWR_SWITCH_EN (1 << 15)
> -#define CORE_IO_PAD_PWR_SWITCH (1 << 16)
> +#define CORE_IO_PAD_PWR_SWITCH_EN BIT(15)
> +#define CORE_IO_PAD_PWR_SWITCH BIT(16)
> #define CORE_HC_SELECT_IN_EN BIT(18)
> #define CORE_HC_SELECT_IN_HS400 (6 << 19)
> #define CORE_HC_SELECT_IN_MASK (7 << 19)
>
> -#define CORE_3_0V_SUPPORT (1 << 25)
> -#define CORE_1_8V_SUPPORT (1 << 26)
> +#define CORE_3_0V_SUPPORT BIT(25)
> +#define CORE_1_8V_SUPPORT BIT(26)
> #define CORE_VOLT_SUPPORT (CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT)
>
> #define CORE_CSR_CDC_CTLR_CFG0 0x130

2020-04-12 17:10:57

by Veerabhadrarao Badiganti

Subject: [PATCH V1] mmc: sdhci-msm: Enable ADMA length mismatch error interrupt

ADMA_ERR_SIZE_EN bit of VENDOR_SPECIFIC_FUNC register controls
ADMA length mismatch error interrupt. Enable it by default.

And update all bit shift defines with BIT macro.

Signed-off-by: Veerabhadrarao Badiganti <[email protected]>
---
drivers/mmc/host/sdhci-msm.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index 482045b..7d744f9 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -56,19 +56,19 @@
#define CORE_FLL_CYCLE_CNT BIT(18)
#define CORE_DLL_CLOCK_DISABLE BIT(21)

-#define CORE_VENDOR_SPEC_POR_VAL 0xa1c
+#define CORE_VENDOR_SPEC_POR_VAL 0xa9c
#define CORE_CLK_PWRSAVE BIT(1)
#define CORE_HC_MCLK_SEL_DFLT (2 << 8)
#define CORE_HC_MCLK_SEL_HS400 (3 << 8)
#define CORE_HC_MCLK_SEL_MASK (3 << 8)
-#define CORE_IO_PAD_PWR_SWITCH_EN (1 << 15)
-#define CORE_IO_PAD_PWR_SWITCH (1 << 16)
+#define CORE_IO_PAD_PWR_SWITCH_EN BIT(15)
+#define CORE_IO_PAD_PWR_SWITCH BIT(16)
#define CORE_HC_SELECT_IN_EN BIT(18)
#define CORE_HC_SELECT_IN_HS400 (6 << 19)
#define CORE_HC_SELECT_IN_MASK (7 << 19)

-#define CORE_3_0V_SUPPORT (1 << 25)
-#define CORE_1_8V_SUPPORT (1 << 26)
+#define CORE_3_0V_SUPPORT BIT(25)
+#define CORE_1_8V_SUPPORT BIT(26)
#define CORE_VOLT_SUPPORT (CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT)

#define CORE_CSR_CDC_CTLR_CFG0 0x130
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation Center, Inc., is a member of Code Aurora Forum, a Linux Foundation Collaborative Project

2020-04-16 10:08:12

by Adrian Hunter

Subject: Re: [PATCH V1 3/4] mmc: sdhci-msm: Set SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 quirk

On 12/04/20 6:53 pm, Veerabhadrarao Badiganti wrote:
> sdhci-msm can support auto cmd12.
> So enable SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 quirk.
>
> Signed-off-by: Veerabhadrarao Badiganti <[email protected]>

Acked-by: Adrian Hunter <[email protected]>

> ---
> drivers/mmc/host/sdhci-msm.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
> index d826e9b..482045b 100644
> --- a/drivers/mmc/host/sdhci-msm.c
> +++ b/drivers/mmc/host/sdhci-msm.c
> @@ -1882,7 +1882,9 @@ static void sdhci_msm_reset(struct sdhci_host *host, u8 mask)
> static const struct sdhci_pltfm_data sdhci_msm_pdata = {
> .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
> SDHCI_QUIRK_SINGLE_POWER_WRITE |
> - SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
> + SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
> + SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
> +
> .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
> .ops = &sdhci_msm_ops,
> };
>

2020-04-16 10:11:40

by Adrian Hunter

Subject: Re: [PATCH V1] mmc: sdhci-msm: Enable ADMA length mismatch error interrupt

On 12/04/20 8:07 pm, Veerabhadrarao Badiganti wrote:
> ADMA_ERR_SIZE_EN bit of VENDOR_SPECIFIC_FUNC register controls
> ADMA length mismatch error interrupt. Enable it by default.
>
> And update all bit shift defines with BIT macro.
>
> Signed-off-by: Veerabhadrarao Badiganti <[email protected]>

Acked-by: Adrian Hunter <[email protected]>

> ---
> drivers/mmc/host/sdhci-msm.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
> index 482045b..7d744f9 100644
> --- a/drivers/mmc/host/sdhci-msm.c
> +++ b/drivers/mmc/host/sdhci-msm.c
> @@ -56,19 +56,19 @@
> #define CORE_FLL_CYCLE_CNT BIT(18)
> #define CORE_DLL_CLOCK_DISABLE BIT(21)
>
> -#define CORE_VENDOR_SPEC_POR_VAL 0xa1c
> +#define CORE_VENDOR_SPEC_POR_VAL 0xa9c
> #define CORE_CLK_PWRSAVE BIT(1)
> #define CORE_HC_MCLK_SEL_DFLT (2 << 8)
> #define CORE_HC_MCLK_SEL_HS400 (3 << 8)
> #define CORE_HC_MCLK_SEL_MASK (3 << 8)
> -#define CORE_IO_PAD_PWR_SWITCH_EN (1 << 15)
> -#define CORE_IO_PAD_PWR_SWITCH (1 << 16)
> +#define CORE_IO_PAD_PWR_SWITCH_EN BIT(15)
> +#define CORE_IO_PAD_PWR_SWITCH BIT(16)
> #define CORE_HC_SELECT_IN_EN BIT(18)
> #define CORE_HC_SELECT_IN_HS400 (6 << 19)
> #define CORE_HC_SELECT_IN_MASK (7 << 19)
>
> -#define CORE_3_0V_SUPPORT (1 << 25)
> -#define CORE_1_8V_SUPPORT (1 << 26)
> +#define CORE_3_0V_SUPPORT BIT(25)
> +#define CORE_1_8V_SUPPORT BIT(26)
> #define CORE_VOLT_SUPPORT (CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT)
>
> #define CORE_CSR_CDC_CTLR_CFG0 0x130
>