[v3]
* Update the clock-name to iface instead of gcc_lpass_sway.
* Update the documentation with the reg descriptions and use maxItems.
[v2]
* Update retention macro name.
* Update the register description in the documentation.
[v1]
* Add support for Retention of GDSCR.
* Add YAML schema for LPASS clocks and clock IDs for LPASS.
* Add clock driver for LPASS core clocks and GCC LPASS clock.
Taniya Das (4):
clk: qcom: gdsc: Add support to enable retention of GSDCR
dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7180
clk: qcom: gcc: Add support for GCC LPASS clock for SC7180
clk: qcom: lpass: Add support for LPASS clock controller for SC7180
.../bindings/clock/qcom,sc7180-lpasscorecc.yaml | 98 +++++
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-sc7180.c | 14 +
drivers/clk/qcom/gdsc.c | 12 +
drivers/clk/qcom/gdsc.h | 1 +
drivers/clk/qcom/lpasscorecc-sc7180.c | 478 +++++++++++++++++++++
include/dt-bindings/clock/qcom,gcc-sc7180.h | 1 +
.../dt-bindings/clock/qcom,lpasscorecc-sc7180.h | 29 ++
9 files changed, 643 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7180-lpasscorecc.yaml
create mode 100644 drivers/clk/qcom/lpasscorecc-sc7180.c
create mode 100644 include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the Linux Foundation.
Add the GCC lpass clock which is required to access the LPASS core
clocks.
Signed-off-by: Taniya Das <[email protected]>
---
drivers/clk/qcom/gcc-sc7180.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c
index ca4383e..8d3b161 100644
--- a/drivers/clk/qcom/gcc-sc7180.c
+++ b/drivers/clk/qcom/gcc-sc7180.c
@@ -2251,6 +2251,19 @@ static struct clk_branch gcc_mss_q6_memnoc_axi_clk = {
},
};
+static struct clk_branch gcc_lpass_cfg_noc_sway_clk = {
+ .halt_reg = 0x47018,
+ .halt_check = BRANCH_HALT_DELAY,
+ .clkr = {
+ .enable_reg = 0x47018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_lpass_cfg_noc_sway_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct gdsc ufs_phy_gdsc = {
.gdscr = 0x77004,
.pd = {
@@ -2428,6 +2441,7 @@ static struct clk_regmap *gcc_sc7180_clocks[] = {
[GCC_MSS_Q6_MEMNOC_AXI_CLK] = &gcc_mss_q6_memnoc_axi_clk.clkr,
[GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
[GCC_SEC_CTRL_CLK_SRC] = &gcc_sec_ctrl_clk_src.clkr,
+ [GCC_LPASS_CFG_NOC_SWAY_CLK] = &gcc_lpass_cfg_noc_sway_clk.clkr,
};
static const struct qcom_reset_map gcc_sc7180_resets[] = {
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the Linux Foundation.
Add support for the RETAIN_FF_ENABLE feature which enables the
usage of retention registers. These registers maintain their
state after disabling and re-enabling a GDSC.
Signed-off-by: Taniya Das <[email protected]>
---
drivers/clk/qcom/gdsc.c | 12 ++++++++++++
drivers/clk/qcom/gdsc.h | 1 +
2 files changed, 13 insertions(+)
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index 04944f1..2502430 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -29,6 +29,7 @@
/* CFG_GDSCR */
#define GDSC_POWER_UP_COMPLETE BIT(16)
#define GDSC_POWER_DOWN_COMPLETE BIT(15)
+#define GDSC_RETAIN_FF_ENABLE BIT(11)
#define CFG_GDSCR_OFFSET 0x4
/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
@@ -216,6 +217,14 @@ static inline void gdsc_assert_reset_aon(struct gdsc *sc)
regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
GMEM_RESET_MASK, 0);
}
+
+static void gdsc_retain_ff_on(struct gdsc *sc)
+{
+ u32 mask = GDSC_RETAIN_FF_ENABLE;
+
+ regmap_update_bits(sc->regmap, sc->gdscr, mask, mask);
+}
+
static int gdsc_enable(struct generic_pm_domain *domain)
{
struct gdsc *sc = domain_to_gdsc(domain);
@@ -268,6 +277,9 @@ static int gdsc_enable(struct generic_pm_domain *domain)
udelay(1);
}
+ if (sc->flags & RETAIN_FF_ENABLE)
+ gdsc_retain_ff_on(sc);
+
return 0;
}
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
index c36fc26..a5076fe 100644
--- a/drivers/clk/qcom/gdsc.h
+++ b/drivers/clk/qcom/gdsc.h
@@ -50,6 +50,7 @@ struct gdsc {
#define AON_RESET BIT(4)
#define POLL_CFG_GDSCR BIT(5)
#define ALWAYS_ON BIT(6)
+#define RETAIN_FF_ENABLE BIT(7)
struct reset_controller_dev *rcdev;
unsigned int *resets;
unsigned int reset_count;
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the Linux Foundation.
Quoting Taniya Das (2020-06-10 10:18:03)
> [v3]
> * Update the clock-name to iface instead of gcc_lpass_sway.
> * Update the documentation with the reg descriptions and use maxItems.
>
Most patches look good minus Rob's DT binding comment. Can you resend?