Greg suggested that we move the driver
to the clk from the staging.
Add patches to address the concerns regarding the fractional and
set rate support in the TODO.
The patch set does the following
- Trivial fixes for kernel doc.
- Move the driver to the clk folder
- Add capability to set rate.
- Add fractional support.
- Add support for configurable outputs.
Changes in the v3:
Added the cover-letter.
Add patches for rate setting and fractional support
Add patches for warning.
Remove the driver from staging as suggested
v4:
Reorder the patches.
Merge the CLK_IS_BASIC patch.
Add the yaml form of binding document
v5:
Fix a mismerge
Shubhrajyoti Datta (8):
dt-bindings: add documentation of xilinx clocking wizard
clk: clock-wizard: Add the clockwizard to clk directory
clk: clock-wizard: Fix kernel-doc warning
clk: clock-wizard: Add support for dynamic reconfiguration
clk: clock-wizard: Add support for fractional support
clk: clock-wizard: Remove the hardcoding of the clock outputs
clk: clock-wizard: Update the fixed factor divisors
staging: clocking-wizard: Delete the driver from the staging
.../bindings/clock/xlnx,clocking-wizard.yaml | 71 +++
drivers/clk/Kconfig | 9 +
drivers/clk/Makefile | 1 +
drivers/clk/clk-xlnx-clock-wizard.c | 710 +++++++++++++++++++++
drivers/staging/Kconfig | 2 -
drivers/staging/Makefile | 1 -
drivers/staging/clocking-wizard/Kconfig | 10 -
drivers/staging/clocking-wizard/Makefile | 2 -
drivers/staging/clocking-wizard/TODO | 12 -
.../clocking-wizard/clk-xlnx-clock-wizard.c | 333 ----------
drivers/staging/clocking-wizard/dt-binding.txt | 30 -
11 files changed, 791 insertions(+), 390 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
create mode 100644 drivers/clk/clk-xlnx-clock-wizard.c
delete mode 100644 drivers/staging/clocking-wizard/Kconfig
delete mode 100644 drivers/staging/clocking-wizard/Makefile
delete mode 100644 drivers/staging/clocking-wizard/TODO
delete mode 100644 drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
delete mode 100644 drivers/staging/clocking-wizard/dt-binding.txt
--
2.1.1
Add the devicetree binding for the xilinx clocking wizard.
Signed-off-by: Shubhrajyoti Datta <[email protected]>
---
v4:
change to yaml format
.../bindings/clock/xlnx,clocking-wizard.yaml | 71 ++++++++++++++++++++++
1 file changed, 71 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
new file mode 100644
index 0000000..5a8e991
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/xlnx,clocking-wiz.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx clocking wizard
+
+maintainers:
+ - Shubhrajyoti Datta <[email protected]>
+
+description: |
+ The clocking wizard is a soft ip clocking block of Xilinx versal. It
+ reads required input clock frequencies from the devicetree and acts as clock
+ clock output.
+
+select: false
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - xlnx,clocking-wizard
+ - xlnx,clocking-wizard-6.0
+
+ "#clock-cells":
+ const: 1
+
+ clocks:
+ description: List of clock specifiers which are external input
+ clocks to the given clock controller.
+ items:
+ - description: clock input
+ - description: axi clock
+
+ clock-names:
+ items:
+ - const: clk_in1
+ - const: s_axi_aclk
+
+ speed-grade:
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [1, 2, 3]
+ description:
+ Speed grade of the device.
+ maxItems: 1
+
+required:
+ - compatible
+ - "#clock-cells"
+ - clocks
+ - clock-names
+ - speed-grade
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-generator@40040000 {
+ #clock-cells = <1>;
+ reg = <0x40040000 0x1000>;
+ compatible = "xlnx,clk-wizard-1.0";
+ speed-grade = <1>;
+ clock-names = "clk_in1", "s_axi_aclk";
+ clocks = <&clkc 15>, <&clkc 15>;
+ clock-output-names = "clk_out1", "clk_out2",
+ "clk_out3", "clk_out4", "clk_out5",
+ "clk_out6", "clk_out7";
+ };
+...
--
2.1.1
On Fri, 26 Jun 2020 23:26:18 +0530, Shubhrajyoti Datta wrote:
> Add the devicetree binding for the xilinx clocking wizard.
>
> Signed-off-by: Shubhrajyoti Datta <[email protected]>
> ---
> v4:
> change to yaml format
>
> .../bindings/clock/xlnx,clocking-wizard.yaml | 71 ++++++++++++++++++++++
> 1 file changed, 71 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml: $id: relative path/filename doesn't match actual path or filename
expected: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#
See https://patchwork.ozlabs.org/patch/1317919
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure dt-schema is up to date:
pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade
Please check and re-submit.