This series adds supports for firmware specific flags. These include
- Common Flags
- Divider Flags
- Mux Flags
The intent is to remove firmware's dependency on CCF flag values by
having firmware specific flags with independent values.
Rajan Vaja (3):
clk: zynqmp: Use firmware specific common clock flags
clk: zynqmp: Use firmware specific divider clock flags
clk: zynqmp: Use firmware specific mux clock flags
drivers/clk/zynqmp/clk-mux-zynqmp.c | 14 ++++++++++++-
drivers/clk/zynqmp/clk-zynqmp.h | 39 +++++++++++++++++++++++++++++++++++++
drivers/clk/zynqmp/clkc.c | 25 ++++++++++++++++++++++--
drivers/clk/zynqmp/divider.c | 16 ++++++++++++++-
4 files changed, 90 insertions(+), 4 deletions(-)
--
2.7.4
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From: Rajan Vaja <[email protected]>
Use ZynqMP specific divider clock flags instead of using CCF flags.
Signed-off-by: Rajan Vaja <[email protected]>
Signed-off-by: Amit Sunil Dhamne <[email protected]>
---
drivers/clk/zynqmp/clk-zynqmp.h | 9 +++++++++
drivers/clk/zynqmp/divider.c | 16 +++++++++++++++-
2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqmp.h
index d8e580b..ade5e9e 100644
--- a/drivers/clk/zynqmp/clk-zynqmp.h
+++ b/drivers/clk/zynqmp/clk-zynqmp.h
@@ -32,6 +32,15 @@
/* do not gate, ever */
#define ZYNQMP_CLK_IS_CRITICAL BIT(11)
+/* Type Flags for divider clock */
+#define ZYNQMP_CLK_DIVIDER_ONE_BASED BIT(0)
+#define ZYNQMP_CLK_DIVIDER_POWER_OF_TWO BIT(1)
+#define ZYNQMP_CLK_DIVIDER_ALLOW_ZERO BIT(2)
+#define ZYNQMP_CLK_DIVIDER_HIWORD_MASK BIT(3)
+#define ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST BIT(4)
+#define ZYNQMP_CLK_DIVIDER_READ_ONLY BIT(5)
+#define ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO BIT(6)
+
enum topology_type {
TYPE_INVALID,
TYPE_MUX,
diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
index 66da02b..f15d6b7 100644
--- a/drivers/clk/zynqmp/divider.c
+++ b/drivers/clk/zynqmp/divider.c
@@ -319,7 +319,21 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name,
/* struct clk_divider assignments */
div->is_frac = !!((nodes->flag & CLK_FRAC) |
(nodes->custom_type_flag & CUSTOM_FLAG_CLK_FRAC));
- div->flags = nodes->type_flag;
+ div->flags = 0;
+ div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_ONE_BASED) ?
+ CLK_DIVIDER_ONE_BASED : 0;
+ div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO) ?
+ CLK_DIVIDER_POWER_OF_TWO : 0;
+ div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_ALLOW_ZERO) ?
+ CLK_DIVIDER_ALLOW_ZERO : 0;
+ div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_POWER_OF_TWO) ?
+ CLK_DIVIDER_HIWORD_MASK : 0;
+ div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_ROUND_CLOSEST) ?
+ CLK_DIVIDER_ROUND_CLOSEST : 0;
+ div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_READ_ONLY) ?
+ CLK_DIVIDER_READ_ONLY : 0;
+ div->flags |= (nodes->type_flag & ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO) ?
+ CLK_DIVIDER_MAX_AT_ZERO : 0;
div->hw.init = &init;
div->clk_id = clk_id;
div->div_type = nodes->type;
--
2.7.4
This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately.
From: Rajan Vaja <[email protected]>
Use ZynqMP specific mux clock flags instead of using CCF flags.
Signed-off-by: Rajan Vaja <[email protected]>
Signed-off-by: Amit Sunil Dhamne <[email protected]>
---
drivers/clk/zynqmp/clk-mux-zynqmp.c | 14 +++++++++++++-
drivers/clk/zynqmp/clk-zynqmp.h | 8 ++++++++
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/zynqmp/clk-mux-zynqmp.c b/drivers/clk/zynqmp/clk-mux-zynqmp.c
index 0619414..9e365e7 100644
--- a/drivers/clk/zynqmp/clk-mux-zynqmp.c
+++ b/drivers/clk/zynqmp/clk-mux-zynqmp.c
@@ -123,7 +123,19 @@ struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,
init.flags = nodes->flag;
init.parent_names = parents;
init.num_parents = num_parents;
- mux->flags = nodes->type_flag;
+ mux->flags = 0;
+ mux->flags |= (nodes->type_flag & ZYNQMP_CLK_MUX_INDEX_ONE) ?
+ CLK_MUX_INDEX_ONE : 0;
+ mux->flags |= (nodes->type_flag & ZYNQMP_CLK_MUX_INDEX_BIT) ?
+ CLK_MUX_INDEX_BIT : 0;
+ mux->flags |= (nodes->type_flag & ZYNQMP_CLK_MUX_HIWORD_MASK) ?
+ CLK_MUX_HIWORD_MASK : 0;
+ mux->flags |= (nodes->type_flag & ZYNQMP_CLK_MUX_READ_ONLY) ?
+ CLK_MUX_READ_ONLY : 0;
+ mux->flags |= (nodes->type_flag & ZYNQMP_CLK_MUX_ROUND_CLOSEST) ?
+ CLK_MUX_ROUND_CLOSEST : 0;
+ mux->flags |= (nodes->type_flag & ZYNQMP_CLK_MUX_BIG_ENDIAN) ?
+ CLK_MUX_BIG_ENDIAN : 0;
mux->hw.init = &init;
mux->clk_id = clk_id;
diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqmp.h
index ade5e9e..a29ab43 100644
--- a/drivers/clk/zynqmp/clk-zynqmp.h
+++ b/drivers/clk/zynqmp/clk-zynqmp.h
@@ -41,6 +41,14 @@
#define ZYNQMP_CLK_DIVIDER_READ_ONLY BIT(5)
#define ZYNQMP_CLK_DIVIDER_MAX_AT_ZERO BIT(6)
+/* Type Flags for mux clock */
+#define ZYNQMP_CLK_MUX_INDEX_ONE BIT(0)
+#define ZYNQMP_CLK_MUX_INDEX_BIT BIT(1)
+#define ZYNQMP_CLK_MUX_HIWORD_MASK BIT(2)
+#define ZYNQMP_CLK_MUX_READ_ONLY BIT(3)
+#define ZYNQMP_CLK_MUX_ROUND_CLOSEST BIT(4)
+#define ZYNQMP_CLK_MUX_BIG_ENDIAN BIT(5)
+
enum topology_type {
TYPE_INVALID,
TYPE_MUX,
--
2.7.4
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