From: Andy Teng <[email protected]>
Add devicetree bindings for MediaTek MT6779 pinctrl driver.
Signed-off-by: Andy Teng <[email protected]>
---
.../bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 210 ++++++++++++++++++++
1 file changed, 210 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
new file mode 100644
index 0000000..3a9fc4d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
@@ -0,0 +1,210 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek MT6779 Pin Controller Device Tree Bindings
+
+maintainers:
+ - Andy Teng <[email protected]>
+
+description: |+
+ The pin controller node should be the child of a syscon node with the
+ required property:
+ - compatible: "syscon"
+
+properties:
+ compatible:
+ const: mediatek,mt6779-pinctrl
+
+ reg:
+ minItems: 9
+ maxItems: 9
+ description: |
+ physical address base for gpio-related control registers.
+
+ reg-names:
+ description: |
+ GPIO base register names. The names are "gpio", "iocfg_rm",
+ "iocfg_br", "iocfg_lm", "iocfg_lb", "iocfg_rt", "iocfg_lt",
+ "iocfg_tl", "eint";
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ const: 2
+ description: |
+ Number of cells in GPIO specifier. Since the generic GPIO
+ binding is used, the amount of cells must be specified as 2. See the below
+ mentioned gpio binding representation for description of particular cells.
+
+ gpio-ranges:
+ minItems: 1
+ maxItems: 5
+ description: |
+ GPIO valid number range.
+
+ interrupt-controller: true
+
+ interrupts:
+ maxItems: 1
+ description: |
+ Specifies the summary IRQ.
+
+ "#interrupt-cells":
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - gpio-controller
+ - "#gpio-cells"
+ - gpio-ranges
+ - interrupt-controller
+ - interrupts
+ - "#interrupt-cells"
+
+patternProperties:
+ '-[0-9]*$':
+ type: object
+ patternProperties:
+ '-pins*$':
+ type: object
+ description: |
+ A pinctrl node should contain at least one subnodes representing the
+ pinctrl groups available on the machine. Each subnode will list the
+ pins it needs, and how they should be configured, with regard to muxer
+ configuration, pullups, drive strength, input enable/disable and input schmitt.
+
+ properties:
+ pinmux:
+ description:
+ integer array, represents gpio pin number and mux setting.
+ Supported pin number and mux varies for different SoCs, and are defined
+ as macros in boot/dts/<soc>-pinfunc.h directly.
+
+ bias-disable:
+ type: boolean
+
+ bias-pull-up:
+ type: boolean
+
+ bias-pull-down:
+ type: boolean
+
+ input-enable:
+ type: boolean
+
+ input-disable:
+ type: boolean
+
+ output-low:
+ type: boolean
+
+ output-high:
+ type: boolean
+
+ input-schmitt-enable:
+ type: boolean
+
+ input-schmitt-disable:
+ type: boolean
+
+ mediatek,pull-up-adv:
+ description: |
+ Pull up setings for 2 pull resistors, R0 and R1. User can
+ configure those special pins. Valid arguments are described as below:
+ 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
+ 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
+ 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
+ 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [0, 1, 2, 3]
+
+ mediatek,pull-down-adv:
+ description: |
+ Pull down settings for 2 pull resistors, R0 and R1. User can
+ configure those special pins. Valid arguments are described as below:
+ 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
+ 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
+ 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
+ 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [0, 1, 2, 3]
+
+ drive-strength:
+ description: |
+ Selects the drive strength for the specified pins in mA.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [2, 4, 6, 8, 10, 12, 14, 16]
+
+ required:
+ - pinmux
+
+ additionalProperties: false
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/pinctrl/mt6779-pinfunc.h>
+
+ pio: pinctrl@10005000 {
+ compatible = "mediatek,mt6779-pinctrl";
+ reg = <0 0x10005000 0 0x1000>,
+ <0 0x11c20000 0 0x1000>,
+ <0 0x11d10000 0 0x1000>,
+ <0 0x11e20000 0 0x1000>,
+ <0 0x11e70000 0 0x1000>,
+ <0 0x11ea0000 0 0x1000>,
+ <0 0x11f20000 0 0x1000>,
+ <0 0x11f30000 0 0x1000>,
+ <0 0x1000b000 0 0x1000>;
+ reg-names = "gpio", "iocfg_rm",
+ "iocfg_br", "iocfg_lm",
+ "iocfg_lb", "iocfg_rt",
+ "iocfg_lt", "iocfg_tl",
+ "eint";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pio 0 0 210>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
+
+ mmc0_pins_default: mmc0-0 {
+ cmd-dat-pins {
+ pinmux = <PINMUX_GPIO168__FUNC_MSDC0_DAT0>,
+ <PINMUX_GPIO172__FUNC_MSDC0_DAT1>,
+ <PINMUX_GPIO169__FUNC_MSDC0_DAT2>,
+ <PINMUX_GPIO177__FUNC_MSDC0_DAT3>,
+ <PINMUX_GPIO170__FUNC_MSDC0_DAT4>,
+ <PINMUX_GPIO173__FUNC_MSDC0_DAT5>,
+ <PINMUX_GPIO171__FUNC_MSDC0_DAT6>,
+ <PINMUX_GPIO174__FUNC_MSDC0_DAT7>,
+ <PINMUX_GPIO167__FUNC_MSDC0_CMD>;
+ input-enable;
+ mediatek,pull-up-adv = <1>;
+ };
+ clk-pins {
+ pinmux = <PINMUX_GPIO176__FUNC_MSDC0_CLK>;
+ mediatek,pull-down-adv = <2>;
+ };
+ rst-pins {
+ pinmux = <PINMUX_GPIO178__FUNC_MSDC0_RSTB>;
+ mediatek,pull-up-adv = <0>;
+ };
+ };
+ };
+
+ mmc0 {
+ pinctrl-0 = <&mmc0_pins_default>;
+ pinctrl-names = "default";
+ };
--
1.7.9.5
On Thu, Jul 02, 2020 at 08:57:05PM +0800, Hanks Chen wrote:
> From: Andy Teng <[email protected]>
>
> Add devicetree bindings for MediaTek MT6779 pinctrl driver.
>
> Signed-off-by: Andy Teng <[email protected]>
> ---
> .../bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 210 ++++++++++++++++++++
> 1 file changed, 210 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
> new file mode 100644
> index 0000000..3a9fc4d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
> @@ -0,0 +1,210 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek MT6779 Pin Controller Device Tree Bindings
> +
> +maintainers:
> + - Andy Teng <[email protected]>
> +
> +description: |+
> + The pin controller node should be the child of a syscon node with the
> + required property:
> + - compatible: "syscon"
> +
> +properties:
> + compatible:
> + const: mediatek,mt6779-pinctrl
> +
> + reg:
> + minItems: 9
> + maxItems: 9
> + description: |
> + physical address base for gpio-related control registers.
Need to describe what each entry is.
items:
- description: ...
- description: ...
- description: ...
> +
> + reg-names:
> + description: |
> + GPIO base register names. The names are "gpio", "iocfg_rm",
> + "iocfg_br", "iocfg_lm", "iocfg_lb", "iocfg_rt", "iocfg_lt",
> + "iocfg_tl", "eint";
The names should be a schema.
> +
> + gpio-controller: true
> +
> + "#gpio-cells":
> + const: 2
> + description: |
> + Number of cells in GPIO specifier. Since the generic GPIO
> + binding is used, the amount of cells must be specified as 2. See the below
> + mentioned gpio binding representation for description of particular cells.
> +
> + gpio-ranges:
> + minItems: 1
> + maxItems: 5
> + description: |
> + GPIO valid number range.
> +
> + interrupt-controller: true
> +
> + interrupts:
> + maxItems: 1
> + description: |
> + Specifies the summary IRQ.
> +
> + "#interrupt-cells":
> + const: 2
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - gpio-controller
> + - "#gpio-cells"
> + - gpio-ranges
> + - interrupt-controller
> + - interrupts
> + - "#interrupt-cells"
> +
> +patternProperties:
> + '-[0-9]*$':
> + type: object
> + patternProperties:
> + '-pins*$':
> + type: object
> + description: |
> + A pinctrl node should contain at least one subnodes representing the
> + pinctrl groups available on the machine. Each subnode will list the
> + pins it needs, and how they should be configured, with regard to muxer
> + configuration, pullups, drive strength, input enable/disable and input schmitt.
Need to include the pinconf schema here.
> +
> + properties:
> + pinmux:
> + description:
> + integer array, represents gpio pin number and mux setting.
> + Supported pin number and mux varies for different SoCs, and are defined
> + as macros in boot/dts/<soc>-pinfunc.h directly.
> +
> + bias-disable:
> + type: boolean
Don't redefine the type. Just indicate what common properties are used:
bias-disable: true
> +
> + bias-pull-up:
> + type: boolean
> +
> + bias-pull-down:
> + type: boolean
> +
> + input-enable:
> + type: boolean
> +
> + input-disable:
> + type: boolean
> +
> + output-low:
> + type: boolean
> +
> + output-high:
> + type: boolean
> +
> + input-schmitt-enable:
> + type: boolean
> +
> + input-schmitt-disable:
> + type: boolean
> +
> + mediatek,pull-up-adv:
> + description: |
> + Pull up setings for 2 pull resistors, R0 and R1. User can
> + configure those special pins. Valid arguments are described as below:
> + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
> + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
> + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
> + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
> + allOf:
You can drop the allOf now.
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - enum: [0, 1, 2, 3]
> +
> + mediatek,pull-down-adv:
> + description: |
> + Pull down settings for 2 pull resistors, R0 and R1. User can
> + configure those special pins. Valid arguments are described as below:
> + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
> + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
> + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
> + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - enum: [0, 1, 2, 3]
> +
> + drive-strength:
> + description: |
> + Selects the drive strength for the specified pins in mA.
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - enum: [2, 4, 6, 8, 10, 12, 14, 16]
> +
> + required:
> + - pinmux
> +
> + additionalProperties: false
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/pinctrl/mt6779-pinfunc.h>
> +
> + pio: pinctrl@10005000 {
> + compatible = "mediatek,mt6779-pinctrl";
> + reg = <0 0x10005000 0 0x1000>,
> + <0 0x11c20000 0 0x1000>,
> + <0 0x11d10000 0 0x1000>,
> + <0 0x11e20000 0 0x1000>,
> + <0 0x11e70000 0 0x1000>,
> + <0 0x11ea0000 0 0x1000>,
> + <0 0x11f20000 0 0x1000>,
> + <0 0x11f30000 0 0x1000>,
> + <0 0x1000b000 0 0x1000>;
> + reg-names = "gpio", "iocfg_rm",
> + "iocfg_br", "iocfg_lm",
> + "iocfg_lb", "iocfg_rt",
> + "iocfg_lt", "iocfg_tl",
> + "eint";
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&pio 0 0 210>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
> +
> + mmc0_pins_default: mmc0-0 {
> + cmd-dat-pins {
> + pinmux = <PINMUX_GPIO168__FUNC_MSDC0_DAT0>,
> + <PINMUX_GPIO172__FUNC_MSDC0_DAT1>,
> + <PINMUX_GPIO169__FUNC_MSDC0_DAT2>,
> + <PINMUX_GPIO177__FUNC_MSDC0_DAT3>,
> + <PINMUX_GPIO170__FUNC_MSDC0_DAT4>,
> + <PINMUX_GPIO173__FUNC_MSDC0_DAT5>,
> + <PINMUX_GPIO171__FUNC_MSDC0_DAT6>,
> + <PINMUX_GPIO174__FUNC_MSDC0_DAT7>,
> + <PINMUX_GPIO167__FUNC_MSDC0_CMD>;
> + input-enable;
> + mediatek,pull-up-adv = <1>;
> + };
> + clk-pins {
> + pinmux = <PINMUX_GPIO176__FUNC_MSDC0_CLK>;
> + mediatek,pull-down-adv = <2>;
> + };
> + rst-pins {
> + pinmux = <PINMUX_GPIO178__FUNC_MSDC0_RSTB>;
> + mediatek,pull-up-adv = <0>;
> + };
> + };
> + };
> +
> + mmc0 {
> + pinctrl-0 = <&mmc0_pins_default>;
> + pinctrl-names = "default";
> + };
> --
> 1.7.9.5
On Thu, 2020-07-02 at 14:58 -0600, Rob Herring wrote:
> On Thu, Jul 02, 2020 at 08:57:05PM +0800, Hanks Chen wrote:
> > From: Andy Teng <[email protected]>
> >
> > Add devicetree bindings for MediaTek MT6779 pinctrl driver.
> >
> > Signed-off-by: Andy Teng <[email protected]>
> > ---
> > .../bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 210 ++++++++++++++++++++
> > 1 file changed, 210 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
> > new file mode 100644
> > index 0000000..3a9fc4d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
> > @@ -0,0 +1,210 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml*__;Iw!!CTRNKA9wMg0ARbw!0474C4nwnSzS27r76why4qthf5712hrWflC57fdhSU7LzHZYpD7W0t5ZhJBgmnpF-A$
> > +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!0474C4nwnSzS27r76why4qthf5712hrWflC57fdhSU7LzHZYpD7W0t5ZhJAzv-fiRw$
> > +
> > +title: Mediatek MT6779 Pin Controller Device Tree Bindings
> > +
> > +maintainers:
> > + - Andy Teng <[email protected]>
> > +
> > +description: |+
> > + The pin controller node should be the child of a syscon node with the
> > + required property:
> > + - compatible: "syscon"
> > +
> > +properties:
> > + compatible:
> > + const: mediatek,mt6779-pinctrl
> > +
> > + reg:
> > + minItems: 9
> > + maxItems: 9
> > + description: |
> > + physical address base for gpio-related control registers.
>
> Need to describe what each entry is.
>
> items:
> - description: ...
> - description: ...
> - description: ...
>
Got it, I'll add description in next version.
Thanks!
> > +
> > + reg-names:
> > + description: |
> > + GPIO base register names. The names are "gpio", "iocfg_rm",
> > + "iocfg_br", "iocfg_lm", "iocfg_lb", "iocfg_rt", "iocfg_lt",
> > + "iocfg_tl", "eint";
>
> The names should be a schema.
>
Got it, I'll fix it.
>
> > +
> > + gpio-controller: true
> > +
> > + "#gpio-cells":
> > + const: 2
> > + description: |
> > + Number of cells in GPIO specifier. Since the generic GPIO
> > + binding is used, the amount of cells must be specified as 2. See the below
> > + mentioned gpio binding representation for description of particular cells.
> > +
> > + gpio-ranges:
> > + minItems: 1
> > + maxItems: 5
> > + description: |
> > + GPIO valid number range.
> > +
> > + interrupt-controller: true
> > +
> > + interrupts:
> > + maxItems: 1
> > + description: |
> > + Specifies the summary IRQ.
> > +
> > + "#interrupt-cells":
> > + const: 2
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - reg-names
> > + - gpio-controller
> > + - "#gpio-cells"
> > + - gpio-ranges
> > + - interrupt-controller
> > + - interrupts
> > + - "#interrupt-cells"
> > +
> > +patternProperties:
> > + '-[0-9]*$':
> > + type: object
> > + patternProperties:
> > + '-pins*$':
> > + type: object
> > + description: |
> > + A pinctrl node should contain at least one subnodes representing the
> > + pinctrl groups available on the machine. Each subnode will list the
> > + pins it needs, and how they should be configured, with regard to muxer
> > + configuration, pullups, drive strength, input enable/disable and input schmitt.
>
> Need to include the pinconf schema here.
Got it, I'll add it in next version.
>
> > +
> > + properties:
> > + pinmux:
> > + description:
> > + integer array, represents gpio pin number and mux setting.
> > + Supported pin number and mux varies for different SoCs, and are defined
> > + as macros in boot/dts/<soc>-pinfunc.h directly.
> > +
> > + bias-disable:
> > + type: boolean
>
> Don't redefine the type. Just indicate what common properties are used:
>
> bias-disable: true
Got it, I'll fix it in next version.
>
> > +
> > + bias-pull-up:
> > + type: boolean
> > +
> > + bias-pull-down:
> > + type: boolean
> > +
> > + input-enable:
> > + type: boolean
> > +
> > + input-disable:
> > + type: boolean
> > +
> > + output-low:
> > + type: boolean
> > +
> > + output-high:
> > + type: boolean
> > +
> > + input-schmitt-enable:
> > + type: boolean
> > +
> > + input-schmitt-disable:
> > + type: boolean
> > +
> > + mediatek,pull-up-adv:
> > + description: |
> > + Pull up setings for 2 pull resistors, R0 and R1. User can
> > + configure those special pins. Valid arguments are described as below:
> > + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
> > + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
> > + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
> > + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
> > + allOf:
>
> You can drop the allOf now.
Got it, I'll drop it in next version.
Thanks
>
> > + - $ref: /schemas/types.yaml#/definitions/uint32
> > + - enum: [0, 1, 2, 3]
> > +
> > + mediatek,pull-down-adv:
> > + description: |
> > + Pull down settings for 2 pull resistors, R0 and R1. User can
> > + configure those special pins. Valid arguments are described as below:
> > + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
> > + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
> > + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
> > + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
> > + allOf:
> > + - $ref: /schemas/types.yaml#/definitions/uint32
> > + - enum: [0, 1, 2, 3]
> > +
> > + drive-strength:
> > + description: |
> > + Selects the drive strength for the specified pins in mA.
> > + allOf:
> > + - $ref: /schemas/types.yaml#/definitions/uint32
> > + - enum: [2, 4, 6, 8, 10, 12, 14, 16]
> > +
> > + required:
> > + - pinmux
> > +
> > + additionalProperties: false
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/pinctrl/mt6779-pinfunc.h>
> > +
> > + pio: pinctrl@10005000 {
> > + compatible = "mediatek,mt6779-pinctrl";
> > + reg = <0 0x10005000 0 0x1000>,
> > + <0 0x11c20000 0 0x1000>,
> > + <0 0x11d10000 0 0x1000>,
> > + <0 0x11e20000 0 0x1000>,
> > + <0 0x11e70000 0 0x1000>,
> > + <0 0x11ea0000 0 0x1000>,
> > + <0 0x11f20000 0 0x1000>,
> > + <0 0x11f30000 0 0x1000>,
> > + <0 0x1000b000 0 0x1000>;
> > + reg-names = "gpio", "iocfg_rm",
> > + "iocfg_br", "iocfg_lm",
> > + "iocfg_lb", "iocfg_rt",
> > + "iocfg_lt", "iocfg_tl",
> > + "eint";
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + gpio-ranges = <&pio 0 0 210>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
> > +
> > + mmc0_pins_default: mmc0-0 {
> > + cmd-dat-pins {
> > + pinmux = <PINMUX_GPIO168__FUNC_MSDC0_DAT0>,
> > + <PINMUX_GPIO172__FUNC_MSDC0_DAT1>,
> > + <PINMUX_GPIO169__FUNC_MSDC0_DAT2>,
> > + <PINMUX_GPIO177__FUNC_MSDC0_DAT3>,
> > + <PINMUX_GPIO170__FUNC_MSDC0_DAT4>,
> > + <PINMUX_GPIO173__FUNC_MSDC0_DAT5>,
> > + <PINMUX_GPIO171__FUNC_MSDC0_DAT6>,
> > + <PINMUX_GPIO174__FUNC_MSDC0_DAT7>,
> > + <PINMUX_GPIO167__FUNC_MSDC0_CMD>;
> > + input-enable;
> > + mediatek,pull-up-adv = <1>;
> > + };
> > + clk-pins {
> > + pinmux = <PINMUX_GPIO176__FUNC_MSDC0_CLK>;
> > + mediatek,pull-down-adv = <2>;
> > + };
> > + rst-pins {
> > + pinmux = <PINMUX_GPIO178__FUNC_MSDC0_RSTB>;
> > + mediatek,pull-up-adv = <0>;
> > + };
> > + };
> > + };
> > +
> > + mmc0 {
> > + pinctrl-0 = <&mmc0_pins_default>;
> > + pinctrl-names = "default";
> > + };
> > --
> > 1.7.9.5
>
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