This path series aims to add interconnect support in
dwc3-qcom driver on SDM845 and SC7180 SoCs.
Changes from v7 -> v8
> Only driver change is pending all other patches are merged so dropped
from the series.
> Removed the device_is_bound call and getting speed from device tree
and rearranged interconnect functions to avoid forward declarations.
> Added patch to specify maximum speed for dwc3 DT node.
Changes from v6 -> v7
> [PATCH 2/4] Fixed review comments from Matthias in DWC3 driver.
> Other patches remain unchanged.
Changes from v5 -> v6
> [PATCH 1/4] Addressed comments from Rob.
> [PATCH 2/4] Fixed review comments from Matthias in DWC3 driver.
> [PATCH 3/4] Ignoring 80 char limit in defining interconnect paths.
> Added [PATCH 4/4] in this series. Adding interconnect nodes for SC7180.
Depends on patch https://patchwork.kernel.org/patch/11417989/.
Changes from v4 -> v5
> [PATCH 1/3] Added the interconnect properties in yaml. This patch depends
on series https://patchwork.kernel.org/cover/11372641/.
> [PATCH 2/3] Fixed review comments from Matthias in DWC3 driver.
> [PATCH 3/3] Modified as per the new interconnect nodes in sdm845. Depends
on series https://patchwork.kernel.org/cover/11372211/.
Changes from v3 -> v4
> Fixed review comments from Matthias
> [PATCH 1/3] and [PATCH 3/3] remains unchanged
Changes from v2 -> v3
> Fixed review comments from Matthias and Manu
> changed the functions prefix from usb_* to dwc3_qcom_*
Changes since V1:
> Comments by Georgi Djakov on "[PATCH 2/3]" addressed
> [PATCH 1/3] and [PATCH 3/3] remains unchanged
Sandeep Maheswaram (2):
usb: dwc3: qcom: Add interconnect support in dwc3 driver
arm64: dts: qcom: sc7180: Add maximum speed property for DWC3 USB node
arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 +
drivers/usb/dwc3/dwc3-qcom.c | 127 ++++++++++++++++++++++++++++++++++-
2 files changed, 126 insertions(+), 2 deletions(-)
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Adding maximum speed property for DWC3 USB node which can be used
for setting interconnect bandwidth.
Signed-off-by: Sandeep Maheswaram <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 2be81a2..753e1a1 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -2544,6 +2544,7 @@
snps,dis_enblslpm_quirk;
phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
phy-names = "usb2-phy", "usb3-phy";
+ maximum-speed = "super-speed";
};
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Add interconnect support in dwc3-qcom driver to vote for bus
bandwidth.
This requires for two different paths - from USB master to
DDR slave. The other is from APPS master to USB slave.
Signed-off-by: Sandeep Maheswaram <[email protected]>
Signed-off-by: Chandana Kishori Chiluveru <[email protected]>
Reviewed-by: Matthias Kaehlcke <[email protected]>
---
drivers/usb/dwc3/dwc3-qcom.c | 127 ++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 125 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
index 1dfd024..5532988 100644
--- a/drivers/usb/dwc3/dwc3-qcom.c
+++ b/drivers/usb/dwc3/dwc3-qcom.c
@@ -13,6 +13,7 @@
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/extcon.h>
+#include <linux/interconnect.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/phy/phy.h>
@@ -43,6 +44,14 @@
#define SDM845_QSCRATCH_SIZE 0x400
#define SDM845_DWC3_CORE_SIZE 0xcd00
+/* Interconnect path bandwidths in MBps */
+#define USB_MEMORY_AVG_HS_BW MBps_to_icc(240)
+#define USB_MEMORY_PEAK_HS_BW MBps_to_icc(700)
+#define USB_MEMORY_AVG_SS_BW MBps_to_icc(1000)
+#define USB_MEMORY_PEAK_SS_BW MBps_to_icc(2500)
+#define APPS_USB_AVG_BW 0
+#define APPS_USB_PEAK_BW MBps_to_icc(40)
+
struct dwc3_acpi_pdata {
u32 qscratch_base_offset;
u32 qscratch_base_size;
@@ -73,9 +82,12 @@ struct dwc3_qcom {
const struct dwc3_acpi_pdata *acpi_pdata;
+ enum usb_device_speed max_speed;
enum usb_dr_mode mode;
bool is_suspended;
bool pm_suspended;
+ struct icc_path *usb_ddr_icc_path;
+ struct icc_path *apps_usb_icc_path;
};
static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
@@ -190,6 +202,99 @@ static int dwc3_qcom_register_extcon(struct dwc3_qcom *qcom)
return 0;
}
+/* Currently we only use bandwidth level, so just "enable" interconnects */
+static int dwc3_qcom_interconnect_enable(struct dwc3_qcom *qcom)
+{
+ int ret;
+
+ if (qcom->max_speed >= USB_SPEED_SUPER)
+ ret = icc_set_bw(qcom->usb_ddr_icc_path,
+ USB_MEMORY_AVG_SS_BW, USB_MEMORY_PEAK_SS_BW);
+ else
+ ret = icc_set_bw(qcom->usb_ddr_icc_path,
+ USB_MEMORY_AVG_HS_BW, USB_MEMORY_PEAK_HS_BW);
+
+ if (ret)
+ return ret;
+
+ ret = icc_set_bw(qcom->apps_usb_icc_path,
+ APPS_USB_AVG_BW, APPS_USB_PEAK_BW);
+ if (ret)
+ icc_set_bw(qcom->usb_ddr_icc_path, 0, 0);
+
+ return ret;
+}
+
+/* To disable an interconnect, we just set its bandwidth to 0 */
+static int dwc3_qcom_interconnect_disable(struct dwc3_qcom *qcom)
+{
+ int ret;
+
+ ret = icc_set_bw(qcom->usb_ddr_icc_path, 0, 0);
+ if (ret)
+ return ret;
+
+ ret = icc_set_bw(qcom->apps_usb_icc_path, 0, 0);
+ if (ret)
+ goto err_reenable_memory_path;
+
+ return 0;
+
+ /* Re-enable things in the event of an error */
+err_reenable_memory_path:
+ dwc3_qcom_interconnect_enable(qcom);
+
+ return ret;
+}
+
+/**
+ * dwc3_qcom_interconnect_init() - Get interconnect path handles
+ * @qcom: Pointer to the concerned usb core.
+ *
+ */
+static int dwc3_qcom_interconnect_init(struct dwc3_qcom *qcom)
+{
+ struct device *dev = qcom->dev;
+ int ret;
+
+ if (!device_is_bound(&qcom->dwc3->dev))
+ return -EPROBE_DEFER;
+
+ qcom->usb_ddr_icc_path = of_icc_get(dev, "usb-ddr");
+ if (IS_ERR(qcom->usb_ddr_icc_path)) {
+ dev_err(dev, "Error: (%ld) failed getting usb-ddr path\n",
+ PTR_ERR(qcom->usb_ddr_icc_path));
+ return PTR_ERR(qcom->usb_ddr_icc_path);
+ }
+
+ qcom->apps_usb_icc_path = of_icc_get(dev, "apps-usb");
+ if (IS_ERR(qcom->apps_usb_icc_path)) {
+ dev_err(dev, "Error: (%ld) failed getting apps-usb path\n",
+ PTR_ERR(qcom->apps_usb_icc_path));
+ return PTR_ERR(qcom->apps_usb_icc_path);
+ }
+
+ ret = dwc3_qcom_interconnect_enable(qcom);
+ if (ret) {
+ dev_err(dev, "failed to enable interconnect %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+/**
+ * dwc3_qcom_interconnect_exit() - Release interconnect path handles
+ * @qcom: Pointer to the concerned usb core.
+ *
+ * This function is used to release interconnect path handle.
+ */
+static void dwc3_qcom_interconnect_exit(struct dwc3_qcom *qcom)
+{
+ icc_put(qcom->usb_ddr_icc_path);
+ icc_put(qcom->apps_usb_icc_path);
+}
+
static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom)
{
if (qcom->hs_phy_irq) {
@@ -239,7 +344,7 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
static int dwc3_qcom_suspend(struct dwc3_qcom *qcom)
{
u32 val;
- int i;
+ int i, ret;
if (qcom->is_suspended)
return 0;
@@ -251,6 +356,10 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom)
for (i = qcom->num_clocks - 1; i >= 0; i--)
clk_disable_unprepare(qcom->clks[i]);
+ ret = dwc3_qcom_interconnect_disable(qcom);
+ if (ret)
+ dev_warn(qcom->dev, "failed to disable interconnect %d\n", ret);
+
qcom->is_suspended = true;
dwc3_qcom_enable_interrupts(qcom);
@@ -276,6 +385,10 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom)
}
}
+ ret = dwc3_qcom_interconnect_enable(qcom);
+ if (ret)
+ dev_warn(qcom->dev, "failed to enable interconnect %d\n", ret);
+
/* Clear existing events from PHY related to L2 in/out */
dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG,
PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK);
@@ -285,6 +398,8 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom)
return 0;
}
+
+
static irqreturn_t qcom_dwc3_resume_irq(int irq, void *data)
{
struct dwc3_qcom *qcom = data;
@@ -648,6 +763,11 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
goto depopulate;
}
+ qcom->max_speed = usb_get_maximum_speed(&qcom->dwc3->dev);
+ ret = dwc3_qcom_interconnect_init(qcom);
+ if (ret)
+ goto depopulate;
+
qcom->mode = usb_get_dr_mode(&qcom->dwc3->dev);
/* enable vbus override for device mode */
@@ -657,7 +777,7 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
/* register extcon to override sw_vbus on Vbus change later */
ret = dwc3_qcom_register_extcon(qcom);
if (ret)
- goto depopulate;
+ goto interconnect_exit;
device_init_wakeup(&pdev->dev, 1);
qcom->is_suspended = false;
@@ -667,6 +787,8 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
return 0;
+interconnect_exit:
+ dwc3_qcom_interconnect_exit(qcom);
depopulate:
if (np)
of_platform_depopulate(&pdev->dev);
@@ -697,6 +819,7 @@ static int dwc3_qcom_remove(struct platform_device *pdev)
}
qcom->num_clocks = 0;
+ dwc3_qcom_interconnect_exit(qcom);
reset_control_assert(qcom->resets);
pm_runtime_allow(dev);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Hi Sandeep,
On Thu, Jul 09, 2020 at 09:30:11PM +0530, Sandeep Maheswaram wrote:
> Add interconnect support in dwc3-qcom driver to vote for bus
> bandwidth.
>
> This requires for two different paths - from USB master to
> DDR slave. The other is from APPS master to USB slave.
>
> Signed-off-by: Sandeep Maheswaram <[email protected]>
> Signed-off-by: Chandana Kishori Chiluveru <[email protected]>
> Reviewed-by: Matthias Kaehlcke <[email protected]>
> ---
> drivers/usb/dwc3/dwc3-qcom.c | 127 ++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 125 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
> index 1dfd024..5532988 100644
> --- a/drivers/usb/dwc3/dwc3-qcom.c
> +++ b/drivers/usb/dwc3/dwc3-qcom.c
> @@ -13,6 +13,7 @@
> #include <linux/module.h>
> #include <linux/kernel.h>
> #include <linux/extcon.h>
> +#include <linux/interconnect.h>
> #include <linux/of_platform.h>
> #include <linux/platform_device.h>
> #include <linux/phy/phy.h>
> @@ -43,6 +44,14 @@
> #define SDM845_QSCRATCH_SIZE 0x400
> #define SDM845_DWC3_CORE_SIZE 0xcd00
>
> +/* Interconnect path bandwidths in MBps */
> +#define USB_MEMORY_AVG_HS_BW MBps_to_icc(240)
> +#define USB_MEMORY_PEAK_HS_BW MBps_to_icc(700)
> +#define USB_MEMORY_AVG_SS_BW MBps_to_icc(1000)
> +#define USB_MEMORY_PEAK_SS_BW MBps_to_icc(2500)
> +#define APPS_USB_AVG_BW 0
> +#define APPS_USB_PEAK_BW MBps_to_icc(40)
> +
> struct dwc3_acpi_pdata {
> u32 qscratch_base_offset;
> u32 qscratch_base_size;
> @@ -73,9 +82,12 @@ struct dwc3_qcom {
>
> const struct dwc3_acpi_pdata *acpi_pdata;
>
> + enum usb_device_speed max_speed;
> enum usb_dr_mode mode;
> bool is_suspended;
> bool pm_suspended;
> + struct icc_path *usb_ddr_icc_path;
> + struct icc_path *apps_usb_icc_path;
nit: the names are a bit clunky, the 'usb' part is redundant. You could name
'icc_path_ddr' and 'icc_path_apps' or add an anonymous struct:
struct {
struct icc_path ddr;
struct icc_path apps;
};
not super-important, but since it looks like you have to respin anyway it's
something to consider.
> };
>
> static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
> @@ -190,6 +202,99 @@ static int dwc3_qcom_register_extcon(struct dwc3_qcom *qcom)
> return 0;
> }
>
> +/* Currently we only use bandwidth level, so just "enable" interconnects */
> +static int dwc3_qcom_interconnect_enable(struct dwc3_qcom *qcom)
> +{
> + int ret;
> +
> + if (qcom->max_speed >= USB_SPEED_SUPER)
> + ret = icc_set_bw(qcom->usb_ddr_icc_path,
> + USB_MEMORY_AVG_SS_BW, USB_MEMORY_PEAK_SS_BW);
> + else
> + ret = icc_set_bw(qcom->usb_ddr_icc_path,
> + USB_MEMORY_AVG_HS_BW, USB_MEMORY_PEAK_HS_BW);
> +
> + if (ret)
> + return ret;
> +
> + ret = icc_set_bw(qcom->apps_usb_icc_path,
> + APPS_USB_AVG_BW, APPS_USB_PEAK_BW);
> + if (ret)
> + icc_set_bw(qcom->usb_ddr_icc_path, 0, 0);
> +
The helpers icc_enable/disable() were recently added. With that you only
have to set the bandwidth once (unless it changes) and then use icc_disable()
to set it to 0 and icc_enable() to restore it.
With icc_enable/disable() the above code would move to
dwc3_qcom_interconnect_init(). It would also make it unnecessary to
have a 'max_speed' field in struct dwc3_qcom.
With that it might not be worth to keep dwc3_qcom_interconnect_enable/disable(),
since they will be relatively short and only have a single caller.
> + return ret;
> +}
> +
> +/* To disable an interconnect, we just set its bandwidth to 0 */
> +static int dwc3_qcom_interconnect_disable(struct dwc3_qcom *qcom)
> +{
> + int ret;
> +
> + ret = icc_set_bw(qcom->usb_ddr_icc_path, 0, 0);
> + if (ret)
> + return ret;
> +
> + ret = icc_set_bw(qcom->apps_usb_icc_path, 0, 0);
> + if (ret)
> + goto err_reenable_memory_path;
> +
> + return 0;
> +
> + /* Re-enable things in the event of an error */
> +err_reenable_memory_path:
> + dwc3_qcom_interconnect_enable(qcom);
> +
> + return ret;
> +}
> +
> +/**
> + * dwc3_qcom_interconnect_init() - Get interconnect path handles
> + * @qcom: Pointer to the concerned usb core.
> + *
> + */
> +static int dwc3_qcom_interconnect_init(struct dwc3_qcom *qcom)
> +{
> + struct device *dev = qcom->dev;
> + int ret;
> +
> + if (!device_is_bound(&qcom->dwc3->dev))
> + return -EPROBE_DEFER;
This is the main reason you need to respin. The outcome of earlier
discussions with Greg KH and Rob Herring was that using device_is_bound()
isn't the correct solution, which is why you call usb_get_maximum_speed()
in _probe().
> +
> + qcom->usb_ddr_icc_path = of_icc_get(dev, "usb-ddr");
> + if (IS_ERR(qcom->usb_ddr_icc_path)) {
> + dev_err(dev, "Error: (%ld) failed getting usb-ddr path\n",
nit: the "Error ... failed" is a bit redundant, the message is also
inconsistent with the format used when dwc3_qcom_interconnect_enable()
fails (a few lines further below). I would suggest to use "failed to
<whatever failed>: %d\n".
> + PTR_ERR(qcom->usb_ddr_icc_path));
> + return PTR_ERR(qcom->usb_ddr_icc_path);
> + }
> +
> + qcom->apps_usb_icc_path = of_icc_get(dev, "apps-usb");
> + if (IS_ERR(qcom->apps_usb_icc_path)) {
> + dev_err(dev, "Error: (%ld) failed getting apps-usb path\n",
> + PTR_ERR(qcom->apps_usb_icc_path));
ditto
> + return PTR_ERR(qcom->apps_usb_icc_path);
> + }
> +
> + ret = dwc3_qcom_interconnect_enable(qcom);
> + if (ret) {
> + dev_err(dev, "failed to enable interconnect %d\n", ret);
nit: add ':' after 'interconnect'
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * dwc3_qcom_interconnect_exit() - Release interconnect path handles
> + * @qcom: Pointer to the concerned usb core.
> + *
> + * This function is used to release interconnect path handle.
> + */
> +static void dwc3_qcom_interconnect_exit(struct dwc3_qcom *qcom)
> +{
> + icc_put(qcom->usb_ddr_icc_path);
> + icc_put(qcom->apps_usb_icc_path);
> +}
> +
> static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom)
> {
> if (qcom->hs_phy_irq) {
> @@ -239,7 +344,7 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
> static int dwc3_qcom_suspend(struct dwc3_qcom *qcom)
> {
> u32 val;
> - int i;
> + int i, ret;
>
> if (qcom->is_suspended)
> return 0;
> @@ -251,6 +356,10 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom)
> for (i = qcom->num_clocks - 1; i >= 0; i--)
> clk_disable_unprepare(qcom->clks[i]);
>
> + ret = dwc3_qcom_interconnect_disable(qcom);
> + if (ret)
> + dev_warn(qcom->dev, "failed to disable interconnect %d\n", ret);
nit: add ':' after 'interconnect'.
> +
> qcom->is_suspended = true;
> dwc3_qcom_enable_interrupts(qcom);
>
> @@ -276,6 +385,10 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom)
> }
> }
>
> + ret = dwc3_qcom_interconnect_enable(qcom);
> + if (ret)
> + dev_warn(qcom->dev, "failed to enable interconnect %d\n", ret);
ditto
Hi,
inline one more thing I forgot to comment on in my previous mail
On Thu, Jul 09, 2020 at 09:30:11PM +0530, Sandeep Maheswaram wrote:
> Add interconnect support in dwc3-qcom driver to vote for bus
> bandwidth.
>
> This requires for two different paths - from USB master to
> DDR slave. The other is from APPS master to USB slave.
>
> Signed-off-by: Sandeep Maheswaram <[email protected]>
> Signed-off-by: Chandana Kishori Chiluveru <[email protected]>
> Reviewed-by: Matthias Kaehlcke <[email protected]>
> ---
> drivers/usb/dwc3/dwc3-qcom.c | 127 ++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 125 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
> index 1dfd024..5532988 100644
> --- a/drivers/usb/dwc3/dwc3-qcom.c
> +++ b/drivers/usb/dwc3/dwc3-qcom.c
>
> ...
>
> @@ -648,6 +763,11 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
> goto depopulate;
> }
>
> + qcom->max_speed = usb_get_maximum_speed(&qcom->dwc3->dev);
What if the function returns USB_SPEED_UNKNOWN?
You need a reasonable default value for that case, which I think would be
USB_SPEED_SUPER (i.e. the controller would work properly at super speed,
though the interconnects would consume a bit more power than necessary lower
speed modes).
On Thu, Jul 09, 2020 at 09:30:12PM +0530, Sandeep Maheswaram wrote:
> Adding maximum speed property for DWC3 USB node which can be used
> for setting interconnect bandwidth.
>
> Signed-off-by: Sandeep Maheswaram <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index 2be81a2..753e1a1 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -2544,6 +2544,7 @@
> snps,dis_enblslpm_quirk;
> phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
> phy-names = "usb2-phy", "usb3-phy";
> + maximum-speed = "super-speed";
> };
> };
It shouldn't be strictly necessary if you use super-speed as default
max-speed in the driver, but it also does no harm.
Reviewed-by: Matthias Kaehlcke <[email protected]>
You might want to add it for other platforms too.