2020-06-20 16:26:15

by Martin Blumenstingl

Subject: [PATCH v2] arm64: dts: amlogic: Add the Ethernet "timing-adjustment" clock

Add the "timing-adjustment" clock now that we know how it is connected
to the PRG_ETHERNET registers. It is used internally to generate the
RGMII RX delay on the MAC side (if needed).

Signed-off-by: Martin Blumenstingl <[email protected]>
---
Changes since v1 at [0]:
- fixed all typos in the commit message (hopefully...). Thanks to Andrew
for spotting the first ("no" -> "on") one and shame on me for having
to find two more ("adjusment" -> "adjustment", "now" -> "know")


[0] https://patchwork.kernel.org/patch/11616101/


arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 6 ++++--
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 6 ++++--
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 5 +++--
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 5 +++--
4 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 8e6281c685fa..b9efc8469265 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -181,8 +181,10 @@ ethmac: ethernet@ff3f0000 {
interrupt-names = "macirq";
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
- <&clkc CLKID_MPLL2>;
- clock-names = "stmmaceth", "clkin0", "clkin1";
+ <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_FCLK_DIV2>;
+ clock-names = "stmmaceth", "clkin0", "clkin1",
+ "timing-adjustment";
rx-fifo-depth = <4096>;
tx-fifo-depth = <2048>;
status = "disabled";
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
index 593a006f4b7b..41805f2ed8fc 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
@@ -185,8 +185,10 @@ ethmac: ethernet@ff3f0000 {
interrupt-names = "macirq";
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
- <&clkc CLKID_MPLL2>;
- clock-names = "stmmaceth", "clkin0", "clkin1";
+ <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_FCLK_DIV2>;
+ clock-names = "stmmaceth", "clkin0", "clkin1",
+ "timing-adjustment";
rx-fifo-depth = <4096>;
tx-fifo-depth = <2048>;
status = "disabled";
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 234490d3ee68..03c25b9facff 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -333,8 +333,9 @@ &efuse {
&ethmac {
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
- <&clkc CLKID_MPLL2>;
- clock-names = "stmmaceth", "clkin0", "clkin1";
+ <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_FCLK_DIV2>;
+ clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
};

&gpio_intc {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index fc59c8534c0f..60484bbc7272 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -131,8 +131,9 @@ &efuse {
&ethmac {
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
- <&clkc CLKID_MPLL2>;
- clock-names = "stmmaceth", "clkin0", "clkin1";
+ <&clkc CLKID_MPLL2>,
+ <&clkc CLKID_FCLK_DIV2>;
+ clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";

mdio0: mdio {
#address-cells = <1>;
--
2.27.0

2020-06-22 07:59:28

by Neil Armstrong

Subject: Re: [PATCH v2] arm64: dts: amlogic: Add the Ethernet "timing-adjustment" clock

On 20/06/2020 18:23, Martin Blumenstingl wrote:
> Add the "timing-adjustment" clock now that we know how it is connected
> to the PRG_ETHERNET registers. It is used internally to generate the
> RGMII RX delay on the MAC side (if needed).
>
> Signed-off-by: Martin Blumenstingl <[email protected]>
> ---
> Changes since v1 at [0]:
> - fixed all typos in the commit message (hopefully...). Thanks to Andrew
> for spotting the first ("no" -> "on") one and shame on me for having
> to find two more ("adjusment" -> "adjustment", "now" -> "know")
>
>
> [0] https://patchwork.kernel.org/patch/11616101/
>
>
> arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 6 ++++--
> arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 6 ++++--
> arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 5 +++--
> arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 5 +++--
> 4 files changed, 14 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> index 8e6281c685fa..b9efc8469265 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> @@ -181,8 +181,10 @@ ethmac: ethernet@ff3f0000 {
> interrupt-names = "macirq";
> clocks = <&clkc CLKID_ETH>,
> <&clkc CLKID_FCLK_DIV2>,
> - <&clkc CLKID_MPLL2>;
> - clock-names = "stmmaceth", "clkin0", "clkin1";
> + <&clkc CLKID_MPLL2>,
> + <&clkc CLKID_FCLK_DIV2>;
> + clock-names = "stmmaceth", "clkin0", "clkin1",
> + "timing-adjustment";
> rx-fifo-depth = <4096>;
> tx-fifo-depth = <2048>;
> status = "disabled";
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
> index 593a006f4b7b..41805f2ed8fc 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
> @@ -185,8 +185,10 @@ ethmac: ethernet@ff3f0000 {
> interrupt-names = "macirq";
> clocks = <&clkc CLKID_ETH>,
> <&clkc CLKID_FCLK_DIV2>,
> - <&clkc CLKID_MPLL2>;
> - clock-names = "stmmaceth", "clkin0", "clkin1";
> + <&clkc CLKID_MPLL2>,
> + <&clkc CLKID_FCLK_DIV2>;
> + clock-names = "stmmaceth", "clkin0", "clkin1",
> + "timing-adjustment";
> rx-fifo-depth = <4096>;
> tx-fifo-depth = <2048>;
> status = "disabled";
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> index 234490d3ee68..03c25b9facff 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> @@ -333,8 +333,9 @@ &efuse {
> &ethmac {
> clocks = <&clkc CLKID_ETH>,
> <&clkc CLKID_FCLK_DIV2>,
> - <&clkc CLKID_MPLL2>;
> - clock-names = "stmmaceth", "clkin0", "clkin1";
> + <&clkc CLKID_MPLL2>,
> + <&clkc CLKID_FCLK_DIV2>;
> + clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
> };
>
> &gpio_intc {
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
> index fc59c8534c0f..60484bbc7272 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
> @@ -131,8 +131,9 @@ &efuse {
> &ethmac {
> clocks = <&clkc CLKID_ETH>,
> <&clkc CLKID_FCLK_DIV2>,
> - <&clkc CLKID_MPLL2>;
> - clock-names = "stmmaceth", "clkin0", "clkin1";
> + <&clkc CLKID_MPLL2>,
> + <&clkc CLKID_FCLK_DIV2>;
> + clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
>
> mdio0: mdio {
> #address-cells = <1>;
>

Reviewed-by: Neil Armstrong <[email protected]>

2020-07-13 19:05:24

by Kevin Hilman

Subject: Re: [PATCH v2] arm64: dts: amlogic: Add the Ethernet "timing-adjustment" clock

On Sat, 20 Jun 2020 18:23:47 +0200, Martin Blumenstingl wrote:
> Add the "timing-adjustment" clock now that we know how it is connected
> to the PRG_ETHERNET registers. It is used internally to generate the
> RGMII RX delay on the MAC side (if needed).

Applied, thanks!

[1/1] arm64: dts: amlogic: Add the Ethernet "timing-adjustment" clock
(no commit info)

Best regards,
--
Kevin Hilman <[email protected]>