From: Wanpeng Li <[email protected]>
Prevent setting the tscdeadline timer if the lapic is hw disabled.
Signed-off-by: Wanpeng Li <[email protected]>
---
arch/x86/kvm/lapic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 5bf72fc..4ce2ddd 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -2195,7 +2195,7 @@ void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
{
struct kvm_lapic *apic = vcpu->arch.apic;
- if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
+ if (!kvm_apic_present(vcpu) || apic_lvtt_oneshot(apic) ||
apic_lvtt_period(apic))
return;
--
2.7.4
From: Wanpeng Li <[email protected]>
Only bits 0, 1, and 3 are settable, others are reserved for APIC_TDCR.
Let's record the settable value in the virtual apic page.
Signed-off-by: Wanpeng Li <[email protected]>
---
arch/x86/kvm/lapic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 4ce2ddd..8f7a14d 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -2068,7 +2068,7 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
case APIC_TDCR: {
uint32_t old_divisor = apic->divide_count;
- kvm_lapic_set_reg(apic, APIC_TDCR, val);
+ kvm_lapic_set_reg(apic, APIC_TDCR, val & 0xb);
update_divide_count(apic);
if (apic->divide_count != old_divisor &&
apic->lapic_timer.period) {
--
2.7.4
Wanpeng Li <[email protected]> writes:
> From: Wanpeng Li <[email protected]>
>
> Prevent setting the tscdeadline timer if the lapic is hw disabled.
>
> Signed-off-by: Wanpeng Li <[email protected]>
> ---
> arch/x86/kvm/lapic.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> index 5bf72fc..4ce2ddd 100644
> --- a/arch/x86/kvm/lapic.c
> +++ b/arch/x86/kvm/lapic.c
> @@ -2195,7 +2195,7 @@ void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
> {
> struct kvm_lapic *apic = vcpu->arch.apic;
>
> - if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
> + if (!kvm_apic_present(vcpu) || apic_lvtt_oneshot(apic) ||
> apic_lvtt_period(apic))
> return;
Out of pure curiosity, what is the architectural behavior if I disable
LAPIC, write to IA32_TSC_DEADLINE and then re-enable LAPIC before the
timer was supposed to fire?
--
Vitaly
Wanpeng Li <[email protected]> writes:
> From: Wanpeng Li <[email protected]>
>
> Only bits 0, 1, and 3 are settable, others are reserved for APIC_TDCR.
> Let's record the settable value in the virtual apic page.
>
> Signed-off-by: Wanpeng Li <[email protected]>
> ---
> arch/x86/kvm/lapic.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> index 4ce2ddd..8f7a14d 100644
> --- a/arch/x86/kvm/lapic.c
> +++ b/arch/x86/kvm/lapic.c
> @@ -2068,7 +2068,7 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
> case APIC_TDCR: {
> uint32_t old_divisor = apic->divide_count;
>
> - kvm_lapic_set_reg(apic, APIC_TDCR, val);
> + kvm_lapic_set_reg(apic, APIC_TDCR, val & 0xb);
> update_divide_count(apic);
> if (apic->divide_count != old_divisor &&
> apic->lapic_timer.period) {
AFAIU bit 2 should be 0 and other upper bits are reserved. Checking on
bare hardware,
# wrmsr 0x83e 0xb
# rdmsr 0x83e
b
# wrmsr 0x83e 0xc
wrmsr: CPU 0 cannot set MSR 0x0000083e to 0x000000000000000c
# rdmsr 0x83e
b
Shouldn't we fail the write in case (val & ~0xb) ?
--
Vitaly
On Tue, Jul 21, 2020 at 12:35:01PM +0200, Vitaly Kuznetsov wrote:
> Wanpeng Li <[email protected]> writes:
>
> > From: Wanpeng Li <[email protected]>
> >
> > Prevent setting the tscdeadline timer if the lapic is hw disabled.
> >
> > Signed-off-by: Wanpeng Li <[email protected]>
A Fixes and/or Cc stable is probably needed for this.
> > ---
> > arch/x86/kvm/lapic.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> > index 5bf72fc..4ce2ddd 100644
> > --- a/arch/x86/kvm/lapic.c
> > +++ b/arch/x86/kvm/lapic.c
> > @@ -2195,7 +2195,7 @@ void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
> > {
> > struct kvm_lapic *apic = vcpu->arch.apic;
> >
> > - if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
> > + if (!kvm_apic_present(vcpu) || apic_lvtt_oneshot(apic) ||
> > apic_lvtt_period(apic))
> > return;
>
> Out of pure curiosity, what is the architectural behavior if I disable
> LAPIC, write to IA32_TSC_DEADLINE and then re-enable LAPIC before the
> timer was supposed to fire?
Intel's SDM reserves the right for the CPU to do whatever it wants :-)
When IA32_APIC_BASE[11] is set to 0, prior initialization to the APIC
may be lost and the APIC may return to the state described in Section
10.4.7.1, “Local APIC State After Power-Up or Reset.”
Practically speaking, resetting APIC state seems like the sane approach,
i.e. KVM should probably call kvm_lapic_reset() when the APIC transitions
from HW enabled -> disabled. Maybe in a follow-up patch to this one?
On Tue, 21 Jul 2020 at 18:51, Vitaly Kuznetsov <[email protected]> wrote:
>
> Wanpeng Li <[email protected]> writes:
>
> > From: Wanpeng Li <[email protected]>
> >
> > Only bits 0, 1, and 3 are settable, others are reserved for APIC_TDCR.
> > Let's record the settable value in the virtual apic page.
> >
> > Signed-off-by: Wanpeng Li <[email protected]>
> > ---
> > arch/x86/kvm/lapic.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> > index 4ce2ddd..8f7a14d 100644
> > --- a/arch/x86/kvm/lapic.c
> > +++ b/arch/x86/kvm/lapic.c
> > @@ -2068,7 +2068,7 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
> > case APIC_TDCR: {
> > uint32_t old_divisor = apic->divide_count;
> >
> > - kvm_lapic_set_reg(apic, APIC_TDCR, val);
> > + kvm_lapic_set_reg(apic, APIC_TDCR, val & 0xb);
> > update_divide_count(apic);
> > if (apic->divide_count != old_divisor &&
> > apic->lapic_timer.period) {
>
> AFAIU bit 2 should be 0 and other upper bits are reserved. Checking on
> bare hardware,
>
> # wrmsr 0x83e 0xb
> # rdmsr 0x83e
> b
> # wrmsr 0x83e 0xc
> wrmsr: CPU 0 cannot set MSR 0x0000083e to 0x000000000000000c
> # rdmsr 0x83e
> b
>
> Shouldn't we fail the write in case (val & ~0xb) ?
Sorry for the late response since I just come back from vacation. I
can remove the "others are reserved" in patch description for the next
version. It is a little different between Intel and AMD, Intel's bit 2
is 0 and AMD is reserved. On bare-metal, Intel will refuse to set
APIC_TDCR once bits except 0, 1, 3 are setting, however, AMD will
accept bits 0, 1, 3 and ignore other bits setting as patch does.
Before the patch, we can get back anything what we set to the
APIC_TDCR, this patch improves it.
Wanpeng
On Tue, 21 Jul 2020 at 23:25, Sean Christopherson
<[email protected]> wrote:
>
> On Tue, Jul 21, 2020 at 12:35:01PM +0200, Vitaly Kuznetsov wrote:
> > Wanpeng Li <[email protected]> writes:
> >
> > > From: Wanpeng Li <[email protected]>
> > >
> > > Prevent setting the tscdeadline timer if the lapic is hw disabled.
> > >
> > > Signed-off-by: Wanpeng Li <[email protected]>
>
> A Fixes and/or Cc stable is probably needed for this.
>
> > > ---
> > > arch/x86/kvm/lapic.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> > > index 5bf72fc..4ce2ddd 100644
> > > --- a/arch/x86/kvm/lapic.c
> > > +++ b/arch/x86/kvm/lapic.c
> > > @@ -2195,7 +2195,7 @@ void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
> > > {
> > > struct kvm_lapic *apic = vcpu->arch.apic;
> > >
> > > - if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
> > > + if (!kvm_apic_present(vcpu) || apic_lvtt_oneshot(apic) ||
> > > apic_lvtt_period(apic))
> > > return;
> >
> > Out of pure curiosity, what is the architectural behavior if I disable
> > LAPIC, write to IA32_TSC_DEADLINE and then re-enable LAPIC before the
> > timer was supposed to fire?
>
> Intel's SDM reserves the right for the CPU to do whatever it wants :-)
>
> When IA32_APIC_BASE[11] is set to 0, prior initialization to the APIC
> may be lost and the APIC may return to the state described in Section
> 10.4.7.1, “Local APIC State After Power-Up or Reset.”
>
> Practically speaking, resetting APIC state seems like the sane approach,
> i.e. KVM should probably call kvm_lapic_reset() when the APIC transitions
> from HW enabled -> disabled. Maybe in a follow-up patch to this one?
kvm_lapic_reset() will call the set base logic, a little recursive in
the codes, it can be done after this recursion is solved.
Wanpeng