This path series aims to add interconnect support in
dwc3-qcom driver on SDM845 and SC7180 SoCs.
Changes from v10 -> v11
> Made the error handling symmetrical in enable and disable cases.
> Removed empty line in interconnect-init function.
Changes from v9 -> v10
> Removed cooments for enable,disable functions.
> Handled the enable,disable failure cases as in v8.
Changes from v8 -> v9
> Addressed comments from Matthias.
Changes from v7 -> v8
> Only driver change is pending all other patches are merged so dropped
from the series.
> Removed the device_is_bound call and getting speed from device tree
and rearranged interconnect functions to avoid forward declarations.
> Added patch to specify maximum speed for dwc3 DT node.
Changes from v6 -> v7
> [PATCH 2/4] Fixed review comments from Matthias in DWC3 driver.
> Other patches remain unchanged.
Changes from v5 -> v6
> [PATCH 1/4] Addressed comments from Rob.
> [PATCH 2/4] Fixed review comments from Matthias in DWC3 driver.
> [PATCH 3/4] Ignoring 80 char limit in defining interconnect paths.
> Added [PATCH 4/4] in this series. Adding interconnect nodes for SC7180.
Depends on patch https://patchwork.kernel.org/patch/11417989/.
Changes from v4 -> v5
> [PATCH 1/3] Added the interconnect properties in yaml. This patch depends
on series https://patchwork.kernel.org/cover/11372641/.
> [PATCH 2/3] Fixed review comments from Matthias in DWC3 driver.
> [PATCH 3/3] Modified as per the new interconnect nodes in sdm845. Depends
on series https://patchwork.kernel.org/cover/11372211/.
Changes from v3 -> v4
> Fixed review comments from Matthias
> [PATCH 1/3] and [PATCH 3/3] remains unchanged
Changes from v2 -> v3
> Fixed review comments from Matthias and Manu
> changed the functions prefix from usb_* to dwc3_qcom_*
Changes since V1:
> Comments by Georgi Djakov on "[PATCH 2/3]" addressed
> [PATCH 1/3] and [PATCH 3/3] remains unchanged
Sandeep Maheswaram (2):
usb: dwc3: qcom: Add interconnect support in dwc3 driver
arm64: dts: qcom: sc7180: Add maximum speed property for DWC3 USB node
arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 +
drivers/usb/dwc3/dwc3-qcom.c | 120 ++++++++++++++++++++++++++++++++++-
2 files changed, 119 insertions(+), 2 deletions(-)
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Add interconnect support in dwc3-qcom driver to vote for bus
bandwidth.
This requires for two different paths - from USB to
DDR. The other is from APPS to USB.
Signed-off-by: Sandeep Maheswaram <[email protected]>
Signed-off-by: Chandana Kishori Chiluveru <[email protected]>
---
drivers/usb/dwc3/dwc3-qcom.c | 120 ++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 118 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
index e1e78e9..fcf7f79 100644
--- a/drivers/usb/dwc3/dwc3-qcom.c
+++ b/drivers/usb/dwc3/dwc3-qcom.c
@@ -13,6 +13,7 @@
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/extcon.h>
+#include <linux/interconnect.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/phy/phy.h>
@@ -43,6 +44,14 @@
#define SDM845_QSCRATCH_SIZE 0x400
#define SDM845_DWC3_CORE_SIZE 0xcd00
+/* Interconnect path bandwidths in MBps */
+#define USB_MEMORY_AVG_HS_BW MBps_to_icc(240)
+#define USB_MEMORY_PEAK_HS_BW MBps_to_icc(700)
+#define USB_MEMORY_AVG_SS_BW MBps_to_icc(1000)
+#define USB_MEMORY_PEAK_SS_BW MBps_to_icc(2500)
+#define APPS_USB_AVG_BW 0
+#define APPS_USB_PEAK_BW MBps_to_icc(40)
+
struct dwc3_acpi_pdata {
u32 qscratch_base_offset;
u32 qscratch_base_size;
@@ -76,6 +85,8 @@ struct dwc3_qcom {
enum usb_dr_mode mode;
bool is_suspended;
bool pm_suspended;
+ struct icc_path *icc_path_ddr;
+ struct icc_path *icc_path_apps;
};
static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
@@ -190,6 +201,96 @@ static int dwc3_qcom_register_extcon(struct dwc3_qcom *qcom)
return 0;
}
+static int dwc3_qcom_interconnect_enable(struct dwc3_qcom *qcom)
+{
+ int ret;
+
+ ret = icc_enable(qcom->icc_path_ddr);
+ if (ret)
+ return ret;
+
+ ret = icc_enable(qcom->icc_path_apps);
+ if (ret)
+ icc_disable(qcom->icc_path_ddr);
+
+ return ret;
+}
+
+static int dwc3_qcom_interconnect_disable(struct dwc3_qcom *qcom)
+{
+ int ret;
+
+ ret = icc_disable(qcom->icc_path_ddr);
+ if (ret)
+ return ret;
+
+ ret = icc_disable(qcom->icc_path_apps);
+ if (ret)
+ icc_enable(qcom->icc_path_ddr);
+
+ return ret;
+}
+
+/**
+ * dwc3_qcom_interconnect_init() - Get interconnect path handles
+ * and set bandwidhth.
+ * @qcom: Pointer to the concerned usb core.
+ *
+ */
+static int dwc3_qcom_interconnect_init(struct dwc3_qcom *qcom)
+{
+ struct device *dev = qcom->dev;
+ int ret;
+
+ qcom->icc_path_ddr = of_icc_get(dev, "usb-ddr");
+ if (IS_ERR(qcom->icc_path_ddr)) {
+ dev_err(dev, "failed to get usb-ddr path: %ld\n",
+ PTR_ERR(qcom->icc_path_ddr));
+ return PTR_ERR(qcom->icc_path_ddr);
+ }
+
+ qcom->icc_path_apps = of_icc_get(dev, "apps-usb");
+ if (IS_ERR(qcom->icc_path_apps)) {
+ dev_err(dev, "failed to get apps-usb path: %ld\n",
+ PTR_ERR(qcom->icc_path_apps));
+ return PTR_ERR(qcom->icc_path_apps);
+ }
+
+ if (usb_get_maximum_speed(&qcom->dwc3->dev) >= USB_SPEED_SUPER ||
+ usb_get_maximum_speed(&qcom->dwc3->dev) == USB_SPEED_UNKNOWN)
+ ret = icc_set_bw(qcom->icc_path_ddr,
+ USB_MEMORY_AVG_SS_BW, USB_MEMORY_PEAK_SS_BW);
+ else
+ ret = icc_set_bw(qcom->icc_path_ddr,
+ USB_MEMORY_AVG_HS_BW, USB_MEMORY_PEAK_HS_BW);
+
+ if (ret) {
+ dev_err(dev, "failed to set bandwidth for usb-ddr path: %d\n", ret);
+ return ret;
+ }
+
+ ret = icc_set_bw(qcom->icc_path_apps,
+ APPS_USB_AVG_BW, APPS_USB_PEAK_BW);
+ if (ret) {
+ dev_err(dev, "failed to set bandwidth for apps-usb path: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+/**
+ * dwc3_qcom_interconnect_exit() - Release interconnect path handles
+ * @qcom: Pointer to the concerned usb core.
+ *
+ * This function is used to release interconnect path handle.
+ */
+static void dwc3_qcom_interconnect_exit(struct dwc3_qcom *qcom)
+{
+ icc_put(qcom->icc_path_ddr);
+ icc_put(qcom->icc_path_apps);
+}
+
static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom)
{
if (qcom->hs_phy_irq) {
@@ -239,7 +340,7 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
static int dwc3_qcom_suspend(struct dwc3_qcom *qcom)
{
u32 val;
- int i;
+ int i, ret;
if (qcom->is_suspended)
return 0;
@@ -251,6 +352,10 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom)
for (i = qcom->num_clocks - 1; i >= 0; i--)
clk_disable_unprepare(qcom->clks[i]);
+ ret = dwc3_qcom_interconnect_disable(qcom);
+ if (ret)
+ dev_warn(qcom->dev, "failed to disable interconnect: %d\n", ret);
+
qcom->is_suspended = true;
dwc3_qcom_enable_interrupts(qcom);
@@ -276,6 +381,10 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom)
}
}
+ ret = dwc3_qcom_interconnect_enable(qcom);
+ if (ret)
+ dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret);
+
/* Clear existing events from PHY related to L2 in/out */
dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG,
PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK);
@@ -638,6 +747,10 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
goto depopulate;
}
+ ret = dwc3_qcom_interconnect_init(qcom);
+ if (ret)
+ goto depopulate;
+
qcom->mode = usb_get_dr_mode(&qcom->dwc3->dev);
/* enable vbus override for device mode */
@@ -647,7 +760,7 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
/* register extcon to override sw_vbus on Vbus change later */
ret = dwc3_qcom_register_extcon(qcom);
if (ret)
- goto depopulate;
+ goto interconnect_exit;
device_init_wakeup(&pdev->dev, 1);
qcom->is_suspended = false;
@@ -657,6 +770,8 @@ static int dwc3_qcom_probe(struct platform_device *pdev)
return 0;
+interconnect_exit:
+ dwc3_qcom_interconnect_exit(qcom);
depopulate:
if (np)
of_platform_depopulate(&pdev->dev);
@@ -687,6 +802,7 @@ static int dwc3_qcom_remove(struct platform_device *pdev)
}
qcom->num_clocks = 0;
+ dwc3_qcom_interconnect_exit(qcom);
reset_control_assert(qcom->resets);
pm_runtime_allow(dev);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Adding maximum speed property for DWC3 USB node which can be used
for setting interconnect bandwidth.
Signed-off-by: Sandeep Maheswaram <[email protected]>
Reviewed-by: Matthias Kaehlcke <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 16df08d..3fe759b6 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -2656,6 +2656,7 @@
snps,dis_enblslpm_quirk;
phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
phy-names = "usb2-phy", "usb3-phy";
+ maximum-speed = "super-speed";
};
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
On Mon, Jul 27, 2020 at 10:36:36PM +0530, Sandeep Maheswaram wrote:
> Add interconnect support in dwc3-qcom driver to vote for bus
> bandwidth.
>
> This requires for two different paths - from USB to
> DDR. The other is from APPS to USB.
>
> Signed-off-by: Sandeep Maheswaram <[email protected]>
> Signed-off-by: Chandana Kishori Chiluveru <[email protected]>
Reviewed-by: Matthias Kaehlcke <[email protected]>
Hi Felipe,
On 7/28/2020 12:50 AM, Matthias Kaehlcke wrote:
> On Mon, Jul 27, 2020 at 10:36:36PM +0530, Sandeep Maheswaram wrote:
>> Add interconnect support in dwc3-qcom driver to vote for bus
>> bandwidth.
>>
>> This requires for two different paths - from USB to
>> DDR. The other is from APPS to USB.
>>
>> Signed-off-by: Sandeep Maheswaram <[email protected]>
>> Signed-off-by: Chandana Kishori Chiluveru <[email protected]>
> Reviewed-by: Matthias Kaehlcke <[email protected]>
Please ack if you are ok with this patch.
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
"Sandeep Maheswaram (Temp)" <[email protected]> writes:
> Hi Felipe,
>
> On 7/28/2020 12:50 AM, Matthias Kaehlcke wrote:
>> On Mon, Jul 27, 2020 at 10:36:36PM +0530, Sandeep Maheswaram wrote:
>>> Add interconnect support in dwc3-qcom driver to vote for bus
>>> bandwidth.
>>>
>>> This requires for two different paths - from USB to
>>> DDR. The other is from APPS to USB.
>>>
>>> Signed-off-by: Sandeep Maheswaram <[email protected]>
>>> Signed-off-by: Chandana Kishori Chiluveru <[email protected]>
>> Reviewed-by: Matthias Kaehlcke <[email protected]>
> Please ack if you are ok with this patch.
What's the plan to get this upstream? Should I take dwc3-qcom patch and
ignore the rest? Is there a hard-dependency on something else?
--
balbi
Hi
On 8/12/2020 12:27 PM, Felipe Balbi wrote:
> "Sandeep Maheswaram (Temp)" <[email protected]> writes:
>
>> Hi Felipe,
>>
>> On 7/28/2020 12:50 AM, Matthias Kaehlcke wrote:
>>> On Mon, Jul 27, 2020 at 10:36:36PM +0530, Sandeep Maheswaram wrote:
>>>> Add interconnect support in dwc3-qcom driver to vote for bus
>>>> bandwidth.
>>>>
>>>> This requires for two different paths - from USB to
>>>> DDR. The other is from APPS to USB.
>>>>
>>>> Signed-off-by: Sandeep Maheswaram <[email protected]>
>>>> Signed-off-by: Chandana Kishori Chiluveru <[email protected]>
>>> Reviewed-by: Matthias Kaehlcke <[email protected]>
>> Please ack if you are ok with this patch.
> What's the plan to get this upstream? Should I take dwc3-qcom patch and
> ignore the rest? Is there a hard-dependency on something else?
Yes take dwc3-qcom patch only,the dt change is already in linux-next.
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
"Sandeep Maheswaram (Temp)" <[email protected]> writes:
> Hi
>
> On 8/12/2020 12:27 PM, Felipe Balbi wrote:
>> "Sandeep Maheswaram (Temp)" <[email protected]> writes:
>>
>>> Hi Felipe,
>>>
>>> On 7/28/2020 12:50 AM, Matthias Kaehlcke wrote:
>>>> On Mon, Jul 27, 2020 at 10:36:36PM +0530, Sandeep Maheswaram wrote:
>>>>> Add interconnect support in dwc3-qcom driver to vote for bus
>>>>> bandwidth.
>>>>>
>>>>> This requires for two different paths - from USB to
>>>>> DDR. The other is from APPS to USB.
>>>>>
>>>>> Signed-off-by: Sandeep Maheswaram <[email protected]>
>>>>> Signed-off-by: Chandana Kishori Chiluveru <[email protected]>
>>>> Reviewed-by: Matthias Kaehlcke <[email protected]>
>>> Please ack if you are ok with this patch.
>> What's the plan to get this upstream? Should I take dwc3-qcom patch and
>> ignore the rest? Is there a hard-dependency on something else?
> Yes take dwc3-qcom patch only,the dt change is already in linux-next.
Thanks for confirming :-)
--
balbi