This series are based on 5.8-rc1 and we provide four i2c patches
to support mt8192 SoC.
Main changes compared to v1:
--modify the commit with access more than 8GB dram
--add Reviewed-by and Acked-by from Yingjoe, Matthias and Rob
Qii Wang (4):
i2c: mediatek: Add apdma sync in i2c driver
i2c: mediatek: Add access to more than 8GB dram in i2c driver
dt-bindings: i2c: update bindings for MT8192 SoC
i2c: mediatek: Add i2c compatible for MediaTek MT8192
.../devicetree/bindings/i2c/i2c-mt65xx.txt | 1 +
drivers/i2c/busses/i2c-mt65xx.c | 76 +++++++++++++++-------
2 files changed, 53 insertions(+), 24 deletions(-)
--
1.9.1
Newer MTK chip support more than 8GB of dram. Replace support_33bits
with more general dma_max_support and remove mtk_i2c_set_4g_mode.
Signed-off-by: Qii Wang <[email protected]>
---
drivers/i2c/busses/i2c-mt65xx.c | 38 +++++++++++++++++---------------------
1 file changed, 17 insertions(+), 21 deletions(-)
diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index e6b984a..49777a6 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -204,11 +204,11 @@ struct mtk_i2c_compatible {
unsigned char dcm: 1;
unsigned char auto_restart: 1;
unsigned char aux_len_reg: 1;
- unsigned char support_33bits: 1;
unsigned char timing_adjust: 1;
unsigned char dma_sync: 1;
unsigned char ltiming_adjust: 1;
unsigned char apdma_sync: 1;
+ unsigned char max_dma_support;
};
struct mtk_i2c_ac_timing {
@@ -311,11 +311,11 @@ struct i2c_spec_values {
.dcm = 1,
.auto_restart = 1,
.aux_len_reg = 1,
- .support_33bits = 1,
.timing_adjust = 1,
.dma_sync = 0,
.ltiming_adjust = 0,
.apdma_sync = 0,
+ .max_dma_support = 33,
};
static const struct mtk_i2c_compatible mt6577_compat = {
@@ -325,11 +325,11 @@ struct i2c_spec_values {
.dcm = 1,
.auto_restart = 0,
.aux_len_reg = 0,
- .support_33bits = 0,
.timing_adjust = 0,
.dma_sync = 0,
.ltiming_adjust = 0,
.apdma_sync = 0,
+ .max_dma_support = 32,
};
static const struct mtk_i2c_compatible mt6589_compat = {
@@ -339,11 +339,11 @@ struct i2c_spec_values {
.dcm = 0,
.auto_restart = 0,
.aux_len_reg = 0,
- .support_33bits = 0,
.timing_adjust = 0,
.dma_sync = 0,
.ltiming_adjust = 0,
.apdma_sync = 0,
+ .max_dma_support = 32,
};
static const struct mtk_i2c_compatible mt7622_compat = {
@@ -353,11 +353,11 @@ struct i2c_spec_values {
.dcm = 1,
.auto_restart = 1,
.aux_len_reg = 1,
- .support_33bits = 0,
.timing_adjust = 0,
.dma_sync = 0,
.ltiming_adjust = 0,
.apdma_sync = 0,
+ .max_dma_support = 32,
};
static const struct mtk_i2c_compatible mt8173_compat = {
@@ -366,11 +366,11 @@ struct i2c_spec_values {
.dcm = 1,
.auto_restart = 1,
.aux_len_reg = 1,
- .support_33bits = 1,
.timing_adjust = 0,
.dma_sync = 0,
.ltiming_adjust = 0,
.apdma_sync = 0,
+ .max_dma_support = 33,
};
static const struct mtk_i2c_compatible mt8183_compat = {
@@ -380,11 +380,11 @@ struct i2c_spec_values {
.dcm = 0,
.auto_restart = 1,
.aux_len_reg = 1,
- .support_33bits = 1,
.timing_adjust = 1,
.dma_sync = 1,
.ltiming_adjust = 1,
.apdma_sync = 0,
+ .max_dma_support = 33,
};
static const struct of_device_id mtk_i2c_of_match[] = {
@@ -796,11 +796,6 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
return 0;
}
-static inline u32 mtk_i2c_set_4g_mode(dma_addr_t addr)
-{
- return (addr & BIT_ULL(32)) ? I2C_DMA_4G_MODE : I2C_DMA_CLR_FLAG;
-}
-
static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
int num, int left_num)
{
@@ -885,8 +880,8 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
return -ENOMEM;
}
- if (i2c->dev_comp->support_33bits) {
- reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
+ if (i2c->dev_comp->max_dma_support > 32) {
+ reg_4g_mode = upper_32_bits(rpaddr);
writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
}
@@ -908,8 +903,8 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
return -ENOMEM;
}
- if (i2c->dev_comp->support_33bits) {
- reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
+ if (i2c->dev_comp->max_dma_support > 32) {
+ reg_4g_mode = upper_32_bits(wpaddr);
writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
}
@@ -954,11 +949,11 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
return -ENOMEM;
}
- if (i2c->dev_comp->support_33bits) {
- reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
+ if (i2c->dev_comp->max_dma_support > 32) {
+ reg_4g_mode = upper_32_bits(wpaddr);
writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
- reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
+ reg_4g_mode = upper_32_bits(rpaddr);
writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
}
@@ -1232,8 +1227,9 @@ static int mtk_i2c_probe(struct platform_device *pdev)
return -EINVAL;
}
- if (i2c->dev_comp->support_33bits) {
- ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(33));
+ if (i2c->dev_comp->max_dma_support > 32) {
+ ret = dma_set_mask(&pdev->dev,
+ DMA_BIT_MASK(i2c->dev_comp->max_dma_support));
if (ret) {
dev_err(&pdev->dev, "dma_set_mask return error.\n");
return ret;
--
1.9.1
Add i2c compatible for MT8192. Compare to MT8183 i2c controller,
MT8192 support more then 8GB DMA mode.
Signed-off-by: Qii Wang <[email protected]>
---
drivers/i2c/busses/i2c-mt65xx.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index 49777a6..dbf31eb 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -387,6 +387,20 @@ struct i2c_spec_values {
.max_dma_support = 33,
};
+static const struct mtk_i2c_compatible mt8192_compat = {
+ .quirks = &mt8183_i2c_quirks,
+ .regs = mt_i2c_regs_v2,
+ .pmic_i2c = 0,
+ .dcm = 0,
+ .auto_restart = 1,
+ .aux_len_reg = 1,
+ .timing_adjust = 1,
+ .dma_sync = 1,
+ .ltiming_adjust = 1,
+ .apdma_sync = 1,
+ .max_dma_support = 36,
+};
+
static const struct of_device_id mtk_i2c_of_match[] = {
{ .compatible = "mediatek,mt2712-i2c", .data = &mt2712_compat },
{ .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
@@ -394,6 +408,7 @@ struct i2c_spec_values {
{ .compatible = "mediatek,mt7622-i2c", .data = &mt7622_compat },
{ .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
{ .compatible = "mediatek,mt8183-i2c", .data = &mt8183_compat },
+ { .compatible = "mediatek,mt8192-i2c", .data = &mt8192_compat },
{}
};
MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
--
1.9.1
Add a DT binding documentation for the MT8192 soc.
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Qii Wang <[email protected]>
---
Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt
index 88b71c1..7f0194f 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.txt
@@ -14,6 +14,7 @@ Required properties:
"mediatek,mt7629-i2c", "mediatek,mt2712-i2c": for MediaTek MT7629
"mediatek,mt8173-i2c": for MediaTek MT8173
"mediatek,mt8183-i2c": for MediaTek MT8183
+ "mediatek,mt8192-i2c": for MediaTek MT8192
"mediatek,mt8516-i2c", "mediatek,mt2712-i2c": for MediaTek MT8516
- reg: physical base address of the controller and dma base, length of memory
mapped region.
--
1.9.1
With the apdma remove hand-shake signal, it need to keep i2c and
apdma in sync manually.
Reviewed-by: Yingjoe Chen <[email protected]>
Reviewed-by: Matthias Brugger <[email protected]>
Signed-off-by: Qii Wang <[email protected]>
---
drivers/i2c/busses/i2c-mt65xx.c | 23 ++++++++++++++++++++---
1 file changed, 20 insertions(+), 3 deletions(-)
diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
index deef69e..e6b984a 100644
--- a/drivers/i2c/busses/i2c-mt65xx.c
+++ b/drivers/i2c/busses/i2c-mt65xx.c
@@ -48,6 +48,9 @@
#define I2C_DMA_CON_TX 0x0000
#define I2C_DMA_CON_RX 0x0001
+#define I2C_DMA_ASYNC_MODE 0x0004
+#define I2C_DMA_SKIP_CONFIG 0x0010
+#define I2C_DMA_DIR_CHANGE 0x0200
#define I2C_DMA_START_EN 0x0001
#define I2C_DMA_INT_FLAG_NONE 0x0000
#define I2C_DMA_CLR_FLAG 0x0000
@@ -205,6 +208,7 @@ struct mtk_i2c_compatible {
unsigned char timing_adjust: 1;
unsigned char dma_sync: 1;
unsigned char ltiming_adjust: 1;
+ unsigned char apdma_sync: 1;
};
struct mtk_i2c_ac_timing {
@@ -311,6 +315,7 @@ struct i2c_spec_values {
.timing_adjust = 1,
.dma_sync = 0,
.ltiming_adjust = 0,
+ .apdma_sync = 0,
};
static const struct mtk_i2c_compatible mt6577_compat = {
@@ -324,6 +329,7 @@ struct i2c_spec_values {
.timing_adjust = 0,
.dma_sync = 0,
.ltiming_adjust = 0,
+ .apdma_sync = 0,
};
static const struct mtk_i2c_compatible mt6589_compat = {
@@ -337,6 +343,7 @@ struct i2c_spec_values {
.timing_adjust = 0,
.dma_sync = 0,
.ltiming_adjust = 0,
+ .apdma_sync = 0,
};
static const struct mtk_i2c_compatible mt7622_compat = {
@@ -350,6 +357,7 @@ struct i2c_spec_values {
.timing_adjust = 0,
.dma_sync = 0,
.ltiming_adjust = 0,
+ .apdma_sync = 0,
};
static const struct mtk_i2c_compatible mt8173_compat = {
@@ -362,6 +370,7 @@ struct i2c_spec_values {
.timing_adjust = 0,
.dma_sync = 0,
.ltiming_adjust = 0,
+ .apdma_sync = 0,
};
static const struct mtk_i2c_compatible mt8183_compat = {
@@ -375,6 +384,7 @@ struct i2c_spec_values {
.timing_adjust = 1,
.dma_sync = 1,
.ltiming_adjust = 1,
+ .apdma_sync = 0,
};
static const struct of_device_id mtk_i2c_of_match[] = {
@@ -798,6 +808,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
u16 start_reg;
u16 control_reg;
u16 restart_flag = 0;
+ u16 dma_sync = 0;
u32 reg_4g_mode;
u8 *dma_rd_buf = NULL;
u8 *dma_wr_buf = NULL;
@@ -851,10 +862,16 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
mtk_i2c_writew(i2c, num, OFFSET_TRANSAC_LEN);
}
+ if (i2c->dev_comp->apdma_sync) {
+ dma_sync = I2C_DMA_SKIP_CONFIG | I2C_DMA_ASYNC_MODE;
+ if (i2c->op == I2C_MASTER_WRRD)
+ dma_sync |= I2C_DMA_DIR_CHANGE;
+ }
+
/* Prepare buffer data to start transfer */
if (i2c->op == I2C_MASTER_RD) {
writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
- writel(I2C_DMA_CON_RX, i2c->pdmabase + OFFSET_CON);
+ writel(I2C_DMA_CON_RX | dma_sync, i2c->pdmabase + OFFSET_CON);
dma_rd_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
if (!dma_rd_buf)
@@ -877,7 +894,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN);
} else if (i2c->op == I2C_MASTER_WR) {
writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
- writel(I2C_DMA_CON_TX, i2c->pdmabase + OFFSET_CON);
+ writel(I2C_DMA_CON_TX | dma_sync, i2c->pdmabase + OFFSET_CON);
dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
if (!dma_wr_buf)
@@ -900,7 +917,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
} else {
writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG);
- writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_CON);
+ writel(I2C_DMA_CLR_FLAG | dma_sync, i2c->pdmabase + OFFSET_CON);
dma_wr_buf = i2c_get_dma_safe_msg_buf(msgs, 1);
if (!dma_wr_buf)
--
1.9.1
On 28/07/2020 14:30, Qii Wang wrote:
> Newer MTK chip support more than 8GB of dram. Replace support_33bits
> with more general dma_max_support and remove mtk_i2c_set_4g_mode.
>
> Signed-off-by: Qii Wang <[email protected]>
> ---
> drivers/i2c/busses/i2c-mt65xx.c | 38 +++++++++++++++++---------------------
> 1 file changed, 17 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
> index e6b984a..49777a6 100644
> --- a/drivers/i2c/busses/i2c-mt65xx.c
> +++ b/drivers/i2c/busses/i2c-mt65xx.c
> @@ -204,11 +204,11 @@ struct mtk_i2c_compatible {
> unsigned char dcm: 1;
> unsigned char auto_restart: 1;
> unsigned char aux_len_reg: 1;
> - unsigned char support_33bits: 1;
> unsigned char timing_adjust: 1;
> unsigned char dma_sync: 1;
> unsigned char ltiming_adjust: 1;
> unsigned char apdma_sync: 1;
> + unsigned char max_dma_support;
> };
>
> struct mtk_i2c_ac_timing {
> @@ -311,11 +311,11 @@ struct i2c_spec_values {
> .dcm = 1,
> .auto_restart = 1,
> .aux_len_reg = 1,
> - .support_33bits = 1,
> .timing_adjust = 1,
> .dma_sync = 0,
> .ltiming_adjust = 0,
> .apdma_sync = 0,
> + .max_dma_support = 33,
> };
>
> static const struct mtk_i2c_compatible mt6577_compat = {
> @@ -325,11 +325,11 @@ struct i2c_spec_values {
> .dcm = 1,
> .auto_restart = 0,
> .aux_len_reg = 0,
> - .support_33bits = 0,
> .timing_adjust = 0,
> .dma_sync = 0,
> .ltiming_adjust = 0,
> .apdma_sync = 0,
> + .max_dma_support = 32,
> };
>
> static const struct mtk_i2c_compatible mt6589_compat = {
> @@ -339,11 +339,11 @@ struct i2c_spec_values {
> .dcm = 0,
> .auto_restart = 0,
> .aux_len_reg = 0,
> - .support_33bits = 0,
> .timing_adjust = 0,
> .dma_sync = 0,
> .ltiming_adjust = 0,
> .apdma_sync = 0,
> + .max_dma_support = 32,
> };
>
> static const struct mtk_i2c_compatible mt7622_compat = {
> @@ -353,11 +353,11 @@ struct i2c_spec_values {
> .dcm = 1,
> .auto_restart = 1,
> .aux_len_reg = 1,
> - .support_33bits = 0,
> .timing_adjust = 0,
> .dma_sync = 0,
> .ltiming_adjust = 0,
> .apdma_sync = 0,
> + .max_dma_support = 32,
> };
>
> static const struct mtk_i2c_compatible mt8173_compat = {
> @@ -366,11 +366,11 @@ struct i2c_spec_values {
> .dcm = 1,
> .auto_restart = 1,
> .aux_len_reg = 1,
> - .support_33bits = 1,
> .timing_adjust = 0,
> .dma_sync = 0,
> .ltiming_adjust = 0,
> .apdma_sync = 0,
> + .max_dma_support = 33,
> };
>
> static const struct mtk_i2c_compatible mt8183_compat = {
> @@ -380,11 +380,11 @@ struct i2c_spec_values {
> .dcm = 0,
> .auto_restart = 1,
> .aux_len_reg = 1,
> - .support_33bits = 1,
> .timing_adjust = 1,
> .dma_sync = 1,
> .ltiming_adjust = 1,
> .apdma_sync = 0,
> + .max_dma_support = 33,
> };
>
> static const struct of_device_id mtk_i2c_of_match[] = {
> @@ -796,11 +796,6 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
> return 0;
> }
>
> -static inline u32 mtk_i2c_set_4g_mode(dma_addr_t addr)
> -{
> - return (addr & BIT_ULL(32)) ? I2C_DMA_4G_MODE : I2C_DMA_CLR_FLAG;
I think you missed my comment in the last version:
I2C_DMA_4G_MODE is no longer needed, you can delete it.
Regards,
Matthias
> -}
> -
> static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> int num, int left_num)
> {
> @@ -885,8 +880,8 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> return -ENOMEM;
> }
>
> - if (i2c->dev_comp->support_33bits) {
> - reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
> + if (i2c->dev_comp->max_dma_support > 32) {
> + reg_4g_mode = upper_32_bits(rpaddr);
> writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
> }
>
> @@ -908,8 +903,8 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> return -ENOMEM;
> }
>
> - if (i2c->dev_comp->support_33bits) {
> - reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
> + if (i2c->dev_comp->max_dma_support > 32) {
> + reg_4g_mode = upper_32_bits(wpaddr);
> writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
> }
>
> @@ -954,11 +949,11 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> return -ENOMEM;
> }
>
> - if (i2c->dev_comp->support_33bits) {
> - reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
> + if (i2c->dev_comp->max_dma_support > 32) {
> + reg_4g_mode = upper_32_bits(wpaddr);
> writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
>
> - reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
> + reg_4g_mode = upper_32_bits(rpaddr);
> writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
> }
>
> @@ -1232,8 +1227,9 @@ static int mtk_i2c_probe(struct platform_device *pdev)
> return -EINVAL;
> }
>
> - if (i2c->dev_comp->support_33bits) {
> - ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(33));
> + if (i2c->dev_comp->max_dma_support > 32) {
> + ret = dma_set_mask(&pdev->dev,
> + DMA_BIT_MASK(i2c->dev_comp->max_dma_support));
> if (ret) {
> dev_err(&pdev->dev, "dma_set_mask return error.\n");
> return ret;
>
On Wed, 2020-07-29 at 09:59 +0200, Matthias Brugger wrote:
>
> On 28/07/2020 14:30, Qii Wang wrote:
> > Newer MTK chip support more than 8GB of dram. Replace support_33bits
> > with more general dma_max_support and remove mtk_i2c_set_4g_mode.
> >
> > Signed-off-by: Qii Wang <[email protected]>
> > ---
> > drivers/i2c/busses/i2c-mt65xx.c | 38 +++++++++++++++++---------------------
> > 1 file changed, 17 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c
> > index e6b984a..49777a6 100644
> > --- a/drivers/i2c/busses/i2c-mt65xx.c
> > +++ b/drivers/i2c/busses/i2c-mt65xx.c
> > @@ -204,11 +204,11 @@ struct mtk_i2c_compatible {
> > unsigned char dcm: 1;
> > unsigned char auto_restart: 1;
> > unsigned char aux_len_reg: 1;
> > - unsigned char support_33bits: 1;
> > unsigned char timing_adjust: 1;
> > unsigned char dma_sync: 1;
> > unsigned char ltiming_adjust: 1;
> > unsigned char apdma_sync: 1;
> > + unsigned char max_dma_support;
> > };
> >
> > struct mtk_i2c_ac_timing {
> > @@ -311,11 +311,11 @@ struct i2c_spec_values {
> > .dcm = 1,
> > .auto_restart = 1,
> > .aux_len_reg = 1,
> > - .support_33bits = 1,
> > .timing_adjust = 1,
> > .dma_sync = 0,
> > .ltiming_adjust = 0,
> > .apdma_sync = 0,
> > + .max_dma_support = 33,
> > };
> >
> > static const struct mtk_i2c_compatible mt6577_compat = {
> > @@ -325,11 +325,11 @@ struct i2c_spec_values {
> > .dcm = 1,
> > .auto_restart = 0,
> > .aux_len_reg = 0,
> > - .support_33bits = 0,
> > .timing_adjust = 0,
> > .dma_sync = 0,
> > .ltiming_adjust = 0,
> > .apdma_sync = 0,
> > + .max_dma_support = 32,
> > };
> >
> > static const struct mtk_i2c_compatible mt6589_compat = {
> > @@ -339,11 +339,11 @@ struct i2c_spec_values {
> > .dcm = 0,
> > .auto_restart = 0,
> > .aux_len_reg = 0,
> > - .support_33bits = 0,
> > .timing_adjust = 0,
> > .dma_sync = 0,
> > .ltiming_adjust = 0,
> > .apdma_sync = 0,
> > + .max_dma_support = 32,
> > };
> >
> > static const struct mtk_i2c_compatible mt7622_compat = {
> > @@ -353,11 +353,11 @@ struct i2c_spec_values {
> > .dcm = 1,
> > .auto_restart = 1,
> > .aux_len_reg = 1,
> > - .support_33bits = 0,
> > .timing_adjust = 0,
> > .dma_sync = 0,
> > .ltiming_adjust = 0,
> > .apdma_sync = 0,
> > + .max_dma_support = 32,
> > };
> >
> > static const struct mtk_i2c_compatible mt8173_compat = {
> > @@ -366,11 +366,11 @@ struct i2c_spec_values {
> > .dcm = 1,
> > .auto_restart = 1,
> > .aux_len_reg = 1,
> > - .support_33bits = 1,
> > .timing_adjust = 0,
> > .dma_sync = 0,
> > .ltiming_adjust = 0,
> > .apdma_sync = 0,
> > + .max_dma_support = 33,
> > };
> >
> > static const struct mtk_i2c_compatible mt8183_compat = {
> > @@ -380,11 +380,11 @@ struct i2c_spec_values {
> > .dcm = 0,
> > .auto_restart = 1,
> > .aux_len_reg = 1,
> > - .support_33bits = 1,
> > .timing_adjust = 1,
> > .dma_sync = 1,
> > .ltiming_adjust = 1,
> > .apdma_sync = 0,
> > + .max_dma_support = 33,
> > };
> >
> > static const struct of_device_id mtk_i2c_of_match[] = {
> > @@ -796,11 +796,6 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk)
> > return 0;
> > }
> >
> > -static inline u32 mtk_i2c_set_4g_mode(dma_addr_t addr)
> > -{
> > - return (addr & BIT_ULL(32)) ? I2C_DMA_4G_MODE : I2C_DMA_CLR_FLAG;
>
> I think you missed my comment in the last version:
> I2C_DMA_4G_MODE is no longer needed, you can delete it.
>
> Regards,
> Matthias
>
Sorry for missing that comment, I will remove it.
Thank you for your comments and reminders.
> > -}
> > -
> > static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> > int num, int left_num)
> > {
> > @@ -885,8 +880,8 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> > return -ENOMEM;
> > }
> >
> > - if (i2c->dev_comp->support_33bits) {
> > - reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
> > + if (i2c->dev_comp->max_dma_support > 32) {
> > + reg_4g_mode = upper_32_bits(rpaddr);
> > writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
> > }
> >
> > @@ -908,8 +903,8 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> > return -ENOMEM;
> > }
> >
> > - if (i2c->dev_comp->support_33bits) {
> > - reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
> > + if (i2c->dev_comp->max_dma_support > 32) {
> > + reg_4g_mode = upper_32_bits(wpaddr);
> > writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
> > }
> >
> > @@ -954,11 +949,11 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
> > return -ENOMEM;
> > }
> >
> > - if (i2c->dev_comp->support_33bits) {
> > - reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
> > + if (i2c->dev_comp->max_dma_support > 32) {
> > + reg_4g_mode = upper_32_bits(wpaddr);
> > writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
> >
> > - reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
> > + reg_4g_mode = upper_32_bits(rpaddr);
> > writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
> > }
> >
> > @@ -1232,8 +1227,9 @@ static int mtk_i2c_probe(struct platform_device *pdev)
> > return -EINVAL;
> > }
> >
> > - if (i2c->dev_comp->support_33bits) {
> > - ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(33));
> > + if (i2c->dev_comp->max_dma_support > 32) {
> > + ret = dma_set_mask(&pdev->dev,
> > + DMA_BIT_MASK(i2c->dev_comp->max_dma_support));
> > if (ret) {
> > dev_err(&pdev->dev, "dma_set_mask return error.\n");
> > return ret;
> >
On Tue, 2020-07-28 at 20:30 +0800, Qii Wang wrote:
> Newer MTK chip support more than 8GB of dram. Replace support_33bits
> with more general dma_max_support and remove mtk_i2c_set_4g_mode.
>
> Signed-off-by: Qii Wang <[email protected]>
Qii,
After you remove I2C_DMA_4G_MODE Matthias mentioned, you can have:
Reviewed-by: Yingjoe Chen <[email protected]>
Joe.C
> > > -static inline u32 mtk_i2c_set_4g_mode(dma_addr_t addr)
> > > -{
> > > - return (addr & BIT_ULL(32)) ? I2C_DMA_4G_MODE : I2C_DMA_CLR_FLAG;
> >
> > I think you missed my comment in the last version:
> > I2C_DMA_4G_MODE is no longer needed, you can delete it.
> >
> > Regards,
> > Matthias
> >
>
> Sorry for missing that comment, I will remove it.
> Thank you for your comments and reminders.
If you send it real soon, I can still include it for 5.9.
(and please guys, shorten mails to the relevant parts)