This series is based on v5.8-rc1
change since v16:
- Introduce hierarchical scpsys device node to show the dependency between each power domain.
And could be more clearly to group subsys clocks into power domain sub node.
change since v15:
- remove unneeded error log in [PATCH 06/11]
changes since v14:
- fix commit message typo
- use property name "mediatek,smi" for smi phandle
changes since v13:
- document optional property "smi-comm"
- move defines in scpsyc.h to mtk-scpsys.c directly
- minor coding sytle fixes
change since v12:
- separate the fix of comma at the end into a new patch [PATCH 09/11]
changes since v11:
- re-order patches "Remove infracfg misc driver support" and "Add multiple step bus protection"
- add cap MTK_SCPD_SRAM_ISO for extra sram control
- minor coding sytle fixes and reword commit messages
changes since v10:
- squash PATCH 04 and PATCH 06 in v9 into its previous patch
- add "ignore_clr_ack" for multiple step bus protection control to have a clean definition of power domain data
- keep the mask register bit definitions and do the same for MT8183
changes since v9:
- add new PATCH 04 and PATCH 06 to replace by new method for all compatibles
- add new PATCH 07 to remove infracfg misc driver
- minor coding sytle fix
changes since v7:
- reword in binding document [PATCH 02/14]
- fix error return checking bug in subsys clock control [PATCH 10/14]
- add power domains properity to mfgcfg patch [PATCH 14/14] from
https://patchwork.kernel.org/patch/11126199/
changes since v6:
- remove the patch of SPDX license identifier because it's already fixed
changes since v5:
- fix documentation in [PATCH 04/14]
- remove useless variable checking and reuse API of clock control in [PATCH 06/14]
- coding style fix of bus protection control in [PATCH 08/14]
- fix naming of new added data in [PATCH 09/14]
- small refactor of multiple step bus protection control in [PATCH 10/14]
changes since v4:
- add property to mt8183 smi-common
- seperate refactor patches and new add function
- add power controller device node
Weiyi Lu (12):
dt-bindings: mediatek: Add property to mt8183 smi-common
soc: mediatek: Add basic_clk_name to scp_power_data
soc: mediatek: Remove infracfg misc driver support
soc: mediatek: Add multiple step bus protection control
dt-bindings: soc: Add MT8183 power dt-bindings
soc: mediatek: Add support for hierarchical scpsys device node
soc: mediatek: Add subsys clock control for bus protection
soc: mediatek: Add extra sram control
soc: mediatek: Add MT8183 scpsys support
soc: mediatek: Add a comma at the end
arm64: dts: Add power controller device node of MT8183
arm64: dts: Add power-domains property to mfgcfg
.../mediatek,smi-common.txt | 2 +-
.../bindings/soc/mediatek/scpsys.txt | 81 +-
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 124 +++
drivers/soc/mediatek/Kconfig | 10 -
drivers/soc/mediatek/Makefile | 1 -
drivers/soc/mediatek/mtk-infracfg.c | 79 --
drivers/soc/mediatek/mtk-scpsys.c | 770 ++++++++++++++----
include/dt-bindings/power/mt8183-power.h | 26 +
include/linux/soc/mediatek/infracfg.h | 39 -
9 files changed, 845 insertions(+), 287 deletions(-)
delete mode 100644 drivers/soc/mediatek/mtk-infracfg.c
create mode 100644 include/dt-bindings/power/mt8183-power.h
delete mode 100644 include/linux/soc/mediatek/infracfg.h
Add power dt-bindings of MT8183.
Add an optional "mediatek,smi" property for phandle to smi-common
node for power controller.
Introduce properties for power domain sub nodes.
Signed-off-by: Weiyi Lu <[email protected]>
---
.../devicetree/bindings/soc/mediatek/scpsys.txt | 81 ++++++++++++++++++++--
include/dt-bindings/power/mt8183-power.h | 26 +++++++
2 files changed, 102 insertions(+), 5 deletions(-)
create mode 100644 include/dt-bindings/power/mt8183-power.h
diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
index 2bc3677..efe2025 100644
--- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
+++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
@@ -15,8 +15,9 @@ power/power-domain.yaml. It provides the power domains defined in
- include/dt-bindings/power/mt2701-power.h
- include/dt-bindings/power/mt2712-power.h
- include/dt-bindings/power/mt7622-power.h
+- include/dt-bindings/power/mt8183-power.h
-Required properties:
+Required properties for power controller:
- compatible: Should be one of:
- "mediatek,mt2701-scpsys"
- "mediatek,mt2712-scpsys"
@@ -27,12 +28,15 @@ Required properties:
- "mediatek,mt7623a-scpsys": For MT7623A SoC
- "mediatek,mt7629-scpsys", "mediatek,mt7622-scpsys": For MT7629 SoC
- "mediatek,mt8173-scpsys"
+ - "mediatek,mt8183-scpsys"
- #power-domain-cells: Must be 1
+- #address-cells: Should be 1
+- #size-cells: Should be 0
- reg: Address range of the SCPSYS unit
- infracfg: must contain a phandle to the infracfg controller
-- clock, clock-names: clocks according to the common clock binding.
- These are clocks which hardware needs to be
- enabled before enabling certain power domains.
+- clocks, clock-names: clocks according to the common clock binding.
+ These are clocks which hardware needs to be
+ enabled before enabling certain power domains.
Required clocks for MT2701 or MT7623: "mm", "mfg", "ethif"
Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec"
Required clocks for MT6765: MUX: "mm", "mfg"
@@ -43,8 +47,11 @@ Required properties:
Required clocks for MT7622 or MT7629: "hif_sel"
Required clocks for MT7623A: "ethif"
Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
+ Required clocks for MT8183: "audio", "audio1", "audio2", "mfg", "mm",
+ "cam", "isp", "vpu", "vpu1", "vpu2",
+ "vpu3";
-Optional properties:
+Optional properties for power controller:
- vdec-supply: Power supply for the vdec power domain
- venc-supply: Power supply for the venc power domain
- isp-supply: Power supply for the isp power domain
@@ -55,6 +62,16 @@ Optional properties:
- mfg_async-supply: Power supply for the mfg_async power domain
- mfg_2d-supply: Power supply for the mfg_2d power domain
- mfg-supply: Power supply for the mfg power domain
+- mediatek,smi : A phandle to the smi_common node
+
+Required properties for power domain sub nodes:
+- reg: index of the power domain, should use macros in:
+ "include/dt-bindings/power/mt8192-power.h" - for power domain of MT8192.
+
+Optional properties for power domain sub nodes:
+- clocks: clocks according to the common clock binding.
+ These are clocks which hardware needs to be enabled before
+ releasing the bus protection.
Example:
@@ -70,6 +87,60 @@ Example:
clock-names = "mfg", "mm", "venc", "venc_lt";
};
+Example(power domain sub node within power controller):
+
+ scpsys: power-controller@10006000 {
+ compatible = "mediatek,mt8183-scpsys", "syscon";
+ reg = <0 0x10006000 0 0x1000>;
+ clocks = <&topckgen CLK_TOP_MUX_MM>,
+ <&topckgen CLK_TOP_MUX_IPU_IF>,
+ <&topckgen CLK_TOP_MUX_DSP>,
+ <&topckgen CLK_TOP_MUX_DSP1>,
+ <&topckgen CLK_TOP_MUX_DSP2>;
+ clock-names = "mm", "vpu", "vpu1", "vpu2", "vpu3";
+ infracfg = <&infracfg>;
+ mediatek,smi = <&smi_common>;
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ conn@MT8183_POWER_DOMAIN_CONN {
+ reg = <MT8183_POWER_DOMAIN_CONN>;
+ };
+
+ disp@MT8183_POWER_DOMAIN_DISP {
+ reg = <MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_SMI_COMMON>,
+ <&mmsys CLK_MM_SMI_LARB0>,
+ <&mmsys CLK_MM_SMI_LARB1>,
+ <&mmsys CLK_MM_GALS_COMM0>,
+ <&mmsys CLK_MM_GALS_COMM1>,
+ <&mmsys CLK_MM_GALS_CCU2MM>,
+ <&mmsys CLK_MM_GALS_IPU12MM>,
+ <&mmsys CLK_MM_GALS_IMG2MM>,
+ <&mmsys CLK_MM_GALS_CAM2MM>,
+ <&mmsys CLK_MM_GALS_IPU2MM>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vpu_top@MT8183_POWER_DOMAIN_VPU_TOP {
+ reg = <MT8183_POWER_DOMAIN_VPU_TOP>;
+ clocks = <&ipu_conn CLK_IPU_CONN_IPU>,
+ <&ipu_conn CLK_IPU_CONN_AHB>,
+ <&ipu_conn CLK_IPU_CONN_AXI>,
+ <&ipu_conn CLK_IPU_CONN_ISP>,
+ <&ipu_conn CLK_IPU_CONN_CAM_ADL>,
+ <&ipu_conn CLK_IPU_CONN_IMG_ADL>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vpu_core0@MT8183_POWER_DOMAIN_VPU_CORE0 {
+ reg = <MT8183_POWER_DOMAIN_VPU_CORE0>;
+ };
+ };
+ };
+ };
+
Example consumer:
afe: mt8173-afe-pcm@11220000 {
diff --git a/include/dt-bindings/power/mt8183-power.h b/include/dt-bindings/power/mt8183-power.h
new file mode 100644
index 0000000..d1ab387
--- /dev/null
+++ b/include/dt-bindings/power/mt8183-power.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020 MediaTek Inc.
+ * Author: Weiyi Lu <[email protected]>
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT8183_POWER_H
+#define _DT_BINDINGS_POWER_MT8183_POWER_H
+
+#define MT8183_POWER_DOMAIN_AUDIO 0
+#define MT8183_POWER_DOMAIN_CONN 1
+#define MT8183_POWER_DOMAIN_MFG_ASYNC 2
+#define MT8183_POWER_DOMAIN_MFG 3
+#define MT8183_POWER_DOMAIN_MFG_CORE0 4
+#define MT8183_POWER_DOMAIN_MFG_CORE1 5
+#define MT8183_POWER_DOMAIN_MFG_2D 6
+#define MT8183_POWER_DOMAIN_DISP 7
+#define MT8183_POWER_DOMAIN_CAM 8
+#define MT8183_POWER_DOMAIN_ISP 9
+#define MT8183_POWER_DOMAIN_VDEC 10
+#define MT8183_POWER_DOMAIN_VENC 11
+#define MT8183_POWER_DOMAIN_VPU_TOP 12
+#define MT8183_POWER_DOMAIN_VPU_CORE0 13
+#define MT8183_POWER_DOMAIN_VPU_CORE1 14
+
+#endif /* _DT_BINDINGS_POWER_MT8183_POWER_H */
--
1.8.1.1.dirty
For the bus protection operations, some subsys clocks need to be enabled
before releasing the protection, and vice versa.
But those subsys clocks could only be controlled once its corresponding
power domain is turned on first.
In this patch, we add the subsys clock control into its relevant steps.
Signed-off-by: Weiyi Lu <[email protected]>
---
drivers/soc/mediatek/mtk-scpsys.c | 39 +++++++++++++++++++++++++++++++++++++--
1 file changed, 37 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index 502b66f..ec62143 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -7,6 +7,7 @@
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/mfd/syscon.h>
+#include <linux/of_clk.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
@@ -97,6 +98,7 @@
#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23)
#define MAX_CLKS 3
+#define MAX_SUBSYS_CLKS 10
#define MAX_STEPS 5
@@ -165,6 +167,7 @@ struct scp_domain {
struct generic_pm_domain genpd;
struct scp *scp;
struct clk *clk[MAX_CLKS];
+ struct clk *subsys_clk[MAX_SUBSYS_CLKS];
const struct scp_domain_data *data;
struct regulator *supply;
};
@@ -427,16 +430,22 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
val |= PWR_RST_B_BIT;
writel(val, ctl_addr);
- ret = scpsys_sram_enable(scpd, ctl_addr);
+ ret = scpsys_clk_enable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
if (ret < 0)
goto err_pwr_ack;
+ ret = scpsys_sram_enable(scpd, ctl_addr);
+ if (ret < 0)
+ goto err_sram;
+
ret = scpsys_bus_protect_disable(scpd);
if (ret < 0)
- goto err_pwr_ack;
+ goto err_sram;
return 0;
+err_sram:
+ scpsys_clk_disable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
err_pwr_ack:
scpsys_clk_disable(scpd->clk, MAX_CLKS);
err_clk:
@@ -463,6 +472,8 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
if (ret < 0)
goto out;
+ scpsys_clk_disable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
+
/* subsys power off */
val = readl(ctl_addr);
val |= PWR_ISO_BIT;
@@ -500,6 +511,24 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
return ret;
}
+static int init_subsys_clks(struct device_node *np,
+ struct clk **clk)
+{
+ int sub_clk_cnt = of_clk_get_parent_count(np);
+ int i;
+
+ BUG_ON(sub_clk_cnt > MAX_SUBSYS_CLKS);
+
+ for (i = 0; i < sub_clk_cnt; i++) {
+ clk[i] = of_clk_get(np, i);
+
+ if (IS_ERR(clk[i]))
+ return PTR_ERR(clk[i]);
+ }
+
+ return 0;
+}
+
static int init_basic_clks(struct platform_device *pdev, struct clk **clk,
const char * const *name)
{
@@ -533,11 +562,17 @@ static int scpsys_get_domain(struct platform_device *pdev, struct scp *scp,
struct device_node *sub;
u32 parent_id, child_id;
int ret;
+ struct scp_domain *scpd;
ret = scpsys_get_domain_id(node, &parent_id);
if (ret)
return ret;
+ scpd = &scp->domains[parent_id];
+ ret = init_subsys_clks(node, scpd->subsys_clk);
+ if (ret)
+ return ret;
+
for_each_child_of_node(node, sub) {
ret = scpsys_get_domain_id(sub, &child_id);
if (ret)
--
1.8.1.1.dirty
The functions provided by infracfg misc driver have no other user except
the scpsys driver so move those into scpsys driver directly.
And then, remove infracfg misc driver which is no longer being used.
BTW, in next patch, we're going to extend the bus protection functions
with more customized arguments.
Signed-off-by: Weiyi Lu <[email protected]>
Reviewed-by: Enric Balletbo i Serra <[email protected]>
---
drivers/soc/mediatek/Kconfig | 10 -----
drivers/soc/mediatek/Makefile | 1 -
drivers/soc/mediatek/mtk-infracfg.c | 79 -----------------------------------
drivers/soc/mediatek/mtk-scpsys.c | 66 +++++++++++++++++++++++++----
include/linux/soc/mediatek/infracfg.h | 39 -----------------
5 files changed, 57 insertions(+), 138 deletions(-)
delete mode 100644 drivers/soc/mediatek/mtk-infracfg.c
delete mode 100644 include/linux/soc/mediatek/infracfg.h
diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index 59a56cd..3f5e5cb 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -10,21 +10,12 @@ config MTK_CMDQ
depends on ARCH_MEDIATEK || COMPILE_TEST
select MAILBOX
select MTK_CMDQ_MBOX
- select MTK_INFRACFG
help
Say yes here to add support for the MediaTek Command Queue (CMDQ)
driver. The CMDQ is used to help read/write registers with critical
time limitation, such as updating display configuration during the
vblank.
-config MTK_INFRACFG
- bool "MediaTek INFRACFG Support"
- select REGMAP
- help
- Say yes here to add support for the MediaTek INFRACFG controller. The
- INFRACFG controller contains various infrastructure registers not
- directly associated to any device.
-
config MTK_PMIC_WRAP
tristate "MediaTek PMIC Wrapper Support"
depends on RESET_CONTROLLER
@@ -38,7 +29,6 @@ config MTK_SCPSYS
bool "MediaTek SCPSYS Support"
default ARCH_MEDIATEK
select REGMAP
- select MTK_INFRACFG
select PM_GENERIC_DOMAINS if PM
help
Say yes here to add support for the MediaTek SCPSYS power domain
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index 01f9f87..2afa7b9 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -1,6 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
-obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
diff --git a/drivers/soc/mediatek/mtk-infracfg.c b/drivers/soc/mediatek/mtk-infracfg.c
deleted file mode 100644
index 341c7ac..0000000
--- a/drivers/soc/mediatek/mtk-infracfg.c
+++ /dev/null
@@ -1,79 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2015 Pengutronix, Sascha Hauer <[email protected]>
- */
-
-#include <linux/export.h>
-#include <linux/jiffies.h>
-#include <linux/regmap.h>
-#include <linux/soc/mediatek/infracfg.h>
-#include <asm/processor.h>
-
-#define MTK_POLL_DELAY_US 10
-#define MTK_POLL_TIMEOUT (jiffies_to_usecs(HZ))
-
-#define INFRA_TOPAXI_PROTECTEN 0x0220
-#define INFRA_TOPAXI_PROTECTSTA1 0x0228
-#define INFRA_TOPAXI_PROTECTEN_SET 0x0260
-#define INFRA_TOPAXI_PROTECTEN_CLR 0x0264
-
-/**
- * mtk_infracfg_set_bus_protection - enable bus protection
- * @regmap: The infracfg regmap
- * @mask: The mask containing the protection bits to be enabled.
- * @reg_update: The boolean flag determines to set the protection bits
- * by regmap_update_bits with enable register(PROTECTEN) or
- * by regmap_write with set register(PROTECTEN_SET).
- *
- * This function enables the bus protection bits for disabled power
- * domains so that the system does not hang when some unit accesses the
- * bus while in power down.
- */
-int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask,
- bool reg_update)
-{
- u32 val;
- int ret;
-
- if (reg_update)
- regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask,
- mask);
- else
- regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask);
-
- ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1,
- val, (val & mask) == mask,
- MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
-
- return ret;
-}
-
-/**
- * mtk_infracfg_clear_bus_protection - disable bus protection
- * @regmap: The infracfg regmap
- * @mask: The mask containing the protection bits to be disabled.
- * @reg_update: The boolean flag determines to clear the protection bits
- * by regmap_update_bits with enable register(PROTECTEN) or
- * by regmap_write with clear register(PROTECTEN_CLR).
- *
- * This function disables the bus protection bits previously enabled with
- * mtk_infracfg_set_bus_protection.
- */
-
-int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask,
- bool reg_update)
-{
- int ret;
- u32 val;
-
- if (reg_update)
- regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0);
- else
- regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask);
-
- ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1,
- val, !(val & mask),
- MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
-
- return ret;
-}
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index c9c3cf7..b603af7 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -10,8 +10,8 @@
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
+#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
-#include <linux/soc/mediatek/infracfg.h>
#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/power/mt2712-power.h>
@@ -78,6 +78,29 @@
#define PWR_STATUS_HIF1 BIT(26) /* MT7622 */
#define PWR_STATUS_WB BIT(27) /* MT7622 */
+#define INFRA_TOPAXI_PROTECTEN 0x0220
+#define INFRA_TOPAXI_PROTECTSTA1 0x0228
+#define INFRA_TOPAXI_PROTECTEN_SET 0x0260
+#define INFRA_TOPAXI_PROTECTEN_CLR 0x0264
+
+#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1)
+#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2)
+#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8)
+
+#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17))
+#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25))
+#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \
+ BIT(28))
+#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \
+ BIT(7) | BIT(8))
+
+#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1)
+#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2)
+#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14)
+#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21)
+#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22)
+#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23)
+
#define MAX_CLKS 3
/**
@@ -251,25 +274,50 @@ static int scpsys_sram_disable(struct scp_domain *scpd, void __iomem *ctl_addr)
static int scpsys_bus_protect_enable(struct scp_domain *scpd)
{
struct scp *scp = scpd->scp;
+ struct regmap *infracfg = scp->infracfg;
+ u32 mask = scpd->data->bus_prot_mask;
+ bool reg_update = scp->bus_prot_reg_update;
+ u32 val;
+ int ret;
- if (!scpd->data->bus_prot_mask)
+ if (!mask)
return 0;
- return mtk_infracfg_set_bus_protection(scp->infracfg,
- scpd->data->bus_prot_mask,
- scp->bus_prot_reg_update);
+ if (reg_update)
+ regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask,
+ mask);
+ else
+ regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask);
+
+ ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1,
+ val, (val & mask) == mask,
+ MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+
+ return ret;
}
static int scpsys_bus_protect_disable(struct scp_domain *scpd)
{
struct scp *scp = scpd->scp;
+ struct regmap *infracfg = scp->infracfg;
+ u32 mask = scpd->data->bus_prot_mask;
+ bool reg_update = scp->bus_prot_reg_update;
+ u32 val;
+ int ret;
- if (!scpd->data->bus_prot_mask)
+ if (!mask)
return 0;
- return mtk_infracfg_clear_bus_protection(scp->infracfg,
- scpd->data->bus_prot_mask,
- scp->bus_prot_reg_update);
+ if (reg_update)
+ regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0);
+ else
+ regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask);
+
+ ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1,
+ val, !(val & mask),
+ MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+
+ return ret;
}
static int scpsys_power_on(struct generic_pm_domain *genpd)
diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h
deleted file mode 100644
index fd25f01..0000000
--- a/include/linux/soc/mediatek/infracfg.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __SOC_MEDIATEK_INFRACFG_H
-#define __SOC_MEDIATEK_INFRACFG_H
-
-#define MT8173_TOP_AXI_PROT_EN_MCI_M2 BIT(0)
-#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1)
-#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2)
-#define MT8173_TOP_AXI_PROT_EN_MMAPB_S BIT(6)
-#define MT8173_TOP_AXI_PROT_EN_L2C_M2 BIT(9)
-#define MT8173_TOP_AXI_PROT_EN_L2SS_SMI BIT(11)
-#define MT8173_TOP_AXI_PROT_EN_L2SS_ADD BIT(12)
-#define MT8173_TOP_AXI_PROT_EN_CCI_M2 BIT(13)
-#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14)
-#define MT8173_TOP_AXI_PROT_EN_PERI_M0 BIT(15)
-#define MT8173_TOP_AXI_PROT_EN_PERI_M1 BIT(16)
-#define MT8173_TOP_AXI_PROT_EN_DEBUGSYS BIT(17)
-#define MT8173_TOP_AXI_PROT_EN_CQ_DMA BIT(18)
-#define MT8173_TOP_AXI_PROT_EN_GCPU BIT(19)
-#define MT8173_TOP_AXI_PROT_EN_IOMMU BIT(20)
-#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21)
-#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22)
-#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23)
-
-#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1)
-#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2)
-#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8)
-
-#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17))
-#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25))
-#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \
- BIT(28))
-#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \
- BIT(7) | BIT(8))
-
-int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask,
- bool reg_update);
-int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask,
- bool reg_update);
-#endif /* __SOC_MEDIATEK_INFRACFG_H */
--
1.8.1.1.dirty
A minor coding style fix
Signed-off-by: Weiyi Lu <[email protected]>
---
drivers/soc/mediatek/mtk-scpsys.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index 9a699b4..7158863b 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -1468,7 +1468,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.num_domains = ARRAY_SIZE(scp_domain_data_mt2701),
.regs = {
.pwr_sta_offs = SPM_PWR_STATUS,
- .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
+ .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
},
};
@@ -1479,7 +1479,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.num_subdomains = ARRAY_SIZE(scp_subdomain_mt2712),
.regs = {
.pwr_sta_offs = SPM_PWR_STATUS,
- .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
+ .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
},
};
@@ -1490,7 +1490,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.num_subdomains = ARRAY_SIZE(scp_subdomain_mt6797),
.regs = {
.pwr_sta_offs = SPM_PWR_STATUS_MT6797,
- .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6797
+ .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6797,
},
};
@@ -1499,7 +1499,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.num_domains = ARRAY_SIZE(scp_domain_data_mt7622),
.regs = {
.pwr_sta_offs = SPM_PWR_STATUS,
- .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
+ .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
},
};
@@ -1508,7 +1508,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.num_domains = ARRAY_SIZE(scp_domain_data_mt7623a),
.regs = {
.pwr_sta_offs = SPM_PWR_STATUS,
- .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
+ .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
},
};
@@ -1519,7 +1519,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.num_subdomains = ARRAY_SIZE(scp_subdomain_mt8173),
.regs = {
.pwr_sta_offs = SPM_PWR_STATUS,
- .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
+ .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
},
};
@@ -1528,7 +1528,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.num_domains = ARRAY_SIZE(scp_domain_data_mt8183),
.regs = {
.pwr_sta_offs = 0x0180,
- .pwr_sta2nd_offs = 0x0184
+ .pwr_sta2nd_offs = 0x0184,
}
};
--
1.8.1.1.dirty
For scpsys driver using regmap based syscon driver API.
Signed-off-by: Weiyi Lu <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
.../devicetree/bindings/memory-controllers/mediatek,smi-common.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
index b478ade..01744ec 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
@@ -20,7 +20,7 @@ Required properties:
"mediatek,mt2712-smi-common"
"mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
"mediatek,mt8173-smi-common"
- "mediatek,mt8183-smi-common"
+ "mediatek,mt8183-smi-common", "syscon"
- reg : the register and size of the SMI block.
- power-domains : a phandle to the power domain of this local arbiter.
- clocks : Must contain an entry for each entry in clock-names.
--
1.8.1.1.dirty
Add power controller node and smi-common node for MT8183
In scpsys node, it contains clocks and regmapping of
infracfg and smi-common for bus protection.
And list all the power domains of MT8183 under scpsys node
to show the dependency between each other through hierarchical
structure.
Signed-off-by: Weiyi Lu <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 123 +++++++++++++++++++++++++++++++
1 file changed, 123 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 1e03c84..4940bda 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/mt8183-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/power/mt8183-power.h>
#include <dt-bindings/reset-controller/mt8183-resets.h>
#include "mt8183-pinfunc.h"
@@ -309,6 +310,123 @@
#interrupt-cells = <2>;
};
+ scpsys: power-controller@10006000 {
+ compatible = "mediatek,mt8183-scpsys", "syscon";
+ reg = <0 0x10006000 0 0x1000>;
+ clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>,
+ <&infracfg CLK_INFRA_AUDIO>,
+ <&infracfg CLK_INFRA_AUDIO_26M_BCLK>,
+ <&topckgen CLK_TOP_MUX_MFG>,
+ <&topckgen CLK_TOP_MUX_MM>,
+ <&topckgen CLK_TOP_MUX_CAM>,
+ <&topckgen CLK_TOP_MUX_IMG>,
+ <&topckgen CLK_TOP_MUX_IPU_IF>,
+ <&topckgen CLK_TOP_MUX_DSP>,
+ <&topckgen CLK_TOP_MUX_DSP1>,
+ <&topckgen CLK_TOP_MUX_DSP2>;
+ clock-names = "audio", "audio1", "audio2", "mfg", "mm",
+ "cam", "isp", "vpu", "vpu1", "vpu2",
+ "vpu3";
+ infracfg = <&infracfg>;
+ mediatek,smi = <&smi_common>;
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ audio@MT8183_POWER_DOMAIN_AUDIO {
+ reg = <MT8183_POWER_DOMAIN_AUDIO>;
+ };
+
+ conn@MT8183_POWER_DOMAIN_CONN {
+ reg = <MT8183_POWER_DOMAIN_CONN>;
+ };
+
+ mfg_async@MT8183_POWER_DOMAIN_MFG_ASYNC {
+ reg = <MT8183_POWER_DOMAIN_MFG_ASYNC>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mfg@MT8183_POWER_DOMAIN_MFG {
+ reg = <MT8183_POWER_DOMAIN_MFG>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mfg_core0@MT8183_POWER_DOMAIN_MFG_CORE0 {
+ reg = <MT8183_POWER_DOMAIN_MFG_CORE0>;
+ };
+
+ mfg_core1@MT8183_POWER_DOMAIN_MFG_CORE1 {
+ reg = <MT8183_POWER_DOMAIN_MFG_CORE1>;
+ };
+
+ mfg_2d@MT8183_POWER_DOMAIN_MFG_2D {
+ reg = <MT8183_POWER_DOMAIN_MFG_2D>;
+ };
+ };
+ };
+
+ disp@MT8183_POWER_DOMAIN_DISP {
+ reg = <MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_SMI_COMMON>,
+ <&mmsys CLK_MM_SMI_LARB0>,
+ <&mmsys CLK_MM_SMI_LARB1>,
+ <&mmsys CLK_MM_GALS_COMM0>,
+ <&mmsys CLK_MM_GALS_COMM1>,
+ <&mmsys CLK_MM_GALS_CCU2MM>,
+ <&mmsys CLK_MM_GALS_IPU12MM>,
+ <&mmsys CLK_MM_GALS_IMG2MM>,
+ <&mmsys CLK_MM_GALS_CAM2MM>,
+ <&mmsys CLK_MM_GALS_IPU2MM>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cam@MT8183_POWER_DOMAIN_CAM {
+ reg = <MT8183_POWER_DOMAIN_CAM>;
+ clocks = <&camsys CLK_CAM_LARB6>,
+ <&camsys CLK_CAM_LARB3>,
+ <&camsys CLK_CAM_SENINF>,
+ <&camsys CLK_CAM_CAMSV0>,
+ <&camsys CLK_CAM_CAMSV1>,
+ <&camsys CLK_CAM_CAMSV2>,
+ <&camsys CLK_CAM_CCU>;
+ };
+
+ isp@MT8183_POWER_DOMAIN_ISP {
+ reg = <MT8183_POWER_DOMAIN_ISP>;
+ clocks = <&imgsys CLK_IMG_LARB5>,
+ <&imgsys CLK_IMG_LARB2>;
+ };
+
+ vdec@MT8183_POWER_DOMAIN_VDEC {
+ reg = <MT8183_POWER_DOMAIN_VDEC>;
+ };
+
+ vden@MT8183_POWER_DOMAIN_VENC {
+ reg = <MT8183_POWER_DOMAIN_VENC>;
+ };
+
+ vpu_top@MT8183_POWER_DOMAIN_VPU_TOP {
+ reg = <MT8183_POWER_DOMAIN_VPU_TOP>;
+ clocks = <&ipu_conn CLK_IPU_CONN_IPU>,
+ <&ipu_conn CLK_IPU_CONN_AHB>,
+ <&ipu_conn CLK_IPU_CONN_AXI>,
+ <&ipu_conn CLK_IPU_CONN_ISP>,
+ <&ipu_conn CLK_IPU_CONN_CAM_ADL>,
+ <&ipu_conn CLK_IPU_CONN_IMG_ADL>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vpu_core0@MT8183_POWER_DOMAIN_VPU_CORE0 {
+ reg = <MT8183_POWER_DOMAIN_VPU_CORE0>;
+ };
+
+ vpu_core1@MT8183_POWER_DOMAIN_VPU_CORE1 {
+ reg = <MT8183_POWER_DOMAIN_VPU_CORE1>;
+ };
+ };
+ };
+ };
+
watchdog: watchdog@10007000 {
compatible = "mediatek,mt8183-wdt",
"mediatek,mt6589-wdt";
@@ -690,6 +808,11 @@
#clock-cells = <1>;
};
+ smi_common: smi@14019000 {
+ compatible = "mediatek,mt8183-smi-common", "syscon";
+ reg = <0 0x14019000 0 0x1000>;
+ };
+
imgsys: syscon@15020000 {
compatible = "mediatek,mt8183-imgsys", "syscon";
reg = <0 0x15020000 0 0x1000>;
--
1.8.1.1.dirty
Try to list all the power domains of under power controller
node to show the dependency between each power domain directly
instead of filling the dependency in scp_soc_data.
And could be more clearly to group subsys clocks into power domain
sub node to introduce subsys clocks of bus protection in next patch.
Signed-off-by: Weiyi Lu <[email protected]>
---
drivers/soc/mediatek/mtk-scpsys.c | 103 +++++++++++++++++++++++++++++++++++---
1 file changed, 95 insertions(+), 8 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index 5a2c323..502b66f 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -182,11 +182,13 @@ struct scp {
struct regmap *infracfg;
struct regmap *smi_common;
struct scp_ctrl_reg ctrl_reg;
+ struct list_head dep_links;
};
struct scp_subdomain {
int origin;
int subdomain;
+ struct list_head list;
};
struct scp_soc_data {
@@ -513,6 +515,79 @@ static int init_basic_clks(struct platform_device *pdev, struct clk **clk,
return 0;
}
+static int scpsys_get_domain_id(struct device_node *node, u32 *id)
+{
+ int ret;
+
+ ret = of_property_read_u32(node, "reg", id);
+ if (ret)
+ pr_err("%pOFn: failed to retrieve domain id, ret=%d\n", node, ret);
+
+ return ret;
+}
+
+static int scpsys_get_domain(struct platform_device *pdev, struct scp *scp,
+ struct device_node *node, const struct scp_domain_data *data)
+{
+ struct scp_subdomain *dep_node;
+ struct device_node *sub;
+ u32 parent_id, child_id;
+ int ret;
+
+ ret = scpsys_get_domain_id(node, &parent_id);
+ if (ret)
+ return ret;
+
+ for_each_child_of_node(node, sub) {
+ ret = scpsys_get_domain_id(sub, &child_id);
+ if (ret)
+ goto out;
+
+ dep_node = devm_kzalloc(&pdev->dev, sizeof(*dep_node), GFP_KERNEL);
+ if (!dep_node) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ dep_node->origin = parent_id;
+ dep_node->subdomain = child_id;
+ list_add(&dep_node->list, &scp->dep_links);
+
+ scpsys_get_domain(pdev, scp, sub, data);
+ }
+
+ return 0;
+
+out:
+ of_node_put(sub);
+ return ret;
+}
+
+static int traverse_scp(struct platform_device *pdev, struct scp *scp,
+ const struct scp_domain_data *scp_domain_data)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct device_node *sub;
+ int ret;
+
+ INIT_LIST_HEAD(&scp->dep_links);
+
+ for_each_available_child_of_node(np, sub) {
+ ret = scpsys_get_domain(pdev, scp, sub, scp_domain_data);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to handle node %pOFn: %d\n", sub, ret);
+ goto err;
+ }
+ }
+
+ return 0;
+
+err:
+ of_node_put(sub);
+ return ret;
+}
+
static struct scp *init_scp(struct platform_device *pdev,
const struct scp_domain_data *scp_domain_data, int num,
const struct scp_ctrl_reg *scp_ctrl_reg)
@@ -582,6 +657,10 @@ static struct scp *init_scp(struct platform_device *pdev,
pd_data->num_domains = num;
+ ret = traverse_scp(pdev, scp, scp_domain_data);
+ if (ret)
+ return ERR_PTR(ret);
+
for (i = 0; i < num; i++) {
struct scp_domain *scpd = &scp->domains[i];
struct generic_pm_domain *genpd = &scpd->genpd;
@@ -1208,7 +1287,7 @@ static int scpsys_probe(struct platform_device *pdev)
const struct scp_soc_data *soc;
struct scp *scp;
struct genpd_onecell_data *pd_data;
- int i, ret;
+ int i, ret = 0;
soc = of_device_get_match_data(&pdev->dev);
@@ -1220,15 +1299,23 @@ static int scpsys_probe(struct platform_device *pdev)
pd_data = &scp->pd_data;
- for (i = 0, sd = soc->subdomains; i < soc->num_subdomains; i++, sd++) {
- ret = pm_genpd_add_subdomain(pd_data->domains[sd->origin],
- pd_data->domains[sd->subdomain]);
- if (ret && IS_ENABLED(CONFIG_PM))
- dev_err(&pdev->dev, "Failed to add subdomain: %d\n",
- ret);
+ if (soc->subdomains && soc->num_subdomains) {
+ for (i = 0, sd = soc->subdomains; i < soc->num_subdomains; i++, sd++) {
+ ret = pm_genpd_add_subdomain(pd_data->domains[sd->origin],
+ pd_data->domains[sd->subdomain]);
+ if (ret && IS_ENABLED(CONFIG_PM))
+ dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
+ }
+ } else {
+ list_for_each_entry(sd, &scp->dep_links, list) {
+ ret = pm_genpd_add_subdomain(pd_data->domains[sd->origin],
+ pd_data->domains[sd->subdomain]);
+ if (ret && IS_ENABLED(CONFIG_PM))
+ dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret);
+ }
}
- return 0;
+ return ret;
}
static struct platform_driver scpsys_drv = {
--
1.8.1.1.dirty
On Thu, 06 Aug 2020 17:21:48 +0800, Weiyi Lu wrote:
> Add power dt-bindings of MT8183.
> Add an optional "mediatek,smi" property for phandle to smi-common
> node for power controller.
> Introduce properties for power domain sub nodes.
>
> Signed-off-by: Weiyi Lu <[email protected]>
> ---
> .../devicetree/bindings/soc/mediatek/scpsys.txt | 81 ++++++++++++++++++++--
> include/dt-bindings/power/mt8183-power.h | 26 +++++++
> 2 files changed, 102 insertions(+), 5 deletions(-)
> create mode 100644 include/dt-bindings/power/mt8183-power.h
>
Reviewed-by: Rob Herring <[email protected]>
On Thu, Aug 6, 2020 at 5:22 PM Weiyi Lu <[email protected]> wrote:
>
> Try to list all the power domains of under power controller
> node to show the dependency between each power domain directly
> instead of filling the dependency in scp_soc_data.
> And could be more clearly to group subsys clocks into power domain
> sub node to introduce subsys clocks of bus protection in next patch.
>
> Signed-off-by: Weiyi Lu <[email protected]>
> ---
[snip]
> +static int traverse_scp(struct platform_device *pdev, struct scp *scp,
> + const struct scp_domain_data *scp_domain_data)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node;
> + struct device_node *sub;
> + int ret;
> +
> + INIT_LIST_HEAD(&scp->dep_links);
> +
> + for_each_available_child_of_node(np, sub) {
> + ret = scpsys_get_domain(pdev, scp, sub, scp_domain_data);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to handle node %pOFn: %d\n", sub, ret);
minor comment: this error should not be printed if ret ==
-EPROBE_DEFER (use the new dev_err_probe?)
> + goto err;
> + }
> + }
> +
> + return 0;
> +
> +err:
> + of_node_put(sub);
> + return ret;
> +}
[snip]
On Mon, 2020-09-28 at 15:14 +0800, Nicolas Boichat wrote:
> On Thu, Aug 6, 2020 at 5:22 PM Weiyi Lu <[email protected]> wrote:
> >
> > Try to list all the power domains of under power controller
> > node to show the dependency between each power domain directly
> > instead of filling the dependency in scp_soc_data.
> > And could be more clearly to group subsys clocks into power domain
> > sub node to introduce subsys clocks of bus protection in next patch.
> >
> > Signed-off-by: Weiyi Lu <[email protected]>
> > ---
> [snip]
> > +static int traverse_scp(struct platform_device *pdev, struct scp *scp,
> > + const struct scp_domain_data *scp_domain_data)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct device_node *np = dev->of_node;
> > + struct device_node *sub;
> > + int ret;
> > +
> > + INIT_LIST_HEAD(&scp->dep_links);
> > +
> > + for_each_available_child_of_node(np, sub) {
> > + ret = scpsys_get_domain(pdev, scp, sub, scp_domain_data);
> > + if (ret) {
> > + dev_err(&pdev->dev, "failed to handle node %pOFn: %d\n", sub, ret);
>
> minor comment: this error should not be printed if ret ==
> -EPROBE_DEFER (use the new dev_err_probe?)
>
You're right! I'll use dev_err_probe() instead if anyone is interested
in this series. Thank you!
> > + goto err;
> > + }
> > + }
> > +
> > + return 0;
> > +
> > +err:
> > + of_node_put(sub);
> > + return ret;
> > +}
> [snip]
On 30/09/2020 05:37, Weiyi Lu wrote:
> On Mon, 2020-09-28 at 15:14 +0800, Nicolas Boichat wrote:
>> On Thu, Aug 6, 2020 at 5:22 PM Weiyi Lu <[email protected]> wrote:
>>>
>>> Try to list all the power domains of under power controller
>>> node to show the dependency between each power domain directly
>>> instead of filling the dependency in scp_soc_data.
>>> And could be more clearly to group subsys clocks into power domain
>>> sub node to introduce subsys clocks of bus protection in next patch.
>>>
>>> Signed-off-by: Weiyi Lu <[email protected]>
>>> ---
>> [snip]
>>> +static int traverse_scp(struct platform_device *pdev, struct scp *scp,
>>> + const struct scp_domain_data *scp_domain_data)
>>> +{
>>> + struct device *dev = &pdev->dev;
>>> + struct device_node *np = dev->of_node;
>>> + struct device_node *sub;
>>> + int ret;
>>> +
>>> + INIT_LIST_HEAD(&scp->dep_links);
>>> +
>>> + for_each_available_child_of_node(np, sub) {
>>> + ret = scpsys_get_domain(pdev, scp, sub, scp_domain_data);
>>> + if (ret) {
>>> + dev_err(&pdev->dev, "failed to handle node %pOFn: %d\n", sub, ret);
>>
>> minor comment: this error should not be printed if ret ==
>> -EPROBE_DEFER (use the new dev_err_probe?)
>>
>
> You're right! I'll use dev_err_probe() instead if anyone is interested
> in this series. Thank you!
>
I'd propose that we put all our effort of reviewing and testing into the series
Enric send:
https://lore.kernel.org/linux-mediatek/[email protected]/
Regards,
Matthias
>>> + goto err;
>>> + }
>>> + }
>>> +
>>> + return 0;
>>> +
>>> +err:
>>> + of_node_put(sub);
>>> + return ret;
>>> +}
>> [snip]
>