From: Wanpeng Li <[email protected]>
Return 0 when getting the tscdeadline timer if the lapic is hw disabled.
Suggested-by: Paolo Bonzini <[email protected]>
Signed-off-by: Wanpeng Li <[email protected]>
---
v1 -> v2:
* fix indentation
arch/x86/kvm/lapic.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 5ccbee7..79599af 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -2183,8 +2183,7 @@ u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
{
struct kvm_lapic *apic = vcpu->arch.apic;
- if (!lapic_in_kernel(vcpu) ||
- !apic_lvtt_tscdeadline(apic))
+ if (!kvm_apic_present(vcpu) || !apic_lvtt_tscdeadline(apic))
return 0;
return apic->lapic_timer.tscdeadline;
--
2.7.4
On Wed, Aug 12, 2020 at 02:30:37PM +0800, Wanpeng Li wrote:
> From: Wanpeng Li <[email protected]>
>
> Return 0 when getting the tscdeadline timer if the lapic is hw disabled.
It'd be helpful to reference the SDM for the general behavior of the MSR.
In other timer modes (LVT bit 18 = 0), the IA32_TSC_DEADLINE MSR reads
zero and writes are ignored.
I'd also vote to squash the two patches together, they really are paired
changes to match the architectural behavior.
Reviewed-by: Sean Christopherson <[email protected]>
On Wed, Aug 12, 2020 at 02:30:37PM +0800, Wanpeng Li wrote:
> From: Wanpeng Li <[email protected]>
>
> Return 0 when getting the tscdeadline timer if the lapic is hw disabled.
>
> Suggested-by: Paolo Bonzini <[email protected]>
> Signed-off-by: Wanpeng Li <[email protected]>
> ---
Reviewed-by: Sean Christopherson <[email protected]>