There is ecspi ERR009165 on i.mx6/7 soc family, which cause FIFO
transfer to be send twice in DMA mode. Please get more information from:
https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf. The workaround is adding
new sdma ram script which works in XCH mode as PIO inside sdma instead
of SMC mode, meanwhile, 'TX_THRESHOLD' should be 0. The issue should be
exist on all legacy i.mx6/7 soc family before i.mx6ul.
NXP fix this design issue from i.mx6ul, so newer chips including i.mx6ul/
6ull/6sll do not need this workaroud anymore. All other i.mx6/7/8 chips
still need this workaroud. This patch set add new 'fsl,imx6ul-ecspi'
for ecspi driver and 'ecspi_fixed' in sdma driver to choose if need errata
or not.
The first two reverted patches should be the same issue, though, it
seems 'fixed' by changing to other shp script. Hope Sean or Sascha could
have the chance to test this patch set if could fix their issues.
Besides, enable sdma support for i.mx8mm/8mq and fix ecspi1 not work
on i.mx8mm because the event id is zero.
PS:
Please get sdma firmware from below linux-firmware and copy it to your
local rootfs /lib/firmware/imx/sdma.
https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/imx/sdma
v2:
1.Add commit log for reverted patches.
2.Add comment for 'ecspi_fixed' in sdma driver.
3.Add 'fsl,imx6sll-ecspi' compatible instead of 'fsl,imx6ul-ecspi'
rather than remove.
v3:
1.Confirm with design team make sure ERR009165 fixed on i.mx6ul/i.mx6ull
/i.mx6sll, not fixed on i.mx8m/8mm and other i.mx6/7 legacy chips.
Correct dts related dts patch in v2.
2.Clean eratta information in binding doc and new 'tx_glitch_fixed' flag
in spi-imx driver to state ERR009165 fixed or not.
3.Enlarge burst size to fifo size for tx since tx_wml set to 0 in the
errata workaroud, thus improve performance as possible.
v4:
1.Add Ack tag from Mark and Vinod
2.Remove checking 'event_id1' zero as 'event_id0'.
v5:
1.Add the last patch for compatible with the current uart driver which
using rom script, so both uart ram script and rom script supported
in latest firmware, by default uart rom script used. UART driver
will be broken without this patch.
v6:
1.Resend after rebase the latest next branch.
2.Remove below No.13~No.15 patches of v5 because they were mergered.
ARM: dts: imx6ul: add dma support on ecspi
ARM: dts: imx6sll: correct sdma compatible
arm64: defconfig: Enable SDMA on i.mx8mq/8mm
3.Revert "dmaengine: imx-sdma: fix context cache" since
'context_loaded' removed.
v7:
1.Put the last patch 13/13 'Revert "dmaengine: imx-sdma: fix context
cache"' to the ahead of 03/13 'Revert "dmaengine: imx-sdma: refine
to load context only once" so that no building waring during comes out
during bisect.
2.Address Sascha's comments, including eliminating any i.mx6sx in this
series, adding new 'is_imx6ul_ecspi()' instead imx in imx51 and taking
care SMC bit for PIO.
3.Add back missing 'Reviewed-by' tag on 08/15(v5):09/13(v7)
'spi: imx: add new i.mx6ul compatible name in binding doc'
v8:
1.remove 0003-Revert-dmaengine-imx-sdma-fix-context-cache.patch and merge
it into 04/13 of v7
2.add 0005-spi-imx-fallback-to-PIO-if-dma-setup-failure.patch for no any
ecspi function broken even if sdma firmware not updated.
3.merge 'tx.dst_maxburst' changes in the two continous patches into one
patch to avoid confusion.
4.fix typo 'duplicated'.
v9:
1. add "spi: imx: add dma_sync_sg_for_device after fallback from dma"
to fix the potential issue brought by commit bcd8e7761ec9("spi: imx:
fallback to PIO if dma setup failure") which is the only one patch
of v8 merged. Thanks Matthias for reporting:
https://lore.kernel.org/linux-arm-kernel/[email protected]/
2. remove 05/13 of v8 "spi: imx:fallback to PIO if dma setup failure"
since it's been merged.
v10:
1. remove 01/13 "spi: imx: add dma_sync_sg_for_device after fallback from dma"
since there is another independent patch merged:
-- commit 809b1b04df898 ("spi: introduce fallback to pio")
2. add "dmaengine: dma: imx-sdma: add fw_loaded and is_ram_script" which
is used to fix the potential dma_alloc_coherent() failure while this
patchset applied but sdma firmware may not be ready for long time.
3. burst size change back from fifo size to normal wml to align with nxp
internal tree which has been test for years. Overnight with loopback
test with spidev failed with fifo size, but pass with wml(half of fifo
size).Seems the whole fifo size fed may cause rxfifo overflow during
tx shift out while rx shift in.
"spi: imx: remove ERR009165 workaround on i.mx6ul"
4. remove 12/13 'dmaengine: imx-sdma: fix ecspi1 rx dma not work on i.mx8mm'
since below two similar patches merged:
-- commit 25962e1a7f1d ("dmaengine: imx-sdma: Fix the event id check to
include RX event for UART6")
-- commit 2f57b8d57673 ("dmaengine: imx-sdma: Fix: Remove 'always true'
comparison")
v11:
1. change dev_err() to dev_warn_once() in case sdma firmware not loaded to
eliminate meaningless duplicate log print.
v12:
1. take care uart_2_mcu_addr/uartsh_2_mcu_addr since such rom scripts are
now located in the bottom part of sdma_script_start_addrs which are beyond
the SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1. Reported by Frieder as below:
https://www.mail-archive.com/[email protected]/msg2263544.html
v13:
1. rebase with latest linux-next.
2. remove 09/12 'spi: imx: add new i.mx6ul compatible name in binding doc'
since it's been converted to yaml already.
3. add 'Fixes', 'Cc: [email protected]' and 'Test-by' tags for 03,04
since they are confirmed fix by Richard Leitner:
https://lkml.org/lkml/2020/8/17/39
https://www.spinics.net/lists/dmaengine/msg23489.html
4. fix potential descriptor free unexpected on the next transfer before
the last channel terminated:
https://www.spinics.net/lists/dmaengine/msg23400.html
Robin Gong (12):
Revert "ARM: dts: imx6q: Use correct SDMA script for SPI5 core"
Revert "ARM: dts: imx6: Use correct SDMA script for SPI cores"
Revert "dmaengine: imx-sdma: refine to load context only once"
dmaengine: imx-sdma: remove duplicated sdma_load_context
dmaengine: dma: imx-sdma: add fw_loaded and is_ram_script
dmaengine: imx-sdma: add mcu_2_ecspi script
spi: imx: fix ERR009165
spi: imx: remove ERR009165 workaround on i.mx6ul
dmaengine: imx-sdma: remove ERR009165 on i.mx6ul
dma: imx-sdma: add i.mx6ul compatible name
dmaengine: imx-sdma: add uart rom script
dmaengine: imx-sdma: add terminated list for freed descriptor in
worker
.../devicetree/bindings/dma/fsl-imx-sdma.txt | 1 +
arch/arm/boot/dts/imx6q.dtsi | 2 +-
arch/arm/boot/dts/imx6qdl.dtsi | 8 +-
drivers/dma/imx-sdma.c | 93 +++++++++++++++++-----
drivers/spi/spi-imx.c | 52 ++++++++++--
include/linux/platform_data/dma-imx-sdma.h | 8 +-
6 files changed, 128 insertions(+), 36 deletions(-)
--
2.7.4
ECSPI issue fixed from i.mx6ul at hardware level, no need
ERR009165 anymore on those chips such as i.mx8mq.
Signed-off-by: Robin Gong <[email protected]>
Acked-by: Vinod Koul <[email protected]>
---
drivers/dma/imx-sdma.c | 29 ++++++++++++++++++++++++++++-
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index fb522a1..147ea88 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -422,6 +422,13 @@ struct sdma_driver_data {
int num_events;
struct sdma_script_start_addrs *script_addrs;
bool check_ratio;
+ /*
+ * ecspi ERR009165 fixed should be done in sdma script
+ * and it has been fixed in soc from i.mx6ul.
+ * please get more information from the below link:
+ * https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
+ */
+ bool ecspi_fixed;
};
struct sdma_engine {
@@ -543,6 +550,13 @@ static struct sdma_driver_data sdma_imx6q = {
.script_addrs = &sdma_script_imx6q,
};
+static struct sdma_driver_data sdma_imx6ul = {
+ .chnenbl0 = SDMA_CHNENBL0_IMX35,
+ .num_events = 48,
+ .script_addrs = &sdma_script_imx6q,
+ .ecspi_fixed = true,
+};
+
static struct sdma_script_start_addrs sdma_script_imx7d = {
.ap_2_ap_addr = 644,
.uart_2_mcu_addr = 819,
@@ -591,6 +605,9 @@ static const struct platform_device_id sdma_devtypes[] = {
.name = "imx7d-sdma",
.driver_data = (unsigned long)&sdma_imx7d,
}, {
+ .name = "imx6ul-sdma",
+ .driver_data = (unsigned long)&sdma_imx6ul,
+ }, {
.name = "imx8mq-sdma",
.driver_data = (unsigned long)&sdma_imx8mq,
}, {
@@ -607,6 +624,7 @@ static const struct of_device_id sdma_dt_ids[] = {
{ .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
{ .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
{ .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
+ { .compatible = "fsl,imx6ul-sdma", .data = &sdma_imx6ul, },
{ .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, },
{ /* sentinel */ }
};
@@ -1176,8 +1194,17 @@ static int sdma_config_channel(struct dma_chan *chan)
if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
sdmac->peripheral_type == IMX_DMATYPE_ASRC)
sdma_set_watermarklevel_for_p2p(sdmac);
- } else
+ } else {
+ /*
+ * ERR009165 fixed from i.mx6ul, no errata need,
+ * set bit31 to let sdma script skip the errata.
+ */
+ if (sdmac->peripheral_type == IMX_DMATYPE_CSPI &&
+ sdmac->direction == DMA_MEM_TO_DEV &&
+ sdmac->sdma->drvdata->ecspi_fixed)
+ __set_bit(31, &sdmac->watermark_level);
__set_bit(sdmac->event_id0, sdmac->event_mask);
+ }
/* Address */
sdmac->shp_addr = sdmac->per_address;
--
2.7.4
Add i.mx6ul compatible name in binding doc.
Signed-off-by: Robin Gong <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
index c9e9740..12c316f 100644
--- a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
+++ b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt
@@ -9,6 +9,7 @@ Required properties:
"fsl,imx53-sdma"
"fsl,imx6q-sdma"
"fsl,imx7d-sdma"
+ "fsl,imx6ul-sdma"
"fsl,imx8mq-sdma"
"fsl,imx8mm-sdma"
"fsl,imx8mn-sdma"
--
2.7.4
Since sdma_transfer_init() will do sdma_load_context before any
sdma transfer, no need once more in sdma_config_channel().
Fixes: ad0d92d7ba6a ("dmaengine: imx-sdma: refine to load context only once")
Cc: <[email protected]>
Signed-off-by: Robin Gong <[email protected]>
Acked-by: Vinod Koul <[email protected]>
Tested-by: Richard Leitner <[email protected]>
---
drivers/dma/imx-sdma.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 22be370..f899083 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -1139,7 +1139,6 @@ static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
static int sdma_config_channel(struct dma_chan *chan)
{
struct sdma_channel *sdmac = to_sdma_chan(chan);
- int ret;
sdma_disable_channel(chan);
@@ -1179,9 +1178,7 @@ static int sdma_config_channel(struct dma_chan *chan)
sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
}
- ret = sdma_load_context(sdmac);
-
- return ret;
+ return 0;
}
static int sdma_set_channel_priority(struct sdma_channel *sdmac,
--
2.7.4
Change to XCH mode even in dma mode, please refer to the below
errata:
https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
Signed-off-by: Robin Gong <[email protected]>
Acked-by: Mark Brown <[email protected]>
---
drivers/spi/spi-imx.c | 10 +++-------
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index 197f606..9edb259 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -593,8 +593,8 @@ static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
ctrl |= mx51_ecspi_clkdiv(spi_imx, t->speed_hz, &clk);
spi_imx->spi_bus_clk = clk;
- if (spi_imx->usedma)
- ctrl |= MX51_ECSPI_CTRL_SMC;
+ /* ERR009165: work in XHC mode as PIO */
+ ctrl &= ~MX51_ECSPI_CTRL_SMC;
writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
@@ -625,7 +625,7 @@ static void mx51_setup_wml(struct spi_imx_data *spi_imx)
* and enable DMA request.
*/
writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
- MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
+ MX51_ECSPI_DMA_TX_WML(0) |
MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
@@ -1261,10 +1261,6 @@ static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
{
int ret;
- /* use pio mode for i.mx6dl chip TKT238285 */
- if (of_machine_is_compatible("fsl,imx6dl"))
- return 0;
-
spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
/* Prepare for TX DMA: */
--
2.7.4
Add 'fw_loaded' and 'is_ram_script' to check if the script used by channel
is ram script and it's loaded or not, so that could prevent meaningless
following malloc dma descriptor and bd allocate in sdma_transfer_init(),
otherwise memory may be consumed out potentially without free in case
that spi fallback into pio while dma transfer failed by sdma firmware not
ready(next ERR009165 patch depends on sdma RAM scripts/firmware).
Signed-off-by: Robin Gong <[email protected]>
Acked-By: Vinod Koul <[email protected]>
---
drivers/dma/imx-sdma.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index f899083..10214bb 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -381,6 +381,7 @@ struct sdma_channel {
enum dma_status status;
struct imx_dma_data data;
struct work_struct terminate_worker;
+ bool is_ram_script;
};
#define IMX_DMA_SG_LOOP BIT(0)
@@ -445,6 +446,7 @@ struct sdma_engine {
struct sdma_buffer_descriptor *bd0;
/* clock ratio for AHB:SDMA core. 1:1 is 1, 2:1 is 0*/
bool clk_ratio;
+ bool fw_loaded;
};
static int sdma_config_write(struct dma_chan *chan,
@@ -931,6 +933,7 @@ static void sdma_get_pc(struct sdma_channel *sdmac,
case IMX_DMATYPE_SSI_DUAL:
per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
+ sdmac->is_ram_script = true;
break;
case IMX_DMATYPE_SSI_SP:
case IMX_DMATYPE_MMC:
@@ -945,6 +948,7 @@ static void sdma_get_pc(struct sdma_channel *sdmac,
per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
per_2_per = sdma->script_addrs->per_2_per_addr;
+ sdmac->is_ram_script = true;
break;
case IMX_DMATYPE_ASRC_SP:
per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
@@ -1341,6 +1345,11 @@ static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac,
{
struct sdma_desc *desc;
+ if (!sdmac->sdma->fw_loaded && sdmac->is_ram_script) {
+ dev_warn_once(sdmac->sdma->dev, "sdma firmware not ready!\n");
+ goto err_out;
+ }
+
desc = kzalloc((sizeof(*desc)), GFP_NOWAIT);
if (!desc)
goto err_out;
@@ -1591,6 +1600,8 @@ static int sdma_config_write(struct dma_chan *chan,
{
struct sdma_channel *sdmac = to_sdma_chan(chan);
+ sdmac->is_ram_script = false;
+
if (direction == DMA_DEV_TO_MEM) {
sdmac->per_address = dmaengine_cfg->src_addr;
sdmac->watermark_level = dmaengine_cfg->src_maxburst *
@@ -1770,6 +1781,8 @@ static void sdma_load_firmware(const struct firmware *fw, void *context)
sdma_add_scripts(sdma, addr);
+ sdma->fw_loaded = true;
+
dev_info(sdma->dev, "loaded firmware %d.%d\n",
header->version_major,
header->version_minor);
--
2.7.4
For the compatibility of NXP internal legacy kernel before 4.19 which
is based on uart ram script and upstreaming kernel based on uart rom
script, add both uart ram/rom script in latest sdma firmware. By default
uart rom script used.
Besides, add two multi-fifo scripts for SAI/PDM on i.mx8m/8mm and add
back qspi script miss for v4(i.mx7d/8m/8mm family, but v3 is for i.mx6).
rom script:
uart_2_mcu_addr
uartsh_2_mcu_addr /* through spba bus */
am script:
uart_2_mcu_ram_addr
uartsh_2_mcu_ram_addr /* through spba bus */
Please get latest sdma firmware from the below and put them into the path
(/lib/firmware/imx/sdma/):
https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git
/tree/imx/sdma
Signed-off-by: Robin Gong <[email protected]>
Acked-by: Vinod Koul <[email protected]>
---
drivers/dma/imx-sdma.c | 17 +++++++++++++++--
include/linux/platform_data/dma-imx-sdma.h | 8 ++++++--
2 files changed, 21 insertions(+), 4 deletions(-)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 147ea88..9bb6270 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -1731,8 +1731,8 @@ static void sdma_issue_pending(struct dma_chan *chan)
#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38
-#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41
-#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 42
+#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 45
+#define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 46
static void sdma_add_scripts(struct sdma_engine *sdma,
const struct sdma_script_start_addrs *addr)
@@ -1756,6 +1756,19 @@ static void sdma_add_scripts(struct sdma_engine *sdma,
for (i = 0; i < sdma->script_number; i++)
if (addr_arr[i] > 0)
saddr_arr[i] = addr_arr[i];
+
+ /*
+ * get uart_2_mcu_addr/uartsh_2_mcu_addr rom script specially because
+ * they are now replaced by uart_2_mcu_ram_addr/uartsh_2_mcu_ram_addr
+ * to be compatible with legacy freescale/nxp sdma firmware, and they
+ * are located in the bottom part of sdma_script_start_addrs which are
+ * beyond the SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1.
+ */
+ if (addr->uart_2_mcu_addr)
+ sdma->script_addrs->uart_2_mcu_addr = addr->uart_2_mcu_addr;
+ if (addr->uartsh_2_mcu_addr)
+ sdma->script_addrs->uartsh_2_mcu_addr = addr->uartsh_2_mcu_addr;
+
}
static void sdma_load_firmware(const struct firmware *fw, void *context)
diff --git a/include/linux/platform_data/dma-imx-sdma.h b/include/linux/platform_data/dma-imx-sdma.h
index 30e676b..e12d2e8 100644
--- a/include/linux/platform_data/dma-imx-sdma.h
+++ b/include/linux/platform_data/dma-imx-sdma.h
@@ -20,12 +20,12 @@ struct sdma_script_start_addrs {
s32 per_2_firi_addr;
s32 mcu_2_firi_addr;
s32 uart_2_per_addr;
- s32 uart_2_mcu_addr;
+ s32 uart_2_mcu_ram_addr;
s32 per_2_app_addr;
s32 mcu_2_app_addr;
s32 per_2_per_addr;
s32 uartsh_2_per_addr;
- s32 uartsh_2_mcu_addr;
+ s32 uartsh_2_mcu_ram_addr;
s32 per_2_shp_addr;
s32 mcu_2_shp_addr;
s32 ata_2_mcu_addr;
@@ -52,6 +52,10 @@ struct sdma_script_start_addrs {
s32 zcanfd_2_mcu_addr;
s32 zqspi_2_mcu_addr;
s32 mcu_2_ecspi_addr;
+ s32 mcu_2_sai_addr;
+ s32 sai_2_mcu_addr;
+ s32 uart_2_mcu_addr;
+ s32 uartsh_2_mcu_addr;
/* End of v3 array */
s32 mcu_2_zqspi_addr;
/* End of v4 array */
--
2.7.4
Add terminated list for keeping descriptor so that it could be freed in
worker without any potential involving next descriptor raised up before
this descriptor freed, because vchan_get_all_descriptors get all
descriptors including the last terminated descriptor and the next
descriptor, hence, the next descriptor maybe freed unexpectly when it's
done in worker without this patch.
https://www.spinics.net/lists/dmaengine/msg23367.html
Signed-off-by: Robin Gong <[email protected]>
Reported-by: Richard Leitner <[email protected]>
---
drivers/dma/imx-sdma.c | 17 ++++++++++-------
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 9bb6270..2fa8733 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -381,6 +381,7 @@ struct sdma_channel {
enum dma_status status;
struct imx_dma_data data;
struct work_struct terminate_worker;
+ struct list_head terminated;
bool is_ram_script;
};
@@ -1076,9 +1077,6 @@ static void sdma_channel_terminate_work(struct work_struct *work)
{
struct sdma_channel *sdmac = container_of(work, struct sdma_channel,
terminate_worker);
- unsigned long flags;
- LIST_HEAD(head);
-
/*
* According to NXP R&D team a delay of one BD SDMA cost time
* (maximum is 1ms) should be added after disable of the channel
@@ -1087,10 +1085,7 @@ static void sdma_channel_terminate_work(struct work_struct *work)
*/
usleep_range(1000, 2000);
- spin_lock_irqsave(&sdmac->vc.lock, flags);
- vchan_get_all_descriptors(&sdmac->vc, &head);
- spin_unlock_irqrestore(&sdmac->vc.lock, flags);
- vchan_dma_desc_free_list(&sdmac->vc, &head);
+ vchan_dma_desc_free_list(&sdmac->vc, &sdmac->terminated);
}
static int sdma_terminate_all(struct dma_chan *chan)
@@ -1104,6 +1099,13 @@ static int sdma_terminate_all(struct dma_chan *chan)
if (sdmac->desc) {
vchan_terminate_vdesc(&sdmac->desc->vd);
+ /*
+ * move out current descriptor into terminated list so that
+ * it could be free in sdma_channel_terminate_work alone
+ * later without potential involving next descriptor raised
+ * up before the last descriptor terminated.
+ */
+ vchan_get_all_descriptors(&sdmac->vc, &sdmac->terminated);
sdmac->desc = NULL;
schedule_work(&sdmac->terminate_worker);
}
@@ -2124,6 +2126,7 @@ static int sdma_probe(struct platform_device *pdev)
sdmac->channel = i;
sdmac->vc.desc_free = sdma_desc_free;
+ INIT_LIST_HEAD(&sdmac->terminated);
INIT_WORK(&sdmac->terminate_worker,
sdma_channel_terminate_work);
/*
--
2.7.4
On 20-09-01 00:03, Robin Gong wrote:
> There is ecspi ERR009165 on i.mx6/7 soc family, which cause FIFO
> transfer to be send twice in DMA mode. Please get more information from:
> https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf. The workaround is adding
> new sdma ram script which works in XCH mode as PIO inside sdma instead
> of SMC mode, meanwhile, 'TX_THRESHOLD' should be 0. The issue should be
> exist on all legacy i.mx6/7 soc family before i.mx6ul.
> NXP fix this design issue from i.mx6ul, so newer chips including i.mx6ul/
> 6ull/6sll do not need this workaroud anymore. All other i.mx6/7/8 chips
> still need this workaroud. This patch set add new 'fsl,imx6ul-ecspi'
> for ecspi driver and 'ecspi_fixed' in sdma driver to choose if need errata
> or not.
> The first two reverted patches should be the same issue, though, it
> seems 'fixed' by changing to other shp script. Hope Sean or Sascha could
> have the chance to test this patch set if could fix their issues.
> Besides, enable sdma support for i.mx8mm/8mq and fix ecspi1 not work
> on i.mx8mm because the event id is zero.
>
> PS:
> Please get sdma firmware from below linux-firmware and copy it to your
> local rootfs /lib/firmware/imx/sdma.
> https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/imx/sdma
Hi Robin,
I took your patches and did a few test on the mainline available
fsl,imx6q-sabrelite. I used a vanilla linux version v5.9-rc1 for all my
tests except the needed SPI-NOR patches [1]. Following are my results:
Testcase 1: "Using ROM-FW"
===
[OK] Playing Audio (SSI)
[OK] TX/RX bytes on a different UART (not the serial used for
interaction)
[OK] Writing to the SPI-NOR
[OK] Doing all at the same time (once for TX and once for RX on UART)
Notes:
- Your Patches adding a maybe noise message "sdma firmware not ready".
Maybe we should consider about that if it should be a warning or a info.
- For spi-nor I did run this test:
dd if=/dev/urandom of=/var/tmp/test1M bs=1M count=1 && \
flashcp -v /var/tmp/test1M /dev/mtd2
and checked /proc/interrupts:
25: 2107169 0 0 0 GPC 31 Level 2008000.spi
Testcase 2: "Using new FW from linux-firmware"
===
[OK] Playing Audio (SSI)
[OK] TX/RX bytes on a different UART (not the serial used for
interaction)
[OK] Writing to the SPI-NOR
[OK] Doing all at the same time (once for TX and once for RX on UART)
Notes:
- For spi-nor I did run this test:
dd if=/dev/urandom of=/var/tmp/test1M bs=1M count=1 && \
flashcp -v /var/tmp/test1M /dev/mtd2
and checked /proc/interrupts:
25: 2107993 0 0 0 GPC 31 Level 2008000.spi
I saw no SDMA interrupts during this testcase instead I saw only spi
controller interrupts.
- According linux-firmware you did a version bump from 3.5 to 4.5 but my
dmesg shows:
imx-sdma 20ec000.sdma: loaded firmware 3.5
SPI Benchmark:
===
flash_erase /dev/mtd2 0 0 && \
dd if=/dev/urandom of=/dev/mtd2 bs=1M count=1
- without firmware (ROM-FW)
1048576 bytes (1.0 MB, 1.0 MiB) copied, 51.9713 s, 20.2 kB/s
- with firmware
1048576 bytes (1.0 MB, 1.0 MiB) copied, 59.4174 s, 17.6 kB/s
Conclusion:
===
It seems that we don't have any performance boost with your patchset
instead we are increasing the complexity and the interrupts...
Pls let me know if I did something wrong during testing or if my test
setup was wrong. Note: the /dev/mtd2 isn't mainlined yet but if you use
barebox you only have to add:
8<---------------------------------------------------------------------
diff --git a/arch/arm/dts/imx6qdl-sabrelite.dtsi b/arch/arm/dts/imx6qdl-sabrelite.dtsi
index ec3d364bde..256dd90a0f 100644
--- a/arch/arm/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/dts/imx6qdl-sabrelite.dtsi
@@ -38,6 +38,11 @@
label = "barebox-environment";
reg = <0xe0000 0x20000>;
};
+
+ parition@100000 {
+ label = "user-partition";
+ reg = <0x100000 0x100000>;
+ };
};
&ocotp {
8<---------------------------------------------------------------------
to the barebox device tree.
[1] http://lists.infradead.org/pipermail/linux-mtd/2020-September/082099.html
Regards,
Marco
On 2020/09/12 0:40 Marco Felsch <[email protected]> wrote:
> Hi Robin,
>
> I took your patches and did a few test on the mainline available
> fsl,imx6q-sabrelite. I used a vanilla linux version v5.9-rc1 for all my tests except
> the needed SPI-NOR patches [1]. Following are my results:
Marco, thanks for your test :)
>
> Testcase 1: "Using ROM-FW"
> ===
> [OK] Playing Audio (SSI)
> [OK] TX/RX bytes on a different UART (not the serial used for
> interaction)
> [OK] Writing to the SPI-NOR
> [OK] Doing all at the same time (once for TX and once for RX on UART)
>
> Notes:
> - Your Patches adding a maybe noise message "sdma firmware not ready".
> Maybe we should consider about that if it should be a warning or a info.
That means the script you're using is ram script which may not be loaded as your
case. That should be a warning I think, to avoid too much noise I have refine it
to dev_warn_once.
>
> - For spi-nor I did run this test:
> dd if=/dev/urandom of=/var/tmp/test1M bs=1M count=1 && \
> flashcp -v /var/tmp/test1M /dev/mtd2
>
> and checked /proc/interrupts:
> 25: 2107169 0 0 0 GPC 31
> Level 2008000.spi
>
> Testcase 2: "Using new FW from linux-firmware"
> ===
> [OK] Playing Audio (SSI)
> [OK] TX/RX bytes on a different UART (not the serial used for
> interaction)
> [OK] Writing to the SPI-NOR
> [OK] Doing all at the same time (once for TX and once for RX on UART)
>
> Notes:
> - For spi-nor I did run this test:
> dd if=/dev/urandom of=/var/tmp/test1M bs=1M count=1 && \
> flashcp -v /var/tmp/test1M /dev/mtd2
>
> and checked /proc/interrupts:
> 25: 2107993 0 0 0 GPC 31
> Level 2008000.spi
>
> I saw no SDMA interrupts during this testcase instead I saw only spi
> controller interrupts.
That's not expected. But I have tried just now and show that SDMA interrupt
caught by spi as belows. Are you sure sdma firmware loaded indeed?
./spidev_test -D /dev/spidev0.0 -s 1200000 -b 8 -S 512 -I 1 -l 8 -S 512 -I
spi mode: 0x24
bits per word: 8
max speed: 1200000 Hz (1200 kHz)
total: tx 0.5KB, rx 0.5KB
root@imx6qpdlsolox:~# cat /proc/interrupts | grep dma
58: 2 0 GPC 2 Level sdma
>
> - According linux-firmware you did a version bump from 3.5 to 4.5 but my
> dmesg shows:
> imx-sdma 20ec000.sdma: loaded firmware 3.5
3.x is used for i.mx6 family while 4.x is used for i.mx7/8 since there are some
change on ROM which depended by RAM script. Not means version bump
between 3.5/4.5. 3.5 is correct on i.mx6q.
>
> SPI Benchmark:
> ===
> flash_erase /dev/mtd2 0 0 && \
> dd if=/dev/urandom of=/dev/mtd2 bs=1M count=1
>
> - without firmware (ROM-FW)
> 1048576 bytes (1.0 MB, 1.0 MiB) copied, 51.9713 s, 20.2 kB/s
>
> - with firmware
> 1048576 bytes (1.0 MB, 1.0 MiB) copied, 59.4174 s, 17.6 kB/s
>
> Conclusion:
> ===
> It seems that we don't have any performance boost with your patchset instead
> we are increasing the complexity and the interrupts...
Yes, that's expected. What ERR009165 fix is data correct on spi bus though
that bring performance drop in dma mode, because the workaround just let
sdma do similar thing as cpu (PIO), while cpu running faster than sdma. If you
care much spi performance, PIO is better way. If care cpu loading, dma way
is better.
>
> Pls let me know if I did something wrong during testing or if my test setup was
> wrong. Note: the /dev/mtd2 isn't mainlined yet but if you use barebox you only
> have to add:
> 8<---------------------------------------------------------------------
> diff --git a/arch/arm/dts/imx6qdl-sabrelite.dtsi
> b/arch/arm/dts/imx6qdl-sabrelite.dtsi
> index ec3d364bde..256dd90a0f 100644
> --- a/arch/arm/dts/imx6qdl-sabrelite.dtsi
> +++ b/arch/arm/dts/imx6qdl-sabrelite.dtsi
> @@ -38,6 +38,11 @@
> label = "barebox-environment";
> reg = <0xe0000 0x20000>;
> };
> +
> + parition@100000 {
> + label = "user-partition";
> + reg = <0x100000 0x100000>;
> + };
> };
>
> &ocotp {
> 8<---------------------------------------------------------------------
> to the barebox device tree.
>
> [1]
> https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Flists.infra
> dead.org%2Fpipermail%2Flinux-mtd%2F2020-September%2F082099.html&am
> p;data=02%7C01%7Cyibin.gong%40nxp.com%7C324d4b5c2f2344883a3108d85
> 67166f9%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C63735439234
> 6471210&sdata=ru8fKz6wpDhzYeaHIT28T0OybHlCFHJ41N1lJYuqKgE%3D&
> amp;reserved=0
>
> Regards,
> Marco