The IPQ5018 is Qualcomm's 802.11ax SoC for Routers,
Gateways and Access Points.
This series adds minimal board boot support for ipq5018-mp03.1-c2 board.
Varadarajan Narayanan (7):
clk: qcom: clk-alpha-pll: Add support for Stromer PLLs
dt-bindings: arm64: ipq5018: Add binding descriptions for clock and
reset
clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018
dt-bindings: pinctrl: qcom: Add ipq5018 pinctrl bindings
pinctrl: qcom: Add IPQ5018 pinctrl driver
arm64: dts: Add ipq5018 SoC and MP03 board support
arm64: defconfig: Enable IPQ5018 SoC base configs
Documentation/devicetree/bindings/arm/qcom.yaml | 7 +
.../devicetree/bindings/clock/qcom,gcc.yaml | 3 +
.../bindings/pinctrl/qcom,ipq5018-pinctrl.yaml | 143 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts | 30 +
arch/arm64/boot/dts/qcom/ipq5018.dtsi | 201 +
arch/arm64/configs/defconfig | 3 +
drivers/clk/qcom/Kconfig | 8 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-alpha-pll.c | 156 +-
drivers/clk/qcom/clk-alpha-pll.h | 5 +
drivers/clk/qcom/gcc-ipq5018.c | 3833 ++++++++++++++++++++
drivers/pinctrl/qcom/Kconfig | 10 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-ipq5018.c | 903 +++++
include/dt-bindings/clock/qcom,gcc-ipq5018.h | 183 +
include/dt-bindings/reset/qcom,gcc-ipq5018.h | 119 +
include/linux/clk-provider.h | 4 +-
18 files changed, 5608 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-pinctrl.yaml
create mode 100644 arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts
create mode 100644 arch/arm64/boot/dts/qcom/ipq5018.dtsi
create mode 100644 drivers/clk/qcom/gcc-ipq5018.c
create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq5018.c
create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq5018.h
create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq5018.h
--
2.7.4
Add programming sequence support for managing the Stromer
PLLs.
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
drivers/clk/qcom/clk-alpha-pll.c | 156 ++++++++++++++++++++++++++++++++++++++-
drivers/clk/qcom/clk-alpha-pll.h | 5 ++
2 files changed, 160 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 26139ef..ce3257f 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -116,6 +116,19 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_OPMODE] = 0x38,
[PLL_OFF_ALPHA_VAL] = 0x40,
},
+
+ [CLK_ALPHA_PLL_TYPE_STROMER] = {
+ [PLL_OFF_L_VAL] = 0x08,
+ [PLL_OFF_ALPHA_VAL] = 0x10,
+ [PLL_OFF_ALPHA_VAL_U] = 0x14,
+ [PLL_OFF_USER_CTL] = 0x18,
+ [PLL_OFF_USER_CTL_U] = 0x1c,
+ [PLL_OFF_CONFIG_CTL] = 0x20,
+ [PLL_OFF_CONFIG_CTL_U] = 0xff,
+ [PLL_OFF_TEST_CTL] = 0x30,
+ [PLL_OFF_TEST_CTL_U] = 0x34,
+ [PLL_OFF_STATUS] = 0x28,
+ },
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
@@ -127,6 +140,8 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
#define ALPHA_BITWIDTH 32U
#define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH)
+#define PLL_STATUS_REG_SHIFT 8
+
#define PLL_HUAYRA_M_WIDTH 8
#define PLL_HUAYRA_M_SHIFT 8
#define PLL_HUAYRA_M_MASK 0xff
@@ -210,7 +225,7 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config)
{
- u32 val, mask;
+ u32 val, val_u, mask, mask_u;
regmap_write(regmap, PLL_L_VAL(pll), config->l);
regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
@@ -240,14 +255,143 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
mask |= config->pre_div_mask;
mask |= config->post_div_mask;
mask |= config->vco_mask;
+ mask |= config->alpha_en_mask;
+ mask |= config->alpha_mode_mask;
regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
+ /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */
+ val_u = config->status_reg_val << PLL_STATUS_REG_SHIFT;
+ val_u |= config->lock_det;
+
+ mask_u = config->status_reg_mask;
+ mask_u |= config->lock_det;
+
+ if (val_u != 0)
+ regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u);
+
+ if (config->test_ctl_val != 0)
+ regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
+
+ if (config->test_ctl_hi_val != 0)
+ regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
+
if (pll->flags & SUPPORTS_FSM_MODE)
qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
}
EXPORT_SYMBOL_GPL(clk_alpha_pll_configure);
+static unsigned long
+alpha_pll_stromer_calc_rate(u64 prate, u32 l, u64 a)
+{
+ return (prate * l) + ((prate * a) >> ALPHA_REG_BITWIDTH);
+}
+
+static unsigned long
+alpha_pll_stromer_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a)
+{
+ u64 remainder;
+ u64 quotient;
+
+ quotient = rate;
+ remainder = do_div(quotient, prate);
+ *l = quotient;
+
+ if (!remainder) {
+ *a = 0;
+ return rate;
+ }
+
+ quotient = remainder << ALPHA_REG_BITWIDTH;
+
+ remainder = do_div(quotient, prate);
+
+ if (remainder)
+ quotient++;
+
+ *a = quotient;
+ return alpha_pll_stromer_calc_rate(prate, *l, *a);
+}
+
+static unsigned long
+clk_alpha_pll_stromer_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ u32 l, low, high, ctl;
+ u64 a = 0, prate = parent_rate;
+ struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+
+ regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
+
+ regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
+ if (ctl & PLL_ALPHA_EN) {
+ regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low);
+ regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
+ &high);
+ a = (u64)high << ALPHA_BITWIDTH | low;
+ }
+
+ return alpha_pll_stromer_calc_rate(prate, l, a);
+}
+
+static int clk_alpha_pll_stromer_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ unsigned long rate = req->rate;
+ u32 l;
+ u64 a;
+
+ rate = alpha_pll_stromer_round_rate(rate, req->best_parent_rate, &l, &a);
+
+ return 0;
+}
+
+static int clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long prate)
+{
+ struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+ u32 l;
+ int ret;
+ u64 a;
+
+ rate = alpha_pll_stromer_round_rate(rate, prate, &l, &a);
+
+ /* Write desired values to registers */
+ regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
+ regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
+ regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
+ a >> ALPHA_BITWIDTH);
+
+ regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
+ PLL_ALPHA_EN, PLL_ALPHA_EN);
+
+ if (!clk_hw_is_enabled(hw))
+ return 0;
+
+ /* Stromer PLL supports Dynamic programming.
+ * It allows the PLL frequency to be changed on-the-fly without first
+ * execution of a shutdown procedure followed by a bring up procedure.
+ */
+
+ regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
+ PLL_UPDATE);
+ /* Make sure PLL_UPDATE request goes through */
+ mb();
+
+ /* Wait for PLL_UPDATE to be cleared */
+ ret = wait_for_pll_update(pll);
+ if (ret)
+ return ret;
+
+ /* Wait 11or more PLL clk_ref ticks[to be explored more on wait] */
+
+ /* Poll LOCK_DET for one */
+ ret = wait_for_pll_enable_lock(pll);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
{
int ret;
@@ -898,6 +1042,16 @@ const struct clk_ops clk_alpha_pll_hwfsm_ops = {
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
+const struct clk_ops clk_alpha_pll_stromer_ops = {
+ .enable = clk_alpha_pll_enable,
+ .disable = clk_alpha_pll_disable,
+ .is_enabled = clk_alpha_pll_is_enabled,
+ .recalc_rate = clk_alpha_pll_stromer_recalc_rate,
+ .determine_rate = clk_alpha_pll_stromer_determine_rate,
+ .set_rate = clk_alpha_pll_stromer_set_rate,
+};
+EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_ops);
+
const struct clk_ops clk_alpha_pll_fixed_trion_ops = {
.enable = clk_trion_pll_enable,
.disable = clk_trion_pll_disable,
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index d3201b8..3e25b1b 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -15,6 +15,7 @@ enum {
CLK_ALPHA_PLL_TYPE_FABIA,
CLK_ALPHA_PLL_TYPE_TRION,
CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
+ CLK_ALPHA_PLL_TYPE_STROMER,
CLK_ALPHA_PLL_TYPE_MAX,
};
@@ -121,6 +122,9 @@ struct alpha_pll_config {
u32 post_div_mask;
u32 vco_val;
u32 vco_mask;
+ u32 status_reg_val;
+ u32 status_reg_mask;
+ u32 lock_det;
};
extern const struct clk_ops clk_alpha_pll_ops;
@@ -129,6 +133,7 @@ extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
extern const struct clk_ops clk_alpha_pll_postdiv_ops;
extern const struct clk_ops clk_alpha_pll_huayra_ops;
extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;
+extern const struct clk_ops clk_alpha_pll_stromer_ops;
extern const struct clk_ops clk_alpha_pll_fabia_ops;
extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
--
2.7.4
Enables clk & pinctrl related configs
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
arch/arm64/configs/defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 6d04b95..ca25f79 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -473,6 +473,7 @@ CONFIG_PINCTRL_IMX8MQ=y
CONFIG_PINCTRL_IMX8QXP=y
CONFIG_PINCTRL_IMX8DXL=y
CONFIG_PINCTRL_IPQ8074=y
+CONFIG_PINCTRL_IPQ5018=y
CONFIG_PINCTRL_IPQ6018=y
CONFIG_PINCTRL_MSM8916=y
CONFIG_PINCTRL_MSM8994=y
@@ -851,6 +852,8 @@ CONFIG_QCOM_CLK_APCS_MSM8916=y
CONFIG_QCOM_CLK_SMD_RPM=y
CONFIG_QCOM_CLK_RPMH=y
CONFIG_IPQ_GCC_8074=y
+CONFIG_IPQ_GCC_5018=y
+CONFIG_IPQ_APSS_5018=y
CONFIG_IPQ_GCC_6018=y
CONFIG_MSM_GCC_8916=y
CONFIG_MSM_GCC_8994=y
--
2.7.4
This patch adds support for the global clock controller found on
the IPQ5018 based devices.
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
.../devicetree/bindings/clock/qcom,gcc.yaml | 3 +
include/dt-bindings/clock/qcom,gcc-ipq5018.h | 183 +++++++++++++++++++++
include/dt-bindings/reset/qcom,gcc-ipq5018.h | 119 ++++++++++++++
3 files changed, 305 insertions(+)
create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq5018.h
create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq5018.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
index ee0467f..74d67fc 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
@@ -18,6 +18,8 @@ description: |
- dt-bindings/clock/qcom,gcc-apq8084.h
- dt-bindings/reset/qcom,gcc-apq8084.h
- dt-bindings/clock/qcom,gcc-ipq4019.h
+ - dt-bindings/clock/qcom,gcc-ipq5018.h
+ - dt-bindings/reset/qcom,gcc-ipq5018.h
- dt-bindings/clock/qcom,gcc-ipq6018.h
- dt-bindings/reset/qcom,gcc-ipq6018.h
- dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
@@ -39,6 +41,7 @@ properties:
enum:
- qcom,gcc-apq8084
- qcom,gcc-ipq4019
+ - qcom,gcc-ipq5018
- qcom,gcc-ipq6018
- qcom,gcc-ipq8064
- qcom,gcc-msm8660
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq5018.h b/include/dt-bindings/clock/qcom,gcc-ipq5018.h
new file mode 100644
index 00000000..069165f
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-ipq5018.h
@@ -0,0 +1,183 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_5018_H
+#define _DT_BINDINGS_CLOCK_IPQ_GCC_5018_H
+
+#define GPLL0_MAIN 0
+#define GPLL0 1
+#define GPLL2_MAIN 2
+#define GPLL2 3
+#define GPLL4_MAIN 4
+#define GPLL4 5
+#define UBI32_PLL_MAIN 6
+#define UBI32_PLL 7
+#define APSS_AHB_CLK_SRC 9
+#define APSS_AHB_POSTDIV_CLK_SRC 10
+#define APSS_AXI_CLK_SRC 11
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC 12
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC 13
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC 14
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC 15
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC 16
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC 17
+#define BLSP1_UART1_APPS_CLK_SRC 18
+#define BLSP1_UART2_APPS_CLK_SRC 19
+#define CRYPTO_CLK_SRC 20
+#define GCC_APSS_AHB_CLK 23
+#define GCC_APSS_AXI_CLK 24
+#define GCC_BLSP1_AHB_CLK 25
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK 26
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK 27
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK 28
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK 29
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK 30
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK 31
+#define GCC_BLSP1_UART1_APPS_CLK 33
+#define GCC_BLSP1_UART2_APPS_CLK 34
+#define GCC_BTSS_LPO_CLK 36
+#define GCC_CMN_BLK_AHB_CLK 40
+#define GCC_CMN_BLK_SYS_CLK 41
+#define GCC_CRYPTO_AHB_CLK 44
+#define GCC_CRYPTO_AXI_CLK 45
+#define GCC_CRYPTO_CLK 46
+#define GCC_CRYPTO_PPE_CLK 47
+#define GCC_DCC_CLK 48
+#define GCC_GEPHY_RX_CLK 53
+#define GCC_GEPHY_TX_CLK 54
+#define GCC_GMAC0_CFG_CLK 55
+#define GCC_GMAC0_PTP_CLK 56
+#define GCC_GMAC0_RX_CLK 57
+#define GCC_GMAC0_SYS_CLK 58
+#define GCC_GMAC0_TX_CLK 59
+#define GCC_GMAC1_CFG_CLK 60
+#define GCC_GMAC1_PTP_CLK 61
+#define GCC_GMAC1_RX_CLK 62
+#define GCC_GMAC1_SYS_CLK 63
+#define GCC_GMAC1_TX_CLK 64
+#define GCC_GP1_CLK 65
+#define GCC_GP2_CLK 66
+#define GCC_GP3_CLK 67
+#define GCC_LPASS_CORE_AXIM_CLK 69
+#define GCC_LPASS_SWAY_CLK 70
+#define GCC_MDIO0_AHB_CLK 71
+#define GCC_MDIO1_AHB_CLK 72
+#define GCC_PCIE0_AHB_CLK 74
+#define GCC_PCIE0_AUX_CLK 75
+#define GCC_PCIE0_AXI_M_CLK 76
+#define GCC_PCIE0_AXI_S_BRIDGE_CLK 77
+#define GCC_PCIE0_AXI_S_CLK 78
+#define GCC_PCIE1_AHB_CLK 79
+#define GCC_PCIE1_AUX_CLK 80
+#define GCC_PCIE1_AXI_M_CLK 81
+#define GCC_PCIE1_AXI_S_BRIDGE_CLK 82
+#define GCC_PCIE1_AXI_S_CLK 83
+#define GCC_PRNG_AHB_CLK 84
+#define GCC_Q6_AXIM_CLK 85
+#define GCC_Q6_AXIM2_CLK 86
+#define GCC_Q6_AXIS_CLK 87
+#define GCC_Q6_AHB_CLK 88
+#define GCC_Q6_AHB_S_CLK 89
+#define GCC_Q6_TSCTR_1TO2_CLK 90
+#define GCC_Q6SS_ATBM_CLK 91
+#define GCC_Q6SS_PCLKDBG_CLK 92
+#define GCC_Q6SS_TRIG_CLK 93
+#define GCC_QDSS_AT_CLK 94
+#define GCC_QDSS_CFG_AHB_CLK 95
+#define GCC_QDSS_DAP_AHB_CLK 96
+#define GCC_QDSS_DAP_CLK 97
+#define GCC_QDSS_ETR_USB_CLK 98
+#define GCC_QDSS_EUD_AT_CLK 99
+#define GCC_QDSS_STM_CLK 100
+#define GCC_QDSS_TRACECLKIN_CLK 101
+#define GCC_QDSS_TSCTR_DIV8_CLK 102
+#define GCC_QPIC_AHB_CLK 103
+#define GCC_QPIC_CLK 104
+#define GCC_QPIC_IO_MACRO_CLK 105
+#define GCC_SDCC1_AHB_CLK 107
+#define GCC_SDCC1_APPS_CLK 108
+#define GCC_SLEEP_CLK_SRC 109
+#define GCC_SNOC_GMAC0_AHB_CLK 110
+#define GCC_SNOC_GMAC0_AXI_CLK 111
+#define GCC_SNOC_GMAC1_AHB_CLK 112
+#define GCC_SNOC_GMAC1_AXI_CLK 113
+#define GCC_SNOC_LPASS_AXIM_CLK 114
+#define GCC_SNOC_LPASS_SWAY_CLK 115
+#define GCC_SNOC_UBI0_AXI_CLK 118
+#define GCC_SYS_NOC_PCIE0_AXI_CLK 119
+#define GCC_SYS_NOC_PCIE1_AXI_CLK 120
+#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 121
+#define GCC_SYS_NOC_USB0_AXI_CLK 123
+#define GCC_SYS_NOC_WCSS_AHB_CLK 124
+#define GCC_UBI0_AXI_CLK 128
+#define GCC_UBI0_CFG_CLK 129
+#define GCC_UBI0_CORE_CLK 130
+#define GCC_UBI0_DBG_CLK 131
+#define GCC_UBI0_NC_AXI_CLK 132
+#define GCC_UBI0_UTCM_CLK 133
+#define GCC_UNIPHY_AHB_CLK 134
+#define GCC_UNIPHY_RX_CLK 135
+#define GCC_UNIPHY_SYS_CLK 136
+#define GCC_UNIPHY_TX_CLK 137
+#define GCC_USB0_AUX_CLK 138
+#define GCC_USB0_EUD_AT_CLK 139
+#define GCC_USB0_LFPS_CLK 140
+#define GCC_USB0_MASTER_CLK 141
+#define GCC_USB0_MOCK_UTMI_CLK 142
+#define GCC_USB0_PHY_CFG_AHB_CLK 143
+#define GCC_USB0_SLEEP_CLK 144
+#define GCC_WCSS_ACMT_CLK 145
+#define GCC_WCSS_AHB_S_CLK 146
+#define GCC_WCSS_AXI_M_CLK 147
+#define GCC_WCSS_AXI_S_CLK 148
+#define GCC_WCSS_DBG_IFC_APB_BDG_CLK 149
+#define GCC_WCSS_DBG_IFC_APB_CLK 150
+#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 151
+#define GCC_WCSS_DBG_IFC_ATB_CLK 152
+#define GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK 153
+#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 154
+#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 155
+#define GCC_WCSS_DBG_IFC_NTS_CLK 156
+#define GCC_WCSS_ECAHB_CLK 157
+#define GCC_XO_CLK 158
+#define GCC_XO_CLK_SRC 159
+#define GMAC0_RX_CLK_SRC 161
+#define GMAC0_TX_CLK_SRC 162
+#define GMAC1_RX_CLK_SRC 163
+#define GMAC1_TX_CLK_SRC 164
+#define GMAC_CLK_SRC 165
+#define GP1_CLK_SRC 166
+#define GP2_CLK_SRC 167
+#define GP3_CLK_SRC 168
+#define LPASS_AXIM_CLK_SRC 169
+#define LPASS_SWAY_CLK_SRC 170
+#define PCIE0_AUX_CLK_SRC 171
+#define PCIE0_AXI_CLK_SRC 172
+#define PCIE1_AUX_CLK_SRC 173
+#define PCIE1_AXI_CLK_SRC 174
+#define PCNOC_BFDCD_CLK_SRC 175
+#define Q6_AXI_CLK_SRC 176
+#define QDSS_AT_CLK_SRC 177
+#define QDSS_STM_CLK_SRC 178
+#define QDSS_TSCTR_CLK_SRC 179
+#define QDSS_TRACECLKIN_CLK_SRC 180
+#define QPIC_IO_MACRO_CLK_SRC 181
+#define SDCC1_APPS_CLK_SRC 182
+#define SYSTEM_NOC_BFDCD_CLK_SRC 184
+#define UBI0_AXI_CLK_SRC 185
+#define UBI0_CORE_CLK_SRC 186
+#define USB0_AUX_CLK_SRC 187
+#define USB0_LFPS_CLK_SRC 188
+#define USB0_MASTER_CLK_SRC 189
+#define USB0_MOCK_UTMI_CLK_SRC 190
+#define WCSS_AHB_CLK_SRC 191
+#define PCIE0_PIPE_CLK_SRC 192
+#define PCIE1_PIPE_CLK_SRC 193
+#define GCC_PCIE0_PIPE_CLK 194
+#define GCC_PCIE1_PIPE_CLK 195
+#define USB0_PIPE_CLK_SRC 196
+#define GCC_USB0_PIPE_CLK 197
+#define GMAC0_RX_DIV_CLK_SRC 198
+#define GMAC0_TX_DIV_CLK_SRC 199
+#define GMAC1_RX_DIV_CLK_SRC 200
+#define GMAC1_TX_DIV_CLK_SRC 201
+#endif
diff --git a/include/dt-bindings/reset/qcom,gcc-ipq5018.h b/include/dt-bindings/reset/qcom,gcc-ipq5018.h
new file mode 100644
index 00000000..cd9c4e1
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,gcc-ipq5018.h
@@ -0,0 +1,119 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _DT_BINDINGS_RESET_IPQ_GCC_5018_H
+#define _DT_BINDINGS_RESET_IPQ_GCC_5018_H
+
+#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 0
+#define GCC_BLSP1_BCR 1
+#define GCC_BLSP1_QUP1_BCR 2
+#define GCC_BLSP1_QUP2_BCR 3
+#define GCC_BLSP1_QUP3_BCR 4
+#define GCC_BLSP1_UART1_BCR 5
+#define GCC_BLSP1_UART2_BCR 6
+#define GCC_BOOT_ROM_BCR 7
+#define GCC_BTSS_BCR 8
+#define GCC_CMN_BLK_BCR 9
+#define GCC_CMN_LDO_BCR 10
+#define GCC_CE_BCR 11
+#define GCC_CRYPTO_BCR 12
+#define GCC_DCC_BCR 13
+#define GCC_DCD_BCR 14
+#define GCC_DDRSS_BCR 15
+#define GCC_EDPD_BCR 16
+#define GCC_GEPHY_BCR 17
+#define GCC_GEPHY_MDC_SW_ARES 18
+#define GCC_GEPHY_DSP_HW_ARES 19
+#define GCC_GEPHY_RX_ARES 20
+#define GCC_GEPHY_TX_ARES 21
+#define GCC_GMAC0_BCR 22
+#define GCC_GMAC0_CFG_ARES 23
+#define GCC_GMAC0_SYS_ARES 24
+#define GCC_GMAC1_BCR 25
+#define GCC_GMAC1_CFG_ARES 26
+#define GCC_GMAC1_SYS_ARES 27
+#define GCC_IMEM_BCR 28
+#define GCC_LPASS_BCR 29
+#define GCC_MDIO0_BCR 30
+#define GCC_MDIO1_BCR 31
+#define GCC_MPM_BCR 32
+#define GCC_PCIE0_BCR 33
+#define GCC_PCIE0_LINK_DOWN_BCR 34
+#define GCC_PCIE0_PHY_BCR 35
+#define GCC_PCIE0PHY_PHY_BCR 36
+#define GCC_PCIE0_PIPE_ARES 37
+#define GCC_PCIE0_SLEEP_ARES 38
+#define GCC_PCIE0_CORE_STICKY_ARES 39
+#define GCC_PCIE0_AXI_MASTER_ARES 40
+#define GCC_PCIE0_AXI_SLAVE_ARES 41
+#define GCC_PCIE0_AHB_ARES 42
+#define GCC_PCIE0_AXI_MASTER_STICKY_ARES 43
+#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 44
+#define GCC_PCIE1_BCR 45
+#define GCC_PCIE1_LINK_DOWN_BCR 46
+#define GCC_PCIE1_PHY_BCR 47
+#define GCC_PCIE1PHY_PHY_BCR 48
+#define GCC_PCIE1_PIPE_ARES 49
+#define GCC_PCIE1_SLEEP_ARES 50
+#define GCC_PCIE1_CORE_STICKY_ARES 51
+#define GCC_PCIE1_AXI_MASTER_ARES 52
+#define GCC_PCIE1_AXI_SLAVE_ARES 53
+#define GCC_PCIE1_AHB_ARES 54
+#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 55
+#define GCC_PCIE1_AXI_SLAVE_STICKY_ARES 56
+#define GCC_PCNOC_BCR 57
+#define GCC_PCNOC_BUS_TIMEOUT0_BCR 58
+#define GCC_PCNOC_BUS_TIMEOUT1_BCR 59
+#define GCC_PCNOC_BUS_TIMEOUT2_BCR 60
+#define GCC_PCNOC_BUS_TIMEOUT3_BCR 61
+#define GCC_PCNOC_BUS_TIMEOUT4_BCR 62
+#define GCC_PCNOC_BUS_TIMEOUT5_BCR 63
+#define GCC_PCNOC_BUS_TIMEOUT6_BCR 64
+#define GCC_PCNOC_BUS_TIMEOUT7_BCR 65
+#define GCC_PCNOC_BUS_TIMEOUT8_BCR 66
+#define GCC_PCNOC_BUS_TIMEOUT9_BCR 67
+#define GCC_PCNOC_BUS_TIMEOUT10_BCR 68
+#define GCC_PCNOC_BUS_TIMEOUT11_BCR 69
+#define GCC_PRNG_BCR 70
+#define GCC_Q6SS_DBG_ARES 71
+#define GCC_Q6_AHB_S_ARES 72
+#define GCC_Q6_AHB_ARES 73
+#define GCC_Q6_AXIM2_ARES 74
+#define GCC_Q6_AXIM_ARES 75
+#define GCC_Q6_AXIS_ARES 76
+#define GCC_QDSS_BCR 77
+#define GCC_QPIC_BCR 78
+#define GCC_QUSB2_0_PHY_BCR 79
+#define GCC_SDCC1_BCR 80
+#define GCC_SEC_CTRL_BCR 81
+#define GCC_SPDM_BCR 82
+#define GCC_SYSTEM_NOC_BCR 83
+#define GCC_TCSR_BCR 84
+#define GCC_TLMM_BCR 85
+#define GCC_UBI0_AXI_ARES 86
+#define GCC_UBI0_AHB_ARES 87
+#define GCC_UBI0_NC_AXI_ARES 88
+#define GCC_UBI0_DBG_ARES 89
+#define GCC_UBI0_UTCM_ARES 90
+#define GCC_UBI0_CORE_ARES 91
+#define GCC_UBI32_BCR 92
+#define GCC_UNIPHY_BCR 93
+#define GCC_UNIPHY_AHB_ARES 94
+#define GCC_UNIPHY_SYS_ARES 95
+#define GCC_UNIPHY_RX_ARES 96
+#define GCC_UNIPHY_TX_ARES 97
+#define GCC_USB0_BCR 98
+#define GCC_USB0_PHY_BCR 99
+#define GCC_WCSS_BCR 100
+#define GCC_WCSS_DBG_ARES 101
+#define GCC_WCSS_ECAHB_ARES 102
+#define GCC_WCSS_ACMT_ARES 103
+#define GCC_WCSS_DBG_BDG_ARES 104
+#define GCC_WCSS_AHB_S_ARES 105
+#define GCC_WCSS_AXI_M_ARES 106
+#define GCC_WCSS_AXI_S_ARES 107
+#define GCC_WCSS_Q6_BCR 108
+#define GCC_WCSSAON_RESET 109
+#define GCC_UNIPHY_SOFT_RESET 110
+#define GCC_GEPHY_MISC_ARES 111
+
+#endif
--
2.7.4
Add initial device tree support for the Qualcomm IPQ5018 SoC and
MP03.1-C2 board.
Signed-off-by: Varadarajan Narayanan <[email protected]>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 7 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts | 30 ++++
arch/arm64/boot/dts/qcom/ipq5018.dtsi | 201 ++++++++++++++++++++++++
4 files changed, 239 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts
create mode 100644 arch/arm64/boot/dts/qcom/ipq5018.dtsi
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 6031aee..694063f 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -28,6 +28,7 @@ description: |
apq8074
apq8084
apq8096
+ ipq5018
ipq6018
ipq8074
mdm9615
@@ -49,6 +50,7 @@ description: |
hk01
idp
liquid
+ mp03
mtp
qrd
sbc
@@ -142,6 +144,11 @@ properties:
- items:
- enum:
+ - qcom,ipq5018-mp03
+ - const: qcom,ipq5018
+
+ - items:
+ - enum:
- qcom,ipq8064-ap148
- const: qcom,ipq8064
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index d8f1466..3873970 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
+dtb-$(CONFIG_ARCH_QCOM) += ipq5018-mp03.1-c2.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb
diff --git a/arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts
new file mode 100644
index 00000000..41bb3b3
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * IPQ5018 CP01 board device tree source
+ *
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "ipq5018.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ5018/AP-MP03-C2";
+ compatible = "qcom,ipq5018-mp03", "qcom,ipq5018";
+
+ aliases {
+ serial0 = &blsp1_uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs-append = " swiotlb=1";
+ };
+};
+
+&blsp1_uart1 {
+ pinctrl-0 = <&serial_1_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+};
diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
new file mode 100644
index 00000000..12492a4
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * IPQ5018 SoC device tree source
+ *
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
+#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&intc>;
+
+ clocks {
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ #clock-cells = <0>;
+ };
+
+ xo: xo {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ #clock-cells = <0>;
+ };
+ };
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ enable-method = "psci";
+ reg = <0x1>;
+ next-level-cache = <&L2_0>;
+ };
+
+ L2_0: l2-cache {
+ compatible = "cache";
+ cache-level = <0x2>;
+ };
+ };
+
+ pmuv8: pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ psci: psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ tz: tz@4ac00000 {
+ reg = <0x0 0x4ac00000 0x0 0x00400000>;
+ no-map;
+ };
+ };
+
+ soc: soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+ dma-ranges;
+ compatible = "simple-bus";
+
+ tlmm: pinctrl@1000000 {
+ compatible = "qcom,ipq5018-pinctrl";
+ reg = <0x01000000 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&tlmm 0 80>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ serial_1_pins: serial1-pinmux {
+ pins = "gpio31", "gpio32", "gpio33", "gpio34";
+ function = "blsp1_uart1";
+ drive-strength = <8>;
+ bias-pull-down;
+ };
+ };
+
+ gcc: gcc@1800000 {
+ compatible = "qcom,gcc-ipq5018";
+ reg = <0x01800000 0x80000>;
+ clocks = <&xo>, <&sleep_clk>;
+ clock-names = "xo", "sleep_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ blsp1_uart1: serial@78af000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x078af000 0x200>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ intc: interrupt-controller@b000000 {
+ compatible = "qcom,msm-qgic2";
+ interrupt-controller;
+ #interrupt-cells = <0x3>;
+ reg = <0x0b000000 0x1000>, /*GICD*/
+ <0x0b002000 0x1000>, /*GICC*/
+ <0x0b001000 0x1000>, /*GICH*/
+ <0x0b004000 0x1000>; /*GICV*/
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ timer@b120000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x0b120000 0x1000>;
+ clock-frequency = <19200000>;
+
+ frame@b120000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0b121000 0x1000>,
+ <0x0b122000 0x1000>;
+ };
+
+ frame@b123000 {
+ frame-number = <1>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb123000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b124000 {
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0b124000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b125000 {
+ frame-number = <3>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0b125000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b126000 {
+ frame-number = <4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0b126000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b127000 {
+ frame-number = <5>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0b127000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b128000 {
+ frame-number = <6>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0b128000 0x1000>;
+ status = "disabled";
+ };
+ };
+ };
+};
--
2.7.4
On Mon, Sep 28, 2020 at 10:45:35AM +0530, Varadarajan Narayanan wrote:
> This patch adds support for the global clock controller found on
> the IPQ5018 based devices.
>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> ---
> .../devicetree/bindings/clock/qcom,gcc.yaml | 3 +
> include/dt-bindings/clock/qcom,gcc-ipq5018.h | 183 +++++++++++++++++++++
> include/dt-bindings/reset/qcom,gcc-ipq5018.h | 119 ++++++++++++++
> 3 files changed, 305 insertions(+)
> create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq5018.h
> create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq5018.h
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
> index ee0467f..74d67fc 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
> @@ -18,6 +18,8 @@ description: |
> - dt-bindings/clock/qcom,gcc-apq8084.h
> - dt-bindings/reset/qcom,gcc-apq8084.h
> - dt-bindings/clock/qcom,gcc-ipq4019.h
> + - dt-bindings/clock/qcom,gcc-ipq5018.h
> + - dt-bindings/reset/qcom,gcc-ipq5018.h
> - dt-bindings/clock/qcom,gcc-ipq6018.h
> - dt-bindings/reset/qcom,gcc-ipq6018.h
> - dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
> @@ -39,6 +41,7 @@ properties:
> enum:
> - qcom,gcc-apq8084
> - qcom,gcc-ipq4019
> + - qcom,gcc-ipq5018
> - qcom,gcc-ipq6018
> - qcom,gcc-ipq8064
> - qcom,gcc-msm8660
> diff --git a/include/dt-bindings/clock/qcom,gcc-ipq5018.h b/include/dt-bindings/clock/qcom,gcc-ipq5018.h
> new file mode 100644
> index 00000000..069165f
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,gcc-ipq5018.h
> @@ -0,0 +1,183 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
Only care about Linux and GPL OSs? And your employer is okay with GPL3
(and GPL4, ...)?
IOW, dual license please.
On Mon, Sep 28, 2020 at 10:45:39AM +0530, Varadarajan Narayanan wrote:
> Add initial device tree support for the Qualcomm IPQ5018 SoC and
> MP03.1-C2 board.
>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> ---
> Documentation/devicetree/bindings/arm/qcom.yaml | 7 +
Bindings and dts files should be separate patches.
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts | 30 ++++
> arch/arm64/boot/dts/qcom/ipq5018.dtsi | 201 ++++++++++++++++++++++++
> 4 files changed, 239 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts
> create mode 100644 arch/arm64/boot/dts/qcom/ipq5018.dtsi
>
> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
> index 6031aee..694063f 100644
> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
> @@ -28,6 +28,7 @@ description: |
> apq8074
> apq8084
> apq8096
> + ipq5018
> ipq6018
> ipq8074
> mdm9615
> @@ -49,6 +50,7 @@ description: |
> hk01
> idp
> liquid
> + mp03
> mtp
> qrd
> sbc
> @@ -142,6 +144,11 @@ properties:
>
> - items:
> - enum:
> + - qcom,ipq5018-mp03
> + - const: qcom,ipq5018
> +
> + - items:
> + - enum:
> - qcom,ipq8064-ap148
> - const: qcom,ipq8064
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index d8f1466..3873970 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
> dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += ipq5018-mp03.1-c2.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb
> diff --git a/arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts
> new file mode 100644
> index 00000000..41bb3b3
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts
> @@ -0,0 +1,30 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
Your employer is okay with GPL3 (and later)?
> +/*
> + * IPQ5018 CP01 board device tree source
> + *
> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
It's 2020.
> + */
> +
> +/dts-v1/;
> +
> +#include "ipq5018.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. IPQ5018/AP-MP03-C2";
> + compatible = "qcom,ipq5018-mp03", "qcom,ipq5018";
> +
> + aliases {
> + serial0 = &blsp1_uart1;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + bootargs-append = " swiotlb=1";
Not an upstream property.
> + };
> +};
> +
> +&blsp1_uart1 {
> + pinctrl-0 = <&serial_1_pins>;
> + pinctrl-names = "default";
> + status = "ok";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> new file mode 100644
> index 00000000..12492a4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> @@ -0,0 +1,201 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * IPQ5018 SoC device tree source
> + *
> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
> +#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&intc>;
> +
> + clocks {
Drop the container node.
> + sleep_clk: sleep-clk {
> + compatible = "fixed-clock";
> + clock-frequency = <32000>;
> + #clock-cells = <0>;
> + };
> +
> + xo: xo {
> + compatible = "fixed-clock";
> + clock-frequency = <24000000>;
> + #clock-cells = <0>;
> + };
> + };
> +
> + cpus: cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + };
> +
> + CPU1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + enable-method = "psci";
> + reg = <0x1>;
> + next-level-cache = <&L2_0>;
> + };
> +
> + L2_0: l2-cache {
> + compatible = "cache";
> + cache-level = <0x2>;
> + };
> + };
> +
> + pmuv8: pmu {
> + compatible = "arm,cortex-a53-pmu";
> + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
> + IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +
> + psci: psci {
Drop unused (and likely never needed) labels.
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + tz: tz@4ac00000 {
> + reg = <0x0 0x4ac00000 0x0 0x00400000>;
> + no-map;
> + };
> + };
> +
> + soc: soc {
soc@0
Build dtbs with W=1 and fix any warnings. This should be one.
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0 0xffffffff>;
> + dma-ranges;
> + compatible = "simple-bus";
> +
> + tlmm: pinctrl@1000000 {
> + compatible = "qcom,ipq5018-pinctrl";
> + reg = <0x01000000 0x300000>;
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&tlmm 0 80>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + serial_1_pins: serial1-pinmux {
> + pins = "gpio31", "gpio32", "gpio33", "gpio34";
> + function = "blsp1_uart1";
> + drive-strength = <8>;
> + bias-pull-down;
> + };
> + };
> +
> + gcc: gcc@1800000 {
clock-controller@...
> + compatible = "qcom,gcc-ipq5018";
> + reg = <0x01800000 0x80000>;
> + clocks = <&xo>, <&sleep_clk>;
> + clock-names = "xo", "sleep_clk";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + blsp1_uart1: serial@78af000 {
> + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> + reg = <0x078af000 0x200>;
> + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
> + <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "core", "iface";
> + status = "disabled";
> + };
> +
> + intc: interrupt-controller@b000000 {
> + compatible = "qcom,msm-qgic2";
> + interrupt-controller;
> + #interrupt-cells = <0x3>;
> + reg = <0x0b000000 0x1000>, /*GICD*/
> + <0x0b002000 0x1000>, /*GICC*/
> + <0x0b001000 0x1000>, /*GICH*/
> + <0x0b004000 0x1000>; /*GICV*/
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + timer {
Not memory mapped, move to top-level.
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> + };
> +
> + timer@b120000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + compatible = "arm,armv7-timer-mem";
> + reg = <0x0b120000 0x1000>;
> + clock-frequency = <19200000>;
> +
> + frame@b120000 {
> + frame-number = <0>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0b121000 0x1000>,
> + <0x0b122000 0x1000>;
> + };
> +
> + frame@b123000 {
> + frame-number = <1>;
> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0xb123000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@b124000 {
> + frame-number = <2>;
> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0b124000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@b125000 {
> + frame-number = <3>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0b125000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@b126000 {
> + frame-number = <4>;
> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0b126000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@b127000 {
> + frame-number = <5>;
> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0b127000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@b128000 {
> + frame-number = <6>;
> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0b128000 0x1000>;
> + status = "disabled";
> + };
> + };
> + };
No memory node...
Rob
> +};
> --
> 2.7.4
>
Can you check your get_maintainers script invocation? Not sure why arm64
maintainers are Cced on a clk patch.
Quoting Varadarajan Narayanan (2020-09-27 22:15:34)
> Add programming sequence support for managing the Stromer
> PLLs.
>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> ---
> drivers/clk/qcom/clk-alpha-pll.c | 156 ++++++++++++++++++++++++++++++++++++++-
> drivers/clk/qcom/clk-alpha-pll.h | 5 ++
> 2 files changed, 160 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index 26139ef..ce3257f 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -116,6 +116,19 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
> [PLL_OFF_OPMODE] = 0x38,
> [PLL_OFF_ALPHA_VAL] = 0x40,
> },
> +
Nitpick: Drop this newline.
> + [CLK_ALPHA_PLL_TYPE_STROMER] = {
> + [PLL_OFF_L_VAL] = 0x08,
> + [PLL_OFF_ALPHA_VAL] = 0x10,
> + [PLL_OFF_ALPHA_VAL_U] = 0x14,
> + [PLL_OFF_USER_CTL] = 0x18,
> + [PLL_OFF_USER_CTL_U] = 0x1c,
> + [PLL_OFF_CONFIG_CTL] = 0x20,
> + [PLL_OFF_CONFIG_CTL_U] = 0xff,
> + [PLL_OFF_TEST_CTL] = 0x30,
> + [PLL_OFF_TEST_CTL_U] = 0x34,
> + [PLL_OFF_STATUS] = 0x28,
> + },
> };
> EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
>
> @@ -127,6 +140,8 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
> #define ALPHA_BITWIDTH 32U
> #define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH)
>
> +#define PLL_STATUS_REG_SHIFT 8
This should have an ALPHA_ prefix.
> +
> #define PLL_HUAYRA_M_WIDTH 8
> #define PLL_HUAYRA_M_SHIFT 8
> #define PLL_HUAYRA_M_MASK 0xff
> @@ -240,14 +255,143 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
> mask |= config->pre_div_mask;
> mask |= config->post_div_mask;
> mask |= config->vco_mask;
> + mask |= config->alpha_en_mask;
> + mask |= config->alpha_mode_mask;
>
> regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
>
> + /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */
> + val_u = config->status_reg_val << PLL_STATUS_REG_SHIFT;
> + val_u |= config->lock_det;
> +
> + mask_u = config->status_reg_mask;
> + mask_u |= config->lock_det;
> +
> + if (val_u != 0)
if (val_u) is more canonical.
> + regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u);
> +
> + if (config->test_ctl_val != 0)
Same comment
> + regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
> +
> + if (config->test_ctl_hi_val != 0)
Same comment
> + regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
> +
> if (pll->flags & SUPPORTS_FSM_MODE)
> qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
> }
> EXPORT_SYMBOL_GPL(clk_alpha_pll_configure);
>
> +static unsigned long
> +alpha_pll_stromer_calc_rate(u64 prate, u32 l, u64 a)
> +{
> + return (prate * l) + ((prate * a) >> ALPHA_REG_BITWIDTH);
Is this not already in this file? Why can't we use
alpha_pll_calc_rate()?
> +}
> +
> +static unsigned long
> +alpha_pll_stromer_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a)
> +{
> + u64 remainder;
> + u64 quotient;
> +
> + quotient = rate;
> + remainder = do_div(quotient, prate);
> + *l = quotient;
> +
> + if (!remainder) {
> + *a = 0;
> + return rate;
> + }
> +
> + quotient = remainder << ALPHA_REG_BITWIDTH;
> +
> + remainder = do_div(quotient, prate);
> +
> + if (remainder)
> + quotient++;
> +
> + *a = quotient;
> + return alpha_pll_stromer_calc_rate(prate, *l, *a);
> +}
> +
> +static unsigned long
> +clk_alpha_pll_stromer_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> +{
> + u32 l, low, high, ctl;
> + u64 a = 0, prate = parent_rate;
> + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> +
> + regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
> +
> + regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
> + if (ctl & PLL_ALPHA_EN) {
> + regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low);
> + regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
> + &high);
> + a = (u64)high << ALPHA_BITWIDTH | low;
> + }
> +
> + return alpha_pll_stromer_calc_rate(prate, l, a);
> +}
> +
> +static int clk_alpha_pll_stromer_determine_rate(struct clk_hw *hw,
> + struct clk_rate_request *req)
> +{
> + unsigned long rate = req->rate;
> + u32 l;
> + u64 a;
> +
> + rate = alpha_pll_stromer_round_rate(rate, req->best_parent_rate, &l, &a);
Why assign to rate if nobody is going to look at it? Should probably be
set to req->rate instead?
> +
> + return 0;
> +}
> +
> +static int clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long prate)
> +{
> + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> + u32 l;
> + int ret;
> + u64 a;
> +
> + rate = alpha_pll_stromer_round_rate(rate, prate, &l, &a);
> +
> + /* Write desired values to registers */
Please drop this useless comment.
> + regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
> + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
> + regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
> + a >> ALPHA_BITWIDTH);
> +
> + regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
> + PLL_ALPHA_EN, PLL_ALPHA_EN);
> +
> + if (!clk_hw_is_enabled(hw))
> + return 0;
> +
> + /* Stromer PLL supports Dynamic programming.
The /* goes on a line by itself.
> + * It allows the PLL frequency to be changed on-the-fly without first
> + * execution of a shutdown procedure followed by a bring up procedure.
> + */
Cool feature. Maybe that can go into the header file though?
> +
> + regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
> + PLL_UPDATE);
> + /* Make sure PLL_UPDATE request goes through */
> + mb();
regmap APIs already have memory barriers so this isn't needed?
> +
> + /* Wait for PLL_UPDATE to be cleared */
I think the code already says this so we can just drop this comment.
> + ret = wait_for_pll_update(pll);
> + if (ret)
> + return ret;
> +
> + /* Wait 11or more PLL clk_ref ticks[to be explored more on wait] */
> +
Is this a TODO?
> + /* Poll LOCK_DET for one */
I think the code already says this so we can just drop this comment.
> + ret = wait_for_pll_enable_lock(pll);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +
> static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
> {
> int ret;
Hi, are you going to resubmit this patch? Looks like MDM9607 uses Stromer PLL for its CPU clocks and could benefit from it.
Konrad
On Sat, Dec 26, 2020 at 01:51:28AM +0100, Konrad Dybcio wrote:
Konrad,
> Hi, are you going to resubmit this patch? Looks like
> MDM9607 uses Stromer PLL for its CPU clocks and could
> benefit from it.
Yes. But will take some time since we are held up with
additional activities.
Thanks
Varada
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
On Mon 28 Sep 00:15 CDT 2020, Varadarajan Narayanan wrote:
> Add initial device tree support for the Qualcomm IPQ5018 SoC and
> MP03.1-C2 board.
>
> Signed-off-by: Varadarajan Narayanan <[email protected]>
> ---
> Documentation/devicetree/bindings/arm/qcom.yaml | 7 +
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts | 30 ++++
> arch/arm64/boot/dts/qcom/ipq5018.dtsi | 201 ++++++++++++++++++++++++
> 4 files changed, 239 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts
> create mode 100644 arch/arm64/boot/dts/qcom/ipq5018.dtsi
>
> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
> index 6031aee..694063f 100644
> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
> @@ -28,6 +28,7 @@ description: |
> apq8074
> apq8084
> apq8096
> + ipq5018
> ipq6018
> ipq8074
> mdm9615
> @@ -49,6 +50,7 @@ description: |
> hk01
> idp
> liquid
> + mp03
> mtp
> qrd
> sbc
> @@ -142,6 +144,11 @@ properties:
>
> - items:
> - enum:
> + - qcom,ipq5018-mp03
> + - const: qcom,ipq5018
> +
> + - items:
> + - enum:
> - qcom,ipq8064-ap148
> - const: qcom,ipq8064
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index d8f1466..3873970 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
> dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += ipq5018-mp03.1-c2.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a3u-eur.dtb
> diff --git a/arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts
> new file mode 100644
> index 00000000..41bb3b3
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts
> @@ -0,0 +1,30 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * IPQ5018 CP01 board device tree source
> + *
> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "ipq5018.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. IPQ5018/AP-MP03-C2";
> + compatible = "qcom,ipq5018-mp03", "qcom,ipq5018";
> +
> + aliases {
> + serial0 = &blsp1_uart1;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + bootargs-append = " swiotlb=1";
> + };
> +};
> +
> +&blsp1_uart1 {
> + pinctrl-0 = <&serial_1_pins>;
> + pinctrl-names = "default";
> + status = "ok";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> new file mode 100644
> index 00000000..12492a4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
> @@ -0,0 +1,201 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * IPQ5018 SoC device tree source
> + *
> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
> +#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + interrupt-parent = <&intc>;
> +
> + clocks {
> + sleep_clk: sleep-clk {
> + compatible = "fixed-clock";
> + clock-frequency = <32000>;
> + #clock-cells = <0>;
> + };
> +
> + xo: xo {
> + compatible = "fixed-clock";
> + clock-frequency = <24000000>;
> + #clock-cells = <0>;
> + };
> + };
> +
> + cpus: cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + };
> +
> + CPU1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + enable-method = "psci";
> + reg = <0x1>;
> + next-level-cache = <&L2_0>;
> + };
> +
> + L2_0: l2-cache {
> + compatible = "cache";
> + cache-level = <0x2>;
> + };
> + };
> +
> + pmuv8: pmu {
> + compatible = "arm,cortex-a53-pmu";
> + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
> + IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +
> + psci: psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + tz: tz@4ac00000 {
> + reg = <0x0 0x4ac00000 0x0 0x00400000>;
> + no-map;
> + };
> + };
> +
> + soc: soc {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0 0 0xffffffff>;
> + dma-ranges;
You can't have an empty dma-ranges when the bus and the parent node has
different #address/size-cells.
See 77e9c198b155 ("arm64: dts: qcom: clear the warnings caused by empty dma-ranges")
> + compatible = "simple-bus";
> +
> + tlmm: pinctrl@1000000 {
> + compatible = "qcom,ipq5018-pinctrl";
> + reg = <0x01000000 0x300000>;
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&tlmm 0 80>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + serial_1_pins: serial1-pinmux {
> + pins = "gpio31", "gpio32", "gpio33", "gpio34";
> + function = "blsp1_uart1";
> + drive-strength = <8>;
> + bias-pull-down;
> + };
> + };
> +
> + gcc: gcc@1800000 {
> + compatible = "qcom,gcc-ipq5018";
> + reg = <0x01800000 0x80000>;
> + clocks = <&xo>, <&sleep_clk>;
> + clock-names = "xo", "sleep_clk";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + blsp1_uart1: serial@78af000 {
> + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> + reg = <0x078af000 0x200>;
> + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
> + <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "core", "iface";
> + status = "disabled";
> + };
> +
> + intc: interrupt-controller@b000000 {
> + compatible = "qcom,msm-qgic2";
> + interrupt-controller;
> + #interrupt-cells = <0x3>;
> + reg = <0x0b000000 0x1000>, /*GICD*/
> + <0x0b002000 0x1000>, /*GICC*/
> + <0x0b001000 0x1000>, /*GICH*/
> + <0x0b004000 0x1000>; /*GICV*/
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + timer {
This isn't a mmio device, so move it outside /soc
Thanks,
Bjorn
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> + };
> +
> + timer@b120000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + compatible = "arm,armv7-timer-mem";
> + reg = <0x0b120000 0x1000>;
> + clock-frequency = <19200000>;
> +
> + frame@b120000 {
> + frame-number = <0>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0b121000 0x1000>,
> + <0x0b122000 0x1000>;
> + };
> +
> + frame@b123000 {
> + frame-number = <1>;
> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0xb123000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@b124000 {
> + frame-number = <2>;
> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0b124000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@b125000 {
> + frame-number = <3>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0b125000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@b126000 {
> + frame-number = <4>;
> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0b126000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@b127000 {
> + frame-number = <5>;
> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0b127000 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@b128000 {
> + frame-number = <6>;
> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0b128000 0x1000>;
> + status = "disabled";
> + };
> + };
> + };
> +};
> --
> 2.7.4
>